TWI311345B - Electronic device module package structure and method of making the same - Google Patents

Electronic device module package structure and method of making the same Download PDF

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Publication number
TWI311345B
TWI311345B TW095108263A TW95108263A TWI311345B TW I311345 B TWI311345 B TW I311345B TW 095108263 A TW095108263 A TW 095108263A TW 95108263 A TW95108263 A TW 95108263A TW I311345 B TWI311345 B TW I311345B
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TW
Taiwan
Prior art keywords
electronic component
substrate
pads
conductive
electronic
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TW095108263A
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Chinese (zh)
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TW200735234A (en
Inventor
Shui-Ching Lee
Hui-Chin Fang
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Advanced Semiconductor Eng
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Priority to TW095108263A priority Critical patent/TWI311345B/en
Publication of TW200735234A publication Critical patent/TW200735234A/en
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Publication of TWI311345B publication Critical patent/TWI311345B/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

1311345 f 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種電子元件模組封裝結構(Electr〇nic device =〇dule package structure)及其製程。並且特別地,本發明是關於 一種具有電磁遮蔽(Electro-magnetic shielding)效果的電子元件揲 組封裝結構及其製程。 【先前技術】 • 電磁干擾(Electr_gnetic interference, EM)係一欲接收的電 磁信號受到一電磁體之擾亂所造成之損壞。每一電子元件 (^ctmnic device)使用一電流供其運作,該電流周圍環繞一電磁 場。該環繞之電磁場會對其周圍内之電子元件產生充分之干擾致 使該等電子元件之效能受到削減。另外,因現代各式電子產品使 用頻繁,外在環境充斥各種來源之電磁波,足以干擾電子元件之 正常運作。因此,如何保護電子元件不受電磁干擾便為一值得研 究及解決的問題。 請參閱圖一,圖一係關於先前技術之一電子元件模組1〇之 * —剖面視圖。該電子元件模組包含-基板(SUbstrate)l2以及至 少-電子餅14。圖-中騎示出兩個電子元件14做為代表。 該ίΪ子凡件14可能包含晶片(Ch⑹、電阻器(Resistor)、電容器 電容器(Capacitor)、電感器、二極體(Di〇de)或是限流器 (Bead) ° 該基板12具有-上表面122以及複數個形成於該上表面上 之接塾_)124。該每-個電子元件14侧定於該基板之上表面 122上’並且係接合於該等接墊124中之若干接墊124。 該電子猶模組10上之該每一個電子元件14係外露,所以 5 1311345 未受到任何外在裝置保護。 顯見地,該電子元件模組1G並 ί二件易,辦,該電子元4=以; 能便會勺磁干擾。_,該電子元件14之效 此便會又到影響,並且影響電子元件模組1〇之正常運作。(效 環境=磁易受外在 能,便為-值得研究暨解決的問^持電子州吴組正常的運作效 【發明内容】 造方提供一種電子元件模組封裝結構及其製 並包ί據ΐί明Ϊ:較i圭ΐ體實施例之電子元件模組封裝· C〇nduCtive d-ice). 成於該上表面上之接墊。該每一個導電個形 致使該每-個導電元件^該至少-導電元件, 材料之一表面,並且接觸該每',盖該成型封裝 根據本發明之一較佳具體實施例 法,首先,根據本發明之較佳具體實施例的以=構的J 中該基板具有一上表面以及複數個形成 品 土板。其 著’根據本發明之較佳具體實施例的方^將至少4=件= 1311345 及至少-導電元件固定於該基板之上表面上。其中該每—個 元件係接合於該等接墊中之若干接墊,並且該每一個導電元: 接^於該等接墊中之一接墊,該個接墊將被電連接至一接地 接著,根據本發明之較佳具體實施例的方法係將一封裝材 於該基板之上表面上,以覆蓋該至少一電子元件以及該至少 電元件’致使該每-個導電元件外露其頂部。最後,根據本 之較佳具體實施_方法係將-導電層覆蓋該已成型騎裝^ 之一表面,並且接觸該每一個導電元件之頂部,進而完 元件模組封裝結構。 / ,於本發明之優點與精神可以藉由以下的發明詳述及所附圖 式付到進一步的瞭解。 【實施方式】 之二圖二a至圖二旧會示出根據本發明 幸乂佳具體實施例之製造電子元件模組封裝結構的方法。 苦止如t a所示,娜本發明之紐频實施儀製造方法, 形成於該接二板22具有-上表面222以及複數個 接^ ’根據本發明之較佳具體實施例的製造方法係將至少一 於該基板22之上表面222上,其中該每一個電 ^ 接於該等接墊224中之若干接塾224,如圖二B所 不圖一 B中僅繪示出兩個電子元件24做為代表。 以體實施财,鱗電子元件24中之—個電子元件可 片,^'器、一電容15、一電感器、一二極體、-限流器或是 a曰月。 接著,根據本發明之較佳具體實施例的製造方法係將至少一 1311345 導電元件26固定於該基板22之上表面222上,如圖二c所示。 其中該每一導電元件26係接合於該等接墊224中之一個接墊 224,並且特別地,該接墊224將被電連接至一接地端(未顯示)。 於一具體實施例中,該每一個導電元件26係由一金屬(例 如’銅)所形成。例如,該導電元件26可為一事先缚 銅 柱,但不以此為限。 接著,根據本發明之較佳具體實施例的製造方法係 材料28成型於該基板22之上表面222上,以覆蓋該至少一 ίΪΓ/及該至少—導電元件26,致使該每—個導電元件26外 露其頂部’如圖^一 D所不。 材料3 I體實 1,例中’該封裝材料28係一固態環氧樹脂模封 材枓(Epoxy m〇ldmg comp〇und,EMC)或一液態 encapsulation material)。 刊貝屮iquia 方、E所示’根據本發明之較佳具體實施例的製造 且覆蓋該已成型的封裝材料28之—表面,並 =構 =:峨树26爛,娜顧子元件模組 成 於-具體實酬巾,鱗電層29係由-金細如,銅)所形 塗 佈製程、-蒸鍍製程、 心-周緣。在圖三;具:圖成封裝材料 樣_二”麟解搞其同 8 1311345 再睛參閱圖二E,圖二E即為根據本發 例之-電子元件模組封裝結構2G的截面視圖月較佳,、體實知 本發明之較佳具體實施例之電子元件模 -基板22、至少—導電树26、至少、子^冓20包各 料28以及-導電層29。圖二24、一封裝材 代表。 〒僅、'、曰不出兩個電子元件24做為 該基板22具有一上表面222 之接墊224。 以及複數個形成於該上表面上 - 電元件26係固跋該基板22之上表面222上。 母:個導電元件26係接合至該等接塾224中之一個接塾22心 且特別地’該個接塾224將被電連接至一接地端(未顯示)。並 =-具體實施例中,該每—個導電元件26係由—金屬 $ ’銅)所形成。例如,該導電元件26可為一事先禱造成^ 柱’但不以此為限。 〜列 、該每一個電子元件24係固定於該基板22之上表面222上, 並且係接合於該等接墊224中之若干接墊224。 。於一具體實施例中,該至少一電子元件24包含選自由—電 阻器、一電容器、一電感器、一二極體、一限流器以及一晶片所 組成之一群組中之一電子元件24。 ^該封裝材料28係成型於該基板22之上表面222上,進而覆 蓋該至少一電子元件24以及該至少一導電元件26,致使該每— 個導電元件26外露其頂部。 於一具體實施例中’該封裝材料28係一固態環氧樹脂模封 材料或一液態封裝材質。 、 1311345 且接 。於一具體實施例中’該導電層29係由—金屬(例如, 成 鋼)所形 於另—具體實施例令,繪泉 構20之該導電層29係形成並且=電子元件魅封裝結 一周緣。在圖三中具有盥圖二〜成垔的封裴材料28之 行圖二£丨㈣解搞科其同樣執 所每-_子元件係外露, 電子元件额之正常運^件之效錢會受聰響,並且影響 相較於先前技藝,本發明之較 封裝結構巾,絲-個電子元純‘體^狀電子元件模組 用至少-導電元件以接並且利 構,於運作中可減少模組_之 封裝結 維持電子元件模組之正常運作。H電磁干擾之機會’進而 發明具體5例之詳述,係希望能更加清楚描述本 上述所揭露的較佳具體實施例來對 及L月_。相反地,其目的是希望能涵蓋各種改變 此排於本發明所欲申請之專利範圍的範嘴内。因 ΐϋϊ明請之專利範圍的麟應該根據上述的說明作最寬 廣的解釋,以致使其涵蓋所有可能的改變以及具相等性的安排。 1311345 【圖式簡單說明】 圖一係先前技術之電子元件模組之一剖面視圖。 工-,二A至圖二£繪示根據本發明之一較佳具體實施例之一電 子凡件杈組封裝結構的製造方法。 圖二係根據本發明之另 裝結構的剖面視圖。 一較佳具體實施例之| 【主要元件符號說明】 :電子元件模組 12 .基板 122 ·上表面 124 :接墊 14 :電子元件 20 :電子元件模 22 ·基板 222 .上表面 224 =接墊 24 :電子元件 26 :導電元件 28 :封裝材料 29 :導電層 111311345 f IX. Description of the Invention: [Technical Field] The present invention relates to an electronic component module package structure (Electr〇nic device = 〇dule package structure) and a process thereof. In particular, the present invention relates to an electronic component package structure having an electro-magnetic shielding effect and a process thereof. [Prior Art] • Electromagnetic interference (EM) is the damage of an electromagnetic signal to be received by an electromagnet. Each electronic component (^ctmnic device) uses a current for its operation, which surrounds an electromagnetic field. The surrounding electromagnetic field will cause sufficient interference with the electronic components in its surroundings to cause the performance of the electronic components to be reduced. In addition, due to the frequent use of modern electronic products, the external environment is filled with electromagnetic waves of various sources, which is enough to interfere with the normal operation of electronic components. Therefore, how to protect electronic components from electromagnetic interference is a problem worth studying and solving. Referring to FIG. 1, FIG. 1 is a cross-sectional view of a prior art electronic component module. The electronic component module includes a substrate (substrate) 12 and at least an electronic cake 14. The figure-middle shows two electronic components 14 as representative. The substrate 14 may include a chip (Ch (6), a resistor (Resistor), a capacitor capacitor (Capacitor), an inductor, a diode (Di〇de), or a current limiter (Bead). The substrate 12 has - The surface 122 and a plurality of interfaces _) 124 formed on the upper surface. Each of the electronic components 14 is disposed on the upper surface 122 of the substrate and is coupled to a plurality of pads 124 of the pads 124. Each of the electronic components 14 on the electronic module 10 is exposed, so that 5 1311345 is not protected by any external device. Obviously, the electronic component module 1G is easy to handle, and the electronic component 4=is; _, the effect of the electronic component 14 will be affected again, and affect the normal operation of the electronic component module 1 . (Effective environment = magnetic vulnerability to external energy, it is - worthy of research and solution) ^ The normal operation of the electronic state Wu group [invention content] The manufacturer provides an electronic component module packaging structure and its package According to ΐί明Ϊ: The electronic component module package of the embodiment of the invention is C〇nduCtive d-ice. The pad formed on the upper surface. Each of the conductive shapes causes the at least one conductive element to be at least one of the surface of the conductive member, and contact the molded package according to a preferred embodiment of the present invention. First, according to In a preferred embodiment of the invention, the substrate has an upper surface and a plurality of formed soil panels. In accordance with a preferred embodiment of the present invention, at least 4 = member = 1311345 and at least - a conductive member is attached to the upper surface of the substrate. Each of the components is bonded to a plurality of pads of the pads, and each of the conductive elements is connected to one of the pads, and the pads are electrically connected to a ground. Next, a method in accordance with a preferred embodiment of the present invention places a package on the upper surface of the substrate to cover the at least one electronic component and the at least electrical component' such that each of the conductive components exposes its top. Finally, in accordance with a preferred embodiment of the present invention, a method of covering a surface of the formed rider with a conductive layer and contacting the top of each of the conductive members completes the component package structure. The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings. [Embodiment] FIG. 2 a to FIG. 2 will show a method of manufacturing an electronic component module package structure according to a preferred embodiment of the present invention. As shown in ta, the manufacturing method of the invention is formed on the second plate 22 having an upper surface 222 and a plurality of manufacturing methods according to a preferred embodiment of the present invention. At least one of the upper surface 222 of the substrate 22, wherein each of the plurality of interfaces 224 electrically connected to the pads 224, as shown in FIG. 2B, FIG. 24 as a representative. In the implementation of the body, the electronic component of the scale electronic component 24 can be a chip, a capacitor, a capacitor 15, an inductor, a diode, a current limiter or a month. Next, in accordance with a preferred embodiment of the present invention, at least one of the 1311345 conductive elements 26 is secured to the upper surface 222 of the substrate 22, as shown in Figure 2c. Each of the conductive elements 26 is bonded to one of the pads 224, and in particular, the pads 224 are electrically connected to a ground (not shown). In one embodiment, each of the electrically conductive elements 26 is formed from a metal such as 'copper. For example, the conductive element 26 can be a pre-bonded copper post, but is not limited thereto. Next, a manufacturing method according to a preferred embodiment of the present invention is formed on the upper surface 222 of the substrate 22 to cover the at least one/and at least-conductive elements 26, such that each of the conductive elements 26 exposed its top 'as shown in Figure ^1 D. Material 3 I. In the example, the encapsulating material 28 is a solid epoxy resin molding material (Epoxy m〇ldmg comp〇und, EMC) or a liquid encapsulation material. Published by Equia, E, according to a preferred embodiment of the present invention, which covers and covers the surface of the formed encapsulating material 28, and = structure =: 峨树26 烂,娜顾子元件模块In the form of a concrete towel, the scale layer 29 is made of - gold fine, copper) coating process, - evaporation process, heart - circumference. In the figure 3; with: the picture into the package material sample _ two" Lin Jie engages its same 8 1311345 and then see Figure 2E, Figure 2E is the cross-sectional view month of the electronic component module package structure 2G according to the present example Preferably, the electronic component die-substrate 22 of the preferred embodiment of the present invention, at least the conductive tree 26, at least the sub-package 28 and the conductive layer 29 are shown. Figure 2, Figure 24. The package material represents: 〒 only, ', two electronic components 24 are not provided as the substrate 22 has a pad 224 of an upper surface 222. And a plurality of electrodes 224 are formed on the upper surface - the electrical component 26 is fixed to the substrate 22 above surface 222. Female: A conductive element 26 is bonded to one of the ports 22 of the ports 224 and in particular 'the port 224 will be electrically connected to a ground (not shown). And in the specific embodiment, each of the conductive elements 26 is formed of - metal $ 'copper. For example, the conductive element 26 may be a prior prayer to cause a column 'but not limited thereto. Each of the electronic components 24 is fixed on the upper surface 222 of the substrate 22 and is coupled to the pads 224. a plurality of pads 224. In one embodiment, the at least one electronic component 24 comprises a group selected from the group consisting of: a resistor, a capacitor, an inductor, a diode, a current limiter, and a wafer. One of the electronic components 24 in the group. The encapsulating material 28 is formed on the upper surface 222 of the substrate 22 to cover the at least one electronic component 24 and the at least one conductive component 26, such that each of the conductive components 26 is exposed. In a specific embodiment, the encapsulating material 28 is a solid epoxy resin molding material or a liquid encapsulating material. 1311345 is connected. In a specific embodiment, the conductive layer 29 is made of metal ( For example, Chenggang) is formed in another embodiment, and the conductive layer 29 of the soldering structure 20 is formed and = the electronic component is encapsulated with a peripheral edge. In FIG. 3, there is a seal of FIG. Figure 28 of the material 28 diagram (4) to solve the problem of the same implementation of the _ sub-components exposed, the cost of the normal components of the electronic components will be affected, and the impact compared to the prior art, the present invention Compared to the package structure towel, silk The electronic element pure 'body ^ electronic component module uses at least the conductive element to connect and construct, in operation, the module can be reduced to maintain the normal operation of the electronic component module. The opportunity of H electromagnetic interference is further invented The detailed description of the specific examples of the present invention is intended to provide a clearer description of the preferred embodiments disclosed herein, and to the extent that it is intended to cover various modifications. Within the scope of the patent scope, the scope of the patent scope should be interpreted broadly according to the above description so that it covers all possible changes and arrangements of equality. 1311345 [Simple diagram] A cross-sectional view of a prior art electronic component module. A second embodiment of the present invention is directed to a method of fabricating an electronic component package structure in accordance with a preferred embodiment of the present invention. Figure 2 is a cross-sectional view of an alternative structure in accordance with the present invention. A preferred embodiment | [Major component symbol description]: electronic component module 12. Substrate 122 · Upper surface 124 : Pad 14 : Electronic component 20 : Electronic component die 22 · Substrate 222 . Upper surface 224 = pad 24: electronic component 26: conductive component 28: encapsulation material 29: conductive layer 11

Claims (1)

1311345 十、申請專利範圍: 1、 一種電子元件模組封裝結構(Electronic device module package structure),包含: 一基板(Substrate),該基板具有一上表面以及複數個形成於該 上表面上之接塾(Pad); 至乂 導電元件(Electrically conductive device),該每一個導 電元件係固定於該基板之上表面上並且係接合至該等接墊 中之一接墊,其中該接墊係電連接至一接地端; 至少一電子元件(Electronic device),該每一個電子元件係固定 於該基板之上表面上並且係電性連接於該等接墊中之若 接墊; 一封裝材料(Package material),該封裝材料係成型於該基板 上表面上,且覆蓋該至少-電子元件以及該至少一 件,其中該每一個導電元件外露其頂部;以及 2、 3、 4、 5、 ec)nduetive layef) ’ 該導謂係覆蓋該成 如由材料之—表面並且接觸該每—個導電元件之頂部。 專利麵⑹項所述之電子元件模組雜結構,_該 3-電子元件包含選自由一電阻器(Resistor)、」電容器 (BeaS- . 11 元触繼構,其中該每 =====所狀電子元件·«結構,其中該導 二專所述 程所形成。 羔鍍製耘或一印刷製 構,其t該封 科戈-㈣·_iquid eneap=:=^ _P_d’ 12 6、 1311345 第1項所述之電子元件模組封裝結構,其中該導 電層係覆蓋该已成型的封裳材料之一周緣。 -# t ^ - t -f it # ^ ^ ^ ^ ^ ^ (Electronic device module package structure)之方法,該方法包含下列步驟: 製備^基板(Substrate) ’其中該基板具有一上表面以及複數個 形成於該上表面上之接墊(pad);1311345 X. Patent application scope: 1. An electronic device module package structure, comprising: a substrate having an upper surface and a plurality of interfaces formed on the upper surface (Pad); an electrically conductive device, each of the conductive elements being fixed on an upper surface of the substrate and bonded to one of the pads, wherein the pad is electrically connected to a grounding end; at least one electronic device, each of the electronic components is fixed on the upper surface of the substrate and electrically connected to the pads in the pads; a packaging material Forming the encapsulating material on the upper surface of the substrate and covering the at least-electronic component and the at least one piece, wherein each of the conductive elements exposes a top portion thereof; and 2, 3, 4, 5, ec) nduetive layef) The guide covers the surface of the material and contacts the top of each of the conductive elements. The electronic component module hybrid structure described in the item (6), wherein the 3-electronic component comprises a resistor (Resistor), a capacitor (BeaS-.11 element touch structure, wherein each ===== The electronic component «structure, which is formed by the process of the second guide. Lamb plating or a printing structure, which is the seal of the Kogo-(four)·_iquid eneap=:=^ _P_d' 12 6, 1311345 The electronic component module package structure according to Item 1, wherein the conductive layer covers a periphery of the formed sealing material. -# t ^ - t -f it # ^ ^ ^ ^ ^ ^ (Electronic device module a method of package structure, the method comprising the steps of: preparing a substrate [Substrate] wherein the substrate has an upper surface and a plurality of pads formed on the upper surface; 固疋至少一電子元件(Eiectr〇nic device)以及至少一導電元件 ^Electrically conductive device)於該基板之上表面上,其中 该,一個電子元件係接合於該等接墊中之若干接墊,並且 該每一個導電元件係接合於該等接墊中之一接墊,盆中該 接墊係電連接至一接地端; 〃 將一^裝材料(Package material)成型於該基板之上表面上,以 覆蓋該至少一電子元件以及該至少一導電元件,致使該每 一個導電元件外露其頂部;以及 形成一導電層(Electrically conductive layer),以覆蓋該已成型 的封裝材料之一表面,並且接觸該每一個導電元件之頂 部’進而完成該電子元件模組封裝結構。 、 9、如申請專利範圍第8項所述之方法,其中該至少一電子元件包含Forming at least one electronic component and at least one electrically conductive device on the upper surface of the substrate, wherein one electronic component is bonded to the plurality of pads in the pads, and Each of the conductive elements is bonded to one of the pads, wherein the pads are electrically connected to a ground; 〃 a package material is formed on the upper surface of the substrate, The top surface of the formed packaging material is covered and covered The top of each of the conductive elements' completes the electronic component module package structure. 9. The method of claim 8, wherein the at least one electronic component comprises 7、 8、 自由電阻器(Resistor)、一電容器(Capacitor)、一電感器 (Inductor)、一二極體(Diode)、一限流器(Bead)以及一晶片 所組成之一群組中之一電子元件。 1〇、如申請專利範圍第8項所述之方法’其中該每一個導電元件 一金屬所形成。 11、如申請專利範圍第8項所述之方法,其中該導電層係由一金屬 形成。 12、 =申請專利範圍糾項所述之方法,其中該 製程、-塗佈製程…蒸鍍製程或-印刷製程所形成㈣機鍛 13、 專利範圍第8項所述之方法,其中該封裝材料係一固態環 氧樹脂模封材料(Epoxy molding compound, EMC)或一液態封裝 材質(Liquid encapsulation material)。 13 1311345 ♦ * t 14、如申請專利範圍第8項所述之方法,其中該導電層係覆蓋該已成 型的封裝材料之一周緣。7, 8, a free resistor (Resistor), a capacitor (Capacitor), an inductor (Inductor), a diode (Diode), a current limiter (Bead) and a wafer in a group An electronic component. The method of claim 8, wherein each of the conductive members is formed of a metal. 11. The method of claim 8, wherein the conductive layer is formed of a metal. 12, = the method described in the patent scope correction, wherein the process, the coating process, the evaporation process or the printing process, the method described in the fourth aspect of the invention, wherein the package material is It is a solid epoxy molding compound (EMC) or a liquid encapsulation material. The method of claim 8, wherein the conductive layer covers a periphery of one of the formed packaging materials. 1414
TW095108263A 2006-03-10 2006-03-10 Electronic device module package structure and method of making the same TWI311345B (en)

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