CN114864456A - Scheduling method, system and device for semiconductor cleaning equipment and storage medium - Google Patents
Scheduling method, system and device for semiconductor cleaning equipment and storage medium Download PDFInfo
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- CN114864456A CN114864456A CN202210797348.2A CN202210797348A CN114864456A CN 114864456 A CN114864456 A CN 114864456A CN 202210797348 A CN202210797348 A CN 202210797348A CN 114864456 A CN114864456 A CN 114864456A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67276—Production flow monitoring, e.g. for increasing throughput
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a method, a system and a device for scheduling semiconductor cleaning equipment and a storage medium, and belongs to the technical field of semiconductor manufacturing. The invention determines a wafer to be cleaned, determines a predicted dead lock ring based on the wafer to be cleaned, determines a control library corresponding to the predicted dead lock ring, performs process scheduling simulation based on the wafer to be cleaned and the control library, effectively prevents possible deadlock conditions by using a pre-control library, judges whether a simulation result of the process scheduling simulation meets a preset bubble passing time constraint, performs the process scheduling in advance through the process scheduling simulation, exposes a possible wafer bubble passing risk in advance, reduces the wafer damage probability, controls a semiconductor cleaning device to execute cleaning operation according to the simulation result when the simulation result meets the bubble passing time constraint, reduces the occurrence probability of the deadlock conditions and the risk of the wafer bubble passing when the semiconductor cleaning device executes the cleaning operation, and improves the scheduling effectiveness of the semiconductor cleaning device.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method, a system and a device for scheduling semiconductor cleaning equipment and a storage medium.
Background
In recent years, electronic consumer products have been popularized in various aspects of life, and semiconductor materials have been the basis of these products, which has led to the semiconductor industry becoming a focus industry in all countries of the world.
Wafer fabrication is the most automated and complex process in semiconductor manufacturing. The wafer manufacturing comprises the processes of deposition, glue coating, exposure, development, etching and the like. After the above processes are completed, a cleaning process is often required to be performed, so as to ensure the quality of the wafer. The cleaning process is a very important process step in the semiconductor chip manufacturing process. This also results in the length of the cleaning process operation time being one of the key factors that limit the yield of semiconductor chips. Therefore, how to schedule the cleaning equipment so that the cleaning equipment can complete the cleaning process efficiently and quickly is an important problem which needs to be solved at present.
Disclosure of Invention
The invention mainly aims to provide a method, a system, a device and a storage medium for scheduling semiconductor cleaning equipment, and aims to solve the technical problem of improving the effectiveness of scheduling semiconductor cleaning equipment.
In order to achieve the above object, the present invention provides a scheduling method of a semiconductor cleaning device, the method comprising:
determining a wafer to be cleaned, and determining a predicted dead lock ring based on the wafer to be cleaned;
determining a control library corresponding to the predicted dead lock ring;
performing process scheduling simulation based on the wafer to be cleaned and the control library;
and if the bubble passing time constraint is met, controlling the semiconductor cleaning equipment to execute cleaning operation according to the simulation result.
Optionally, the step of determining a predicted dead lock ring based on the wafer to be cleaned comprises:
if a plurality of wafers to be cleaned exist, combining the wafers to be cleaned according to a preset task number to generate a task group to be cleaned;
determining a cleaning path corresponding to the task group to be cleaned and the number of the task groups of the task group to be cleaned;
and determining a predicted dead lock loop according to the number of the task groups and the cleaning path.
Optionally, the step of determining the control library corresponding to the predicted dead lock loop comprises:
if a plurality of the predicted dead lock rings exist, determining a control library corresponding to each predicted dead lock ring;
the step of process scheduling simulation based on the wafer to be cleaned and the control library comprises:
and performing process scheduling simulation based on the task group to be cleaned and the control library.
Optionally, the step of performing process scheduling simulation based on the task group to be cleaned and the control library includes:
determining the task group deadlock number of a task group to be cleaned in each prediction deadlock ring;
determining the task capacity of the control library corresponding to the prediction deadlock ring based on the task group deadlock number corresponding to the prediction deadlock ring;
and performing process scheduling simulation on the task group to be cleaned based on the task capacity of the control library.
Optionally, the step of performing process scheduling simulation on the task group to be cleaned based on the task capacity of the control library includes:
determining the number of the task groups to be cleaned allowed to be accommodated in a prediction deadlock ring corresponding to the control library according to the task capacity;
and performing process scheduling simulation on the task group to be cleaned according to the number of the task groups to be cleaned allowed to be accommodated in the prediction deadlock ring.
Optionally, the step of combining the wafers to be cleaned according to the preset number of tasks to generate a task group to be cleaned includes:
combining the wafers to be cleaned according to the number of preset tasks to generate a first task group to be cleaned;
determining the wafers to be cleaned which are not combined, and combining the wafers to be cleaned which are not combined according to the preset task number to generate a next task group to be cleaned until all the wafers to be cleaned are combined.
Optionally, after the step of determining whether the simulation result of the process scheduling simulation violates a preset bubble passing time constraint, the method further includes:
if the bubble time constraint is not met, combining the wafers to be cleaned according to the preset task quantity to generate a first task group to be cleaned;
and after waiting for a preset time, executing the steps of determining the wafers to be cleaned which are not combined, and combining the wafers to be cleaned which are not combined according to the preset task number.
In addition, in order to achieve the above object, the present invention further provides a semiconductor cleaning apparatus scheduling system, including:
the scheduling simulation module is used for determining a wafer to be cleaned and carrying out procedure scheduling simulation based on the wafer to be cleaned and a preset deadlock control strategy;
the bubble passing constraint module is used for judging whether a simulation result of the procedure scheduling simulation meets a preset bubble passing time constraint;
and the cleaning execution module is used for controlling the semiconductor cleaning equipment to execute cleaning operation according to the simulation result if the bubble passing time constraint is met.
In addition, in order to achieve the above object, the present invention further provides a semiconductor cleaning device scheduling apparatus, which includes a memory, a processor, and a semiconductor cleaning device scheduler that is stored in the memory and is executable on the processor, wherein: the semiconductor cleaning equipment scheduling program realizes the steps of the semiconductor cleaning equipment scheduling method when being executed by the processor.
In addition, to achieve the above object, the present invention also provides a computer readable storage medium, which stores thereon a semiconductor cleaning apparatus scheduler program, which when executed by a processor implements the steps of the semiconductor cleaning apparatus scheduling method as described above.
The invention provides a dispatching method, a system, a device and a storage medium of semiconductor cleaning equipment, which are used for determining a wafer to be cleaned, determining a predicted dead lock ring based on the wafer to be cleaned, determining a control library corresponding to the predicted dead lock ring, performing process scheduling simulation based on the wafer to be cleaned and the control library, effectively preventing possible deadlock conditions by using the pre-control library, judging whether a simulation result of the process scheduling simulation meets a preset bubble passing time constraint or not, performing the process scheduling simulation in advance through the process scheduling simulation, exposing the possible wafer bubble passing risk in advance, reducing the wafer damage probability, controlling the semiconductor cleaning equipment to execute cleaning operation according to the simulation result when the simulation result meets the bubble passing time constraint, and reducing the occurrence probability of the deadlock condition and the wafer bubble passing risk when the semiconductor cleaning equipment executes the cleaning operation, the effectiveness of scheduling the semiconductor cleaning equipment is improved.
Drawings
Fig. 1 is a schematic structural diagram of a scheduling apparatus of a semiconductor cleaning device in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart illustrating a scheduling method of semiconductor cleaning equipment according to a first embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a semiconductor cleaning apparatus according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a deadlock scenario, according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an application of a control library according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a dispatching system of the semiconductor cleaning apparatus of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a scheduling apparatus of a semiconductor cleaning device in a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 1, the semiconductor cleaning apparatus scheduling device may include: a processor 1001, such as a Central Processing Unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a WIreless interface (e.g., a WIreless-FIdelity (WI-FI) interface). The Memory 1005 may be a Random Access Memory (RAM) Memory, or may be a Non-Volatile Memory (NVM), such as a disk Memory. The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the configuration shown in fig. 1 does not constitute a limitation of the semiconductor cleaning apparatus scheduling device and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 1, the memory 1005, which is a storage medium, may include therein an operating system, a data storage module, a network communication module, a user interface module, and a semiconductor cleaning apparatus scheduler.
In the semiconductor cleaning equipment scheduling apparatus shown in fig. 1, the network interface 1004 is mainly used for data communication with other equipment; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 of the semiconductor cleaning equipment scheduling device of the present invention may be provided in a semiconductor cleaning equipment scheduling device, which calls the semiconductor cleaning equipment scheduling program stored in the memory 1005 through the processor 1001 and executes the semiconductor cleaning equipment scheduling method provided by the embodiment of the present invention.
An embodiment of the present invention provides a method for scheduling semiconductor cleaning equipment, and referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of the method for scheduling semiconductor cleaning equipment according to the present invention.
In this embodiment, the semiconductor cleaning device scheduling method includes:
step S100, determining a wafer to be cleaned, and determining a prediction dead lock ring based on the wafer to be cleaned;
wafer fabrication is the most automated and complex process in semiconductor manufacturing. After the wafer is manufactured through the processes of deposition, glue coating, exposure, development, etching and the like, a cleaning procedure is often required to be carried out, and the quality of the wafer is further ensured. Therefore, the cleaning process is a very important process step in the semiconductor chip manufacturing process. The semiconductor cleaning equipment comprises three parts: a front-end storage area, a transmission area, and a process area. In a different area, the apparatus is equipped with a robot for transferring the wafer products. In addition, in the process area, there are wet tanks that can be used to hold various chemical liquids such as acids. The scheduling optimization and control problem of the equipment layout and configuration for cleaning equipment brings two main difficulties: firstly, the workpiece cannot stay in a wet tank for too long after being processed, otherwise, the chemical liquid can corrode the wafer to cause great economic loss, and therefore, strict bubble passing time constraint exists; secondly, because the cleaning equipment can process multiple varieties of wafer products at the same time, the process paths of different wafer products may be different, which results in possible deadlock of the system. The above two difficulties bring great challenges to the scheduling optimization problem of the cleaning equipment. At present, the scheduling scheme of the action sequence of the cleaning equipment is mostly generated by adopting a mixed integer programming method in actual production. The main drawback of this method is that the model size grows exponentially with the increase of discrete variables, so for practical problems it is often difficult to get a solution in an efficient time, which in turn delays the production process, but leads to poor production efficiency of the system. To compensate for the time deficiency, engineers often reduce the number of wafer products in the input model, relax some constraints, and make some assumptions to get a solution in a reasonable time. The solution obtained in this way is often not optimal or even feasible. According to actual production, the problems of long calculation time and poor solution quality mainly exist in the current scheduling scheme of the action sequence of the cleaning equipment. In this embodiment, the operation scheduling simulation is used to preferentially schedule the operations of the cleaning equipment, so as to reasonably schedule the cleaning equipment according to the operation scheduling result, consume few computing resources, rapidly complete the scheduling scheme, and greatly improve the productivity of the cleaning equipment.
In practical applications, the process of executing the cleaning process on the wafer to be cleaned is prone to deadlock due to the fact that the path for cleaning the wafer has the conditions of reentry and reverse order, and the like, and meanwhile bubbles are considered. The method specifically comprises a strategy of limiting a path of a wafer to be cleaned when a cleaning process is executed.
Specifically, the step of determining a predicted dead lock ring based on the wafer to be cleaned comprises:
step a, if a plurality of wafers to be cleaned exist, combining the wafers to be cleaned according to a preset task number to generate a task group to be cleaned;
b, determining a cleaning path corresponding to the task group to be cleaned and the number of the task groups of the task group to be cleaned;
and c, determining a prediction dead lock ring according to the number of the task groups and the cleaning path.
In this embodiment, it should be noted that the semiconductor cleaning apparatus for cleaning a wafer may be applied to a full-automatic or semi-automatic cleaning machine, and referring to fig. 3, in an application scenario, the structure of the cleaning machine includes: a front-end Stocker region, a Transfer region and a process region. The front-end Stocker area (semi-automatic cleaning of the area is completed manually) specifically comprises the following steps: one or more loadports (LP, wafer handler): the cleaning machine is an interactive interface between the cleaning machine and the outside and is used for placing a front-opening-exposed-finished Foup (front-opening standard wafer cassette) to be processed or processed and an FTR (wafer cassette manipulator): foup manipulators, which transport Foup, Buffers between openers, LoadPort, Buffers: the temporary storage area is used for placing processed or to-be-processed wafer products; transfer region (Transfer region): one or more openers: the interface is an interface for interaction between a Transfer area and a Stocker area, and is used for placing a Foup or an empty Foup with wafers (wafers), and one or more transmission modules: taking out the unprocessed wafer from the Foup on the Opener and conveying the wafer to a Pusher, or conveying the wafer with the finished process from the Pusher back to the empty Foup on the Opener, wherein: the wafer placing device is provided with a plurality of stations (two stations in general), and allows wafers in a plurality of Foup to be combined into a Job for carrying out the process, and the Job is also the inlet of a process area; the process area is as follows: PTR robot (process transfer robot): for transporting wafers into the process area and transferring wafer products between different modules of the process area, one or more LTR robots (transfer robots): for connecting two adjacent Tank, and at the same time, for transporting the wafer between the two Tank, the functional module is generally arranged on the process step with high bubble passing requirement: one or more functional modules are uniformly distributed in a Rinse water Tank, a Chemical acid Tank, an EWD manipulator hand washing position and a Dry drying Tank, and can be represented by Tank 1-n.
Based on the cleaning equipment structure in the application scene, the specific process flow for cleaning the wafer is as follows: the FTR transports the Foup from the LP to the Opener and then to the Buffer area for temporary storage, a process called Carrier In. The FTR transports the Foup from Buffer to Opener, transports the Wafer in the Buffer to Pusher through the Transfer area, then transports the empty Foup back to Buffer, repeats one or more times, transports multiple groups of wafers to Pusher area, and combines them into a Job, which is called JobIN. PTR, LTR processes Job from Pusher bit to several function blocks according to Job's processing path, and returns to Pusher bit, which is called JobMid. Job is split into multiple groups of wafers by Pusher and returns to Buffer via the Transfer area and FTR robot, a process called JobOut. The FTR transports the finished Foup to the LP site, awaiting transport outside the facility, a process known as Carrier Out.
In this embodiment, the final process scheduling simulation result is determined, and after all the Job actions are scheduled, CarrierIn and CarrierOut are considered, so that only enough gap time for putting into the CarrierIn or CarrierOut actions without affecting the Job actions needs to be found within the scheduling range of the FTR, and the gap time is arranged one by one.
In this embodiment, it should be noted that, when wafer cleaning is performed, wafers are combined to obtain a task group to be cleaned, and the preset number of tasks is a preset number that limits the number of wafers included in a single cleaning task group, for example, 50 wafers are combined to form one task group to be cleaned. Such as job in the application scenario described above. It is understood that the cleaning paths for all wafers included in the one task group to be cleaned are the same. The cleaning paths between different groups of tasks to be cleaned may or may not be the same. When two Jobs wait for each other to release module resources, a deadlock occurs, for example, JobA needs to go to Tank2 at Tank1 and JobB needs to go to Tank1 at Tank2, which is called a 2Job deadlock. If so, Job1 needs to go to the module of Job2, Job2 needs to go to the module of Job3, Job3 needs to go to the module of Job1, which is called 3Job deadlock, and we can deduce the situation where nJob deadlock occurs. In practical applications, the FTR robot is required to be used to combine the wafers to be cleaned to form the task group to be cleaned, and the carrying capacity of the FTR robot is limited, so that the task group to be cleaned is formed as a group, and a plurality of task groups to be cleaned are not formed at the same time. Therefore, even if the cleaning paths of the task groups to be cleaned are the same, after the task groups enter the process area, because the entering time is different, a deadlock situation is likely to occur when the cleaning process is executed between different task groups to be cleaned. When the deadlock situation occurs, the paths of each task group to be cleaned which is trapped in the deadlock will form a ring, and wait for the next wet slot to be vacated. The number of task groups refers to the number of generated task groups to be cleaned. The predicted deadlock ring refers to a possible deadlock state predicted based on a currently existing task group to be cleaned, wherein the number, paths and other conditions of the task group to be cleaned in the possible deadlock state can be reflected. Specifically, wafers to be cleaned are combined according to the number of preset tasks to generate task groups to be cleaned, all generated task groups to be cleaned are obtained, if only one task group to be cleaned exists, no cleaning path of the task group to be cleaned is in conflict with other task groups to be cleaned, and at this time, a prediction dead lock ring is inevitably avoided; when a plurality of task groups to be cleaned exist, cleaning paths corresponding to all the task groups to be cleaned are respectively determined, calculation is carried out based on the number of the task groups to be cleaned and the cleaning paths of all the task groups to be cleaned, and a prediction dead lock ring is obtained.
In this embodiment, a deadlock situation that may exist in the process scheduling simulation is predicted by using the deadlock prediction ring, so that the simulation of deadlock prevention is performed, thereby ensuring that the occurrence of a deadlock situation is effectively avoided in the process scheduling simulation result, and improving the effectiveness of the process scheduling simulation.
Step S200, determining a control library corresponding to the prediction dead lock loop;
in this embodiment, it should be noted that the control library is used to limit a path of the wafer to be cleaned when the cleaning process is performed.
Specifically, the step of determining the control library corresponding to the predicted dead lock loop comprises the following steps:
d, if a plurality of the predicted dead lock rings exist, determining a control library corresponding to each predicted dead lock ring;
in this embodiment, it should be noted that the number of rings refers to the number of predicted dead lock rings, and when performing the process scheduling simulation, different task groups to be cleaned are located in different cleaning paths at the same time in the simulation process, so that a plurality of predicted dead lock rings may exist in the whole cleaning path. Referring to fig. 4, in a scene, Tank x, Tank1, Tank2, and Tank y respectively represent wet tanks on a cleaning path of a task group to be cleaned, where a 2 jobb deadlock is formed between Tank1 and Tank2, the task group to be cleaned in Tank1 is to enter Tank2, and the task group to be cleaned in Tank2 is to enter Tank 1. The method comprises the steps that the number of wet slots which are possibly deadlocked is included in a prediction deadlock ring, in order to avoid deadlock, a corresponding control library is set based on the number of wet slots which are possibly deadlocked, the control library is used for carrying out capacity control on a task group to be cleaned, which can enter a cleaning path in which the prediction deadlock ring is located, so as to avoid the generation of a deadlock ring, and the control library is dynamically adjusted according to the real-time cleaning path of the task group to be cleaned. The number of the predicted deadlock rings is multiple, so that the number of the corresponding control libraries is determined based on the number of the rings corresponding to the predicted deadlock rings, and each predicted deadlock ring can be correspondingly provided with one control library.
Step S300, process scheduling simulation is carried out based on the wafer to be cleaned and the control library;
specifically, the method comprises the following steps: and e, performing process scheduling simulation based on the task group to be cleaned and the control library.
In this embodiment, the process scheduling simulation refers to a process of simulating a cleaning process of a wafer to be cleaned based on a structure of a cleaning apparatus, and includes a simulation of cleaning paths, a process start time, a process of the cleaning process, and the like of all the wafers to be cleaned. When the wafer is cleaned, the wafer is combined to obtain task groups to be cleaned, after a control library corresponding to the prediction dead lock ring is determined, process scheduling simulation of the task groups to be cleaned is carried out on the basis of the control library, and therefore the prediction dead lock ring possibly appearing in each task group to be cleaned is effectively prevented.
Step S400, judging whether the simulation result of the procedure scheduling simulation meets the preset bubble passing time constraint;
in this embodiment, it should be noted that, in the process area of the cleaning apparatus, there are a plurality of wet tanks (tank) which can be used to hold various chemical liquids such as acid. Therefore, when the cleaning equipment is used for processing, the processed wafer can not stay in the wet tank for too long, otherwise the chemical liquid can corrode the wafer, thereby causing great economic loss, and therefore, the over-soaking time constraint is strict. The soaking time of different wafers in the wet tank is not consistent, the preset bubble passing time constraint comprises a limiting condition of the soaking time of all the wafers in the wet tank, and when the preset bubble passing time constraint is violated, the wafers have corrosion risks. And predicting whether the condition of meeting the preset bubble passing time constraint occurs or not by simulating the process scheduling of the wafer to be cleaned.
And S500, if the bubble passing time constraint is met, controlling the semiconductor cleaning equipment to execute cleaning operation according to the simulation result.
After the process scheduling simulation, determining whether a step violating the preset bubble passing time constraint exists in a simulation result of the process scheduling simulation, if the step violating the preset bubble passing time constraint does not exist, determining that the simulation result of the process scheduling simulation does not violate the preset bubble passing time, and controlling the semiconductor cleaning equipment to perform cleaning operation on the wafer to be cleaned according to the steps of each cleaning process in the simulation result. If the step violating the preset bubble time constraint exists, the simulation result of the process scheduling simulation is considered to violate the preset bubble time constraint, at this time, the semiconductor cleaning equipment is not controlled to perform cleaning operation on the wafer to be cleaned according to the steps of all the cleaning processes in the simulation result, the process scheduling simulation is performed again until the simulation result of the process scheduling simulation does not violate the bubble time constraint, and the semiconductor cleaning equipment is controlled to perform cleaning operation on the wafer to be cleaned according to the steps of all the cleaning processes in the simulation result which does not violate the bubble time constraint. And adjusting the process schedule of the wafer to be cleaned in the process of carrying out the process simulation again.
In the embodiment of the invention, a wafer to be cleaned is determined, a predicted dead lock ring is determined based on the wafer to be cleaned, a control library corresponding to the predicted dead lock ring is determined, process scheduling simulation is carried out based on the wafer to be cleaned and the control library, possible deadlock conditions are effectively prevented by using the pre-control library, whether a simulation result of the process scheduling simulation violates a preset bubble passing time constraint or not is judged, the process scheduling is carried out in advance through the process scheduling simulation, the possible wafer bubble passing risk is exposed in advance, the wafer damage probability is reduced, when the simulation result accords with the bubble passing time constraint, the semiconductor cleaning equipment is controlled to execute cleaning operation according to the simulation result, the occurrence probability of the deadlock conditions and the risk of wafer bubble passing when the semiconductor cleaning equipment executes the cleaning operation are reduced, and the scheduling effectiveness of the semiconductor cleaning equipment is improved.
Further, a second embodiment of the scheduling method of a semiconductor cleaning apparatus according to the present invention is provided based on the first embodiment of the scheduling method of a semiconductor cleaning apparatus according to the present invention, wherein the step of performing the process scheduling simulation based on the task group to be cleaned and the control library includes:
step f, determining the deadlock quantity of the task groups to be cleaned in each prediction deadlock ring;
step g, determining the task capacity of the control library corresponding to the prediction deadlock ring based on the deadlock quantity of the task group corresponding to the prediction deadlock ring;
and h, performing procedure scheduling simulation on the task group to be cleaned based on the task capacity of the control library.
In this embodiment, referring to fig. 5, in a scene, Tank x, Tank1, Tank2, Tank y, Tank x1, and Tank y1 respectively represent wet baths on a cleaning path of a task group to be cleaned, where if a task group to be cleaned in Tank x1 and Tank y1 enters Tank1 and Tank2 at the same time, a 2 jobb deadlock situation will be formed between Tank1 and Tank2, the task group to be cleaned in Tank1 enters Tank2, and the task group to be cleaned in Tank2 enters Tank 1. In this embodiment, a situation that a 2 jobdeadlock will be formed between Tank1 and Tank2 can be determined according to the number of task groups to be cleaned and a cleaning path of each task group to be cleaned, a control library is set before the task groups to be cleaned enter Tank1 or Tank2, and capacity limitation is performed on entering Tank1 or Tank2, for example, when the capacity of the control library is 1, a token is sent to the control library while the task group to be cleaned in Tank x1 enters Tank1, at this time, the control library has reached the capacity upper limit 1, and does not receive the sending of other tokens, and if the task group to be cleaned in Tank y1 wants to enter Tank2, the token needs to be sent to the control library, but because the capacity of the control library has reached the upper limit at this time, the token is not received, and the sending of the Tank y1 fails to enter Tank2, it needs to wait. When a task group to be cleaned in the Tank x1 enters the Tank1, the task group further enters the Tank2 according to a cleaning path, and when the task group comes out of the Tank2 and enters the Tank y, tokens in a control library are synchronously eliminated, and at the moment, the task group to be cleaned in the Tank y1 can successfully send the tokens to the control library and enters the Tank 2. Therefore, deadlock between the Tank1 and the Tank2 is avoided.
When the deadlock of the deadlock ring is predicted to be 2 jobs, two groups of task groups to be cleaned fall into the deadlock, the capacity of the control library is controlled to be 1 at the moment, so that the number of the task groups to be cleaned entering the deadlock ring is 1, and the smoothness of a cleaning path can be ensured. Therefore, the task capacity of the control library is determined based on the number of the task groups to be cleaned in the prediction deadlock ring, namely the task capacity of the control library is determined based on the number of the deadlock groups. The task group deadlock number of the task group to be cleaned, which is contained in the deadlock prediction ring at most, refers to the number of the task groups to be cleaned, which are contained when the deadlock prediction ring forms a deadlock. In this embodiment, in order to improve the efficiency of the semiconductor cleaning apparatus, when determining the task capacity of the control library based on the number of the task group deadlocks corresponding to the prediction deadlock rings, it is determined that the task capacity of the control library is the number of the task group deadlocks minus 1. It will be appreciated that in another embodiment, the task capacity of the control library may be set to between 1 and the number of task group deadlocks minus 1. That is, if the number of task group deadlocks is n, the task capacity of the control store may be set to any value from 1 to (n-1).
When a plurality of prediction deadlock rings exist, a control library is correspondingly arranged for each prediction deadlock ring, and the capacity of each control library is determined by the task group deadlock number of the task group to be cleaned, which is most contained in the prediction deadlock ring corresponding to the control library.
In the embodiment, the task capacity of the control library is determined to carry out process scheduling simulation, so that the possible deadlock situation is effectively avoided, and the cleaning efficiency of the semiconductor cleaning equipment is improved.
Specifically, the step of performing process scheduling simulation on the task group to be cleaned based on the task capacity of the control library includes:
step i, determining the number of the task groups to be cleaned allowed to be contained in each prediction deadlock ring corresponding to the control library according to the task capacity;
step j, process scheduling simulation is carried out on the task group to be cleaned according to the number of the task groups to be cleaned allowed to be contained in the prediction deadlock ring.
In this embodiment, it should be noted that, in the scheduling simulation, when the control library is used to limit the task group to be cleaned entering the prediction dead lock loop, the token is sent to the control library by controlling each task group to be cleaned that is about to enter the prediction dead lock loop, so as to update the task capacity of the control library in real time; when the task group to be cleaned comes out of the prediction dead lock loop, tokens in the control library are synchronously eliminated, so that the task capacity of the control library is updated in real time. When process scheduling simulation is carried out on all task groups to be cleaned, a prediction deadlock control strategy is combined to control cleaning paths of the task groups to be cleaned, each prediction deadlock ring is provided with a corresponding control base, each control base is provided with a task capacity, in the process of process scheduling simulation, when the task groups to be cleaned run on a preset cleaning path, a token is sent to the control base corresponding to the prediction deadlock ring while entering the prediction deadlock ring, the residual capacity of the control base is reduced by one until the task capacity of the control base is zero, the task groups to be cleaned which want to enter need to wait for the task groups to be cleaned in the prediction deadlock rings to come out, when the task capacity of the control base is increased by one, the action of the token sent to the control base is completed, and the task groups to be cleaned are allowed to enter the prediction deadlock ring.
In the embodiment, the task group to be cleaned, which possibly enters the prediction dead lock ring, is strictly limited by using the task capacity of the control library, so that the possible deadlock situation is effectively avoided, and the cleaning efficiency of the semiconductor cleaning equipment is improved.
Further, the step of combining the wafers to be cleaned according to the preset number of tasks to generate a task group to be cleaned includes:
step k, combining the wafers to be cleaned according to the number of preset tasks to generate a first task group to be cleaned;
and step I, determining the wafers to be cleaned which are not combined, and combining the wafers to be cleaned which are not combined according to the preset task number to generate a next task group to be cleaned until all the wafers to be cleaned are combined.
In this embodiment, it should be noted that, when the semiconductor cleaning apparatus cleans the wafers to be cleaned, the wafers to be cleaned are combined and then performed in a group, where the cleaning paths of the combined wafers to be cleaned are consistent. After the semiconductor cleaning equipment is started, continuous cleaning procedures are carried out on the wafers to be cleaned, the wafers to be cleaned are combined, then the combined wafers to be cleaned are processed according to a cleaning path, finally the processed wafers to be cleaned are output in a non-combined mode, and the semiconductor cleaning equipment continuously executes the cleaning procedures. In this embodiment, since the resources of the synchronous operation of the semiconductor cleaning device are limited, not all of the different wafers to be cleaned are set to be executed synchronously, after the first task group to be cleaned is generated according to the cleaning resources of the semiconductor cleaning device, the semiconductor cleaning device determines the second task group to be cleaned while performing the next cleaning process on the task group to be cleaned, and at this time, it can be known that the start time of each cleaning process of the second task group to be cleaned is delayed by a certain time compared with the first task group to be cleaned.
In this embodiment, the wafers to be cleaned are grouped to perform the cleaning process, and the grouping timing is subjected to scheduling simulation, so as to provide a reference basis for further determining better grouping timing according to the scheduling simulation result, thereby improving the cleaning efficiency of the semiconductor cleaning equipment.
Further, after the step of determining whether the simulation result of the process scheduling simulation violates a preset bubble passing time constraint, the method further includes:
step m, if the bubble passing time constraint is not met, combining the wafers to be cleaned according to the preset task quantity to generate a first task group to be cleaned;
and n, after waiting for a preset time, executing the step of determining the wafers to be cleaned which are not combined, and combining the wafers to be cleaned which are not combined according to the preset task number.
In this embodiment, it should be noted that, when the simulation result violates the bubble time constraint, it may be determined that the cleaning resources of the semiconductor cleaning equipment are insufficient in the engineering scheduling simulation, for example, the robot is busy, or the next processing module of the task group to be cleaned is occupied. And determining that the simulation result violates the bubble time constraint, namely that illegal bubble time exists in a certain step of the task group to be cleaned in the scheduling simulation process. For the simulation result, in this embodiment, the generation time of the second task group to be cleaned is further delayed, so as to implement the synchronous delay of the subsequent cleaning process of the second task group to be cleaned, and to implement the alleviation of the cleaning resources of the semiconductor cleaning equipment. The preset time is the delay time, and the preset time can be changed according to practical application. The first task group to be cleaned refers to a task group to be cleaned which is generated firstly in time sequence when the semiconductor cleaning equipment carries out procedure scheduling simulation, and the second task group to be cleaned and the third task group to be cleaned are task groups to be cleaned which are generated sequentially along the time line of the first task group to be cleaned.
Specifically, if the simulation result of the process scheduling simulation violates the preset bubble passing time constraint, the process scheduling simulation is executed again, the wafers to be cleaned are combined according to the preset number of tasks, after a first task group to be cleaned is generated, after a preset time duration is waited, the wafers to be cleaned which are not combined are determined, the wafers to be cleaned which are not combined are combined according to the preset number of tasks, a next task group to be cleaned is generated, and the step of determining all the generated task groups to be cleaned is executed until all the wafers to be cleaned are combined.
In addition, in the process of executing the process scheduling simulation, an early processing strategy is preferably adopted for scheduling, scheduling information is sent to the system in each scheduling action of the task group to be cleaned, and the system receives the scheduling information in a queue mode so as to realize that the scheduling information is firstly input and firstly output and is firstly received and firstly executed. For example, after the job1 sends out the scheduling information from Tank1 to Tank2, the job2 sends out the scheduling information from Tank 3 to Tank4, and since the system receives the job1 first to send out the scheduling information from Tank1 to Tank2, the system will process the scheduling of job1 from Tank1 to Tank2 preferentially.
In the embodiment, the scheduling of the semiconductor cleaning equipment to the wafer to be cleaned is effectively optimized by using the process scheduling simulation, the wafer to be cleaned is ensured not to violate the bubble constraint, the product quality of the wafer is ensured, the process scheduling simulation only needs to consume few computing resources, the scheduling scheme can be completed in a very short time, and the energy consumption of the equipment is effectively reduced.
In addition, referring to fig. 6, the present invention also provides a semiconductor cleaning apparatus dispatching system, including:
a scheduling simulation module 2001, configured to determine a wafer to be cleaned, and perform procedure scheduling simulation based on the wafer to be cleaned and a preset deadlock control strategy;
a bubble-crossing constraint module 2002 for determining whether a simulation result of the process scheduling simulation meets a preset bubble-crossing time constraint;
and a cleaning execution module 2003, configured to control the semiconductor cleaning apparatus to execute a cleaning operation according to the simulation result if the bubble passing time constraint is met.
Optionally, the schedule simulation module 2001 is further configured to:
if a plurality of wafers to be cleaned exist, combining the wafers to be cleaned according to a preset task number to generate a task group to be cleaned;
determining a cleaning path corresponding to the task group to be cleaned and the number of the task groups of the task group to be cleaned;
determining a prediction dead lock ring according to the number of the task groups and the cleaning path;
and performing procedure scheduling simulation based on the task group to be cleaned, the prediction deadlock ring and a preset deadlock control strategy.
Optionally, the schedule simulation module 2001 is further configured to:
determining a control library corresponding to each predicted dead lock ring;
and performing process scheduling simulation based on the task group to be cleaned and the control library.
Optionally, the schedule simulation module 2001 is further configured to:
determining the task group deadlock number of a task group to be cleaned in each prediction deadlock ring;
determining the task capacity of the control library corresponding to the prediction deadlock ring based on the task group deadlock number corresponding to the prediction deadlock ring;
and performing process scheduling simulation on the task group to be cleaned based on the task capacity of the control library.
Optionally, the schedule simulation module 2001 is further configured to:
determining the number of the task groups to be cleaned allowed to be accommodated in a prediction deadlock ring corresponding to the control library according to the task capacity;
and performing process scheduling simulation on the task group to be cleaned according to the number of the task groups to be cleaned allowed to be accommodated in the prediction deadlock ring.
Optionally, the schedule simulation module 2001 is further configured to:
combining the wafers to be cleaned according to the number of preset tasks to generate a first task group to be cleaned;
determining the wafers to be cleaned which are not combined, and combining the wafers to be cleaned which are not combined according to the preset task number to generate a next task group to be cleaned until all the wafers to be cleaned are combined.
Optionally, the schedule simulation module 2001 is further configured to:
if the wafers do not accord with the bubble passing time constraint, combining the wafers to be cleaned according to the preset task quantity to generate a first task group to be cleaned;
and after waiting for a preset time, executing the steps of determining the wafers to be cleaned which are not combined, and combining the wafers to be cleaned which are not combined according to the preset task number.
The specific implementation of the semiconductor cleaning equipment scheduling system of the present invention is substantially the same as the above-mentioned embodiments of the semiconductor cleaning equipment scheduling system, and is not described herein again.
In addition, the present invention further provides a semiconductor cleaning device scheduling apparatus, which is characterized in that the semiconductor cleaning device scheduling apparatus includes a memory, a processor, and a semiconductor cleaning device scheduling program stored in the memory and operable on the processor, wherein: when executed by the processor, the semiconductor cleaning device scheduling program implements the semiconductor cleaning device scheduling method according to various embodiments of the present invention.
In addition, the invention also provides a computer readable storage medium, on which the semiconductor cleaning equipment scheduling program is stored. The computer-readable storage medium may be the Memory 20 in the terminal of fig. 1, and may also be at least one of a ROM (Read-Only Memory)/RAM (Random Access Memory), a magnetic disk, and an optical disk, and the computer-readable storage medium includes several instructions for causing a semiconductor cleaning device scheduling apparatus having a processor to execute the semiconductor cleaning device scheduling method according to the embodiments of the present invention.
It is to be understood that throughout the description of the present specification, references to "an embodiment", "another embodiment", "other embodiments", or "first through nth embodiments", etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A scheduling method of semiconductor cleaning equipment is characterized by comprising the following steps:
determining a wafer to be cleaned, and determining a prediction dead lock ring based on the wafer to be cleaned;
determining a control library corresponding to the predicted dead lock ring;
performing process scheduling simulation based on the wafer to be cleaned and the control library;
judging whether the simulation result of the procedure scheduling simulation meets the preset bubble passing time constraint or not;
and if the bubble passing time constraint is met, controlling the semiconductor cleaning equipment to execute cleaning operation according to the simulation result.
2. The semiconductor cleaning apparatus scheduling method of claim 1, wherein the step of determining a predicted dead lock ring based on the wafer to be cleaned comprises:
if a plurality of wafers to be cleaned exist, combining the wafers to be cleaned according to a preset task number to generate a task group to be cleaned;
determining a cleaning path corresponding to the task group to be cleaned and the number of the task groups of the task group to be cleaned;
and determining a predicted dead lock loop according to the number of the task groups and the cleaning path.
3. The semiconductor cleaning apparatus scheduling method of claim 2, wherein the step of determining the control library corresponding to the predicted dead lock loop comprises:
if a plurality of the predicted dead lock rings exist, determining a control library corresponding to each predicted dead lock ring;
the step of process scheduling simulation based on the wafer to be cleaned and the control library comprises:
and performing process scheduling simulation based on the task group to be cleaned and the control library.
4. The method of claim 3, wherein the step of performing process scheduling simulation based on the set of tasks to be cleaned and the control library comprises:
determining the task group deadlock number of a task group to be cleaned in each prediction deadlock ring;
determining the task capacity of the control library corresponding to the prediction deadlock ring based on the task group deadlock number corresponding to the prediction deadlock ring;
and performing process scheduling simulation on the task group to be cleaned based on the task capacity of the control library.
5. The method of claim 4, wherein the step of simulating the process schedule for the set of tasks to be cleaned based on the task capacity of the control library comprises:
determining the number of the task groups to be cleaned allowed to be accommodated in a prediction deadlock ring corresponding to the control library according to the task capacity;
and performing process scheduling simulation on the task group to be cleaned according to the number of the task groups to be cleaned allowed to be accommodated in the prediction deadlock ring.
6. The method for scheduling semiconductor cleaning equipment according to claim 2, wherein the step of combining the wafers to be cleaned according to the preset number of tasks to generate the task group to be cleaned comprises:
combining the wafers to be cleaned according to the number of preset tasks to generate a first task group to be cleaned;
determining the wafers to be cleaned which are not combined, and combining the wafers to be cleaned which are not combined according to the preset task number to generate a next task group to be cleaned until all the wafers to be cleaned are combined.
7. The method of claim 6, wherein after the step of determining whether the simulation result of the process schedule simulation violates a predetermined bubble time constraint, the method further comprises:
if the bubble time constraint is not met, combining the wafers to be cleaned according to the preset task quantity to generate a first task group to be cleaned;
and after waiting for a preset time, executing the steps of determining the wafers to be cleaned which are not combined, and combining the wafers to be cleaned which are not combined according to the preset task number.
8. A semiconductor cleaning apparatus scheduling system, the semiconductor cleaning apparatus scheduling system comprising:
the scheduling simulation module is used for determining a wafer to be cleaned and carrying out procedure scheduling simulation based on the wafer to be cleaned and a preset deadlock control strategy;
the bubble passing constraint module is used for judging whether a simulation result of the procedure scheduling simulation meets a preset bubble passing time constraint;
and the cleaning execution module is used for controlling the semiconductor cleaning equipment to execute cleaning operation according to the simulation result if the bubble passing time constraint is met.
9. A scheduling device for semiconductor cleaning equipment is characterized in that the scheduling device for semiconductor cleaning equipment comprises: a memory, a processor, and a semiconductor cleaning device scheduler stored on the memory and operable on the processor, the semiconductor cleaning device scheduler being configured to implement the steps of the semiconductor cleaning device scheduling method according to any of claims 1 to 7.
10. A storage medium having stored thereon a semiconductor cleaning apparatus scheduler that, when executed by a processor, implements the steps of the semiconductor cleaning apparatus scheduling method of any one of claims 1 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115374015A (en) * | 2022-10-24 | 2022-11-22 | 埃克斯工业有限公司 | Testing method, testing simulation device and medium of scheduling algorithm |
| CN117711994A (en) * | 2024-02-06 | 2024-03-15 | 泓浒(苏州)半导体科技有限公司 | Wafer monolithic transportation control method and system based on link logic diagram |
Citations (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020198623A1 (en) * | 2001-06-26 | 2002-12-26 | Applied Materials, Inc. | Method and apparatus for providing distributed material management and flow control in an integrated circuit factory |
| US6763277B1 (en) * | 2001-07-16 | 2004-07-13 | Advanced Micro Devices, Inc. | Method and apparatus for proactive dispatch system to improve line balancing |
| US20050137734A1 (en) * | 2003-12-23 | 2005-06-23 | Asml Netherlands B.V. | Method of operating a lithographic apparatus or lithographic processsing cell, lithographic apparatus and lithographic processing cell |
| JP2007197207A (en) * | 2006-01-30 | 2007-08-09 | Murata Mach Ltd | Carrying system |
| JP2008192866A (en) * | 2007-02-06 | 2008-08-21 | Hitachi Kokusai Electric Inc | Substrate processing device |
| WO2012147172A1 (en) * | 2011-04-27 | 2012-11-01 | 株式会社日立製作所 | Goods transportation simulation device, goods transportation plan creation device, goods storage design support device, goods transportation simulation method, goods transportation plan creation method, goods storage design support method and program |
| CN106444649A (en) * | 2016-07-05 | 2017-02-22 | 同济大学 | Semiconductor production line closed-loop scheduling control method |
| US20180076064A1 (en) * | 2016-09-13 | 2018-03-15 | Macau University Of Science And Technology | Cluster tool apparatus and a method of controlling a cluster tool apparatus |
| JP2018101343A (en) * | 2016-12-21 | 2018-06-28 | 日本電気株式会社 | Exclusive control device, exclusive control system, exclusive control method, and exclusive control program |
| CN108781348A (en) * | 2017-05-17 | 2018-11-09 | 华为技术有限公司 | A kind of dispatching method and terminal |
| CN109685398A (en) * | 2019-02-02 | 2019-04-26 | 深圳埃克斯工业自动化有限公司 | A kind of failure response method and system of semiconductor process module |
| CN110531773A (en) * | 2019-09-12 | 2019-12-03 | 北京极智嘉科技有限公司 | Robot path dispatching method, device, server and storage medium |
| CN110675005A (en) * | 2019-10-15 | 2020-01-10 | 深圳埃克斯工业自动化有限公司 | Intelligent decision-making method based on artificial intelligence technology and ROPN technology |
| CN110850819A (en) * | 2019-10-24 | 2020-02-28 | 江西理工大学 | Single-arm combination equipment scheduling method, system, mobile terminal and storage medium |
| CN111229679A (en) * | 2020-01-21 | 2020-06-05 | 北京北方华创微电子装备有限公司 | Control method and control device of wafer cleaning equipment and wafer cleaning equipment |
| CN111354654A (en) * | 2018-12-20 | 2020-06-30 | 北京北方华创微电子装备有限公司 | Deadlock judgment method and semiconductor device |
| CN111446186A (en) * | 2020-03-27 | 2020-07-24 | 北京北方华创微电子装备有限公司 | Material classification scheduling method for preventing scheduling deadlock |
| US10733350B1 (en) * | 2015-12-30 | 2020-08-04 | Sharat C Prasad | On-chip and system-area multi-processor interconnection networks in advanced processes for maximizing performance minimizing cost and energy |
| CN111563336A (en) * | 2020-04-30 | 2020-08-21 | 南通大学 | Deadlock-free scheduling method of flexible manufacturing system based on improved genetic algorithm |
| CN112396328A (en) * | 2020-11-20 | 2021-02-23 | 河海大学常州校区 | Multi-objective task allocation scheduling optimization method for multi-load carrying robot group |
| CN214795685U (en) * | 2020-12-10 | 2021-11-19 | 深度创新科技（深圳）有限公司 | Processing equipment |
| CN114169805A (en) * | 2022-01-10 | 2022-03-11 | 北京烁科精微电子装备有限公司 | Wafer scheduling method and device, storage medium and electronic equipment |
-
2022
- 2022-07-08 CN CN202210797348.2A patent/CN114864456B/en active Active
Patent Citations (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020198623A1 (en) * | 2001-06-26 | 2002-12-26 | Applied Materials, Inc. | Method and apparatus for providing distributed material management and flow control in an integrated circuit factory |
| US6763277B1 (en) * | 2001-07-16 | 2004-07-13 | Advanced Micro Devices, Inc. | Method and apparatus for proactive dispatch system to improve line balancing |
| US20050137734A1 (en) * | 2003-12-23 | 2005-06-23 | Asml Netherlands B.V. | Method of operating a lithographic apparatus or lithographic processsing cell, lithographic apparatus and lithographic processing cell |
| JP2007197207A (en) * | 2006-01-30 | 2007-08-09 | Murata Mach Ltd | Carrying system |
| JP2008192866A (en) * | 2007-02-06 | 2008-08-21 | Hitachi Kokusai Electric Inc | Substrate processing device |
| WO2012147172A1 (en) * | 2011-04-27 | 2012-11-01 | 株式会社日立製作所 | Goods transportation simulation device, goods transportation plan creation device, goods storage design support device, goods transportation simulation method, goods transportation plan creation method, goods storage design support method and program |
| US10733350B1 (en) * | 2015-12-30 | 2020-08-04 | Sharat C Prasad | On-chip and system-area multi-processor interconnection networks in advanced processes for maximizing performance minimizing cost and energy |
| CN106444649A (en) * | 2016-07-05 | 2017-02-22 | 同济大学 | Semiconductor production line closed-loop scheduling control method |
| US20180076064A1 (en) * | 2016-09-13 | 2018-03-15 | Macau University Of Science And Technology | Cluster tool apparatus and a method of controlling a cluster tool apparatus |
| JP2018101343A (en) * | 2016-12-21 | 2018-06-28 | 日本電気株式会社 | Exclusive control device, exclusive control system, exclusive control method, and exclusive control program |
| CN108781348A (en) * | 2017-05-17 | 2018-11-09 | 华为技术有限公司 | A kind of dispatching method and terminal |
| CN111354654A (en) * | 2018-12-20 | 2020-06-30 | 北京北方华创微电子装备有限公司 | Deadlock judgment method and semiconductor device |
| CN109685398A (en) * | 2019-02-02 | 2019-04-26 | 深圳埃克斯工业自动化有限公司 | A kind of failure response method and system of semiconductor process module |
| CN110531773A (en) * | 2019-09-12 | 2019-12-03 | 北京极智嘉科技有限公司 | Robot path dispatching method, device, server and storage medium |
| US20210078175A1 (en) * | 2019-09-12 | 2021-03-18 | Beijing Geekplus Technology Co. Ltd. | Method, server and storage medium for robot routing |
| CN110675005A (en) * | 2019-10-15 | 2020-01-10 | 深圳埃克斯工业自动化有限公司 | Intelligent decision-making method based on artificial intelligence technology and ROPN technology |
| CN110850819A (en) * | 2019-10-24 | 2020-02-28 | 江西理工大学 | Single-arm combination equipment scheduling method, system, mobile terminal and storage medium |
| CN111229679A (en) * | 2020-01-21 | 2020-06-05 | 北京北方华创微电子装备有限公司 | Control method and control device of wafer cleaning equipment and wafer cleaning equipment |
| CN111446186A (en) * | 2020-03-27 | 2020-07-24 | 北京北方华创微电子装备有限公司 | Material classification scheduling method for preventing scheduling deadlock |
| CN111563336A (en) * | 2020-04-30 | 2020-08-21 | 南通大学 | Deadlock-free scheduling method of flexible manufacturing system based on improved genetic algorithm |
| CN112396328A (en) * | 2020-11-20 | 2021-02-23 | 河海大学常州校区 | Multi-objective task allocation scheduling optimization method for multi-load carrying robot group |
| CN214795685U (en) * | 2020-12-10 | 2021-11-19 | 深度创新科技（深圳）有限公司 | Processing equipment |
| CN114169805A (en) * | 2022-01-10 | 2022-03-11 | 北京烁科精微电子装备有限公司 | Wafer scheduling method and device, storage medium and electronic equipment |
Non-Patent Citations (4)
| Title |
|---|
| TAE-EOG LEE ET AL: "《Scheduling a wet station for wafer cleaning with multiple job flows and multiple wafer-handling robots》", 《INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH》 * |
| 刘斌，伍乃骐，曹咏: "《着色 Petri 网模型实现AGV系统无死锁运行》", 《机器人》 * |
| 刘晓斌等: "基于Petri网的OHT搬运系统防死锁调度方法", 《中南大学学报(自然科学版)》 * |
| 贾小恒: "《半导体制造刻蚀设备调度算法的研究》", 《微计算机信息》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115374015A (en) * | 2022-10-24 | 2022-11-22 | 埃克斯工业有限公司 | Testing method, testing simulation device and medium of scheduling algorithm |
| CN115374015B (en) * | 2022-10-24 | 2023-02-10 | 埃克斯工业有限公司 | Testing method, testing simulation device and medium for scheduling algorithm |
| CN117711994A (en) * | 2024-02-06 | 2024-03-15 | 泓浒(苏州)半导体科技有限公司 | Wafer monolithic transportation control method and system based on link logic diagram |
| CN117711994B (en) * | 2024-02-06 | 2024-04-19 | 泓浒(苏州)半导体科技有限公司 | Wafer monolithic transportation control method and system based on link logic diagram |
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