CN114864414A - Chip preparation method and chip - Google Patents

Chip preparation method and chip Download PDF

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Publication number
CN114864414A
CN114864414A CN202210473968.0A CN202210473968A CN114864414A CN 114864414 A CN114864414 A CN 114864414A CN 202210473968 A CN202210473968 A CN 202210473968A CN 114864414 A CN114864414 A CN 114864414A
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China
Prior art keywords
array
wafer
chip
arrays
hole
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CN202210473968.0A
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Inventor
彭祎
李春阳
任超
刘凤
方梁洪
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Ningbo Chipex Semiconductor Co ltd
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Ningbo Chipex Semiconductor Co ltd
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Priority to CN202210473968.0A priority Critical patent/CN114864414A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to the technical field of chip manufacturing, and provides a chip preparation method and a chip. The preparation method of the chip comprises the steps of firstly carrying out electroplating treatment on an initial wafer to obtain a treated wafer; the initial wafer comprises an initial chip and an alignment chip; coating a barrier layer on the processed wafer, and forming a welding spot or a through hole of a contraposition point which needs to be formed by electroplating in the follow-up step through patterning the barrier layer; because the region on the alignment chip for playing the role of packaging alignment is an alignment point, and the cross sectional area of the alignment point is close to that of the welding spot, the height difference of the two structures after electroplating backflow is small, the uniformity of the plane where the two structures are located is improved, and the uniformity of subsequent grinding of the wafer is improved.

Description

Chip preparation method and chip
Technical Field
The invention relates to the technical field of chip manufacturing, in particular to a chip preparation method and a chip.
Background
In the chip manufacturing process, chips are continuously processed on a wafer with uniform specification so as to form chips with different specification sizes, on one hand, the size of the chip is reduced so that the chip is suitable for a circuit with high integration level; on the other hand, in order to improve the flatness of the chip, the chip is required to be lapped, and the uniformity of the lapping of the chip has higher requirements on the flatness of the chip in addition to the requirements on equipment.
In the prior art, generally, the lapping is performed based on the wafer level chip, and the lapping process is followed by slicing to form a single chip, so that the machining efficiency of the chip is improved, but the flatness of the wafer level chip is subjected to more rigorous requirements, however, the wafer in the prior art not only contains effective chips, but also contains alignment mark chips, the existing machining process enables the height difference of the two chips to be larger, so that the integral height uniformity of the wafer level chip is lower, and uneven stress during lapping causes cracking or yield loss.
Disclosure of Invention
The invention aims to solve the technical problem that the existing chip preparation method has low wafer level chip height uniformity.
In order to solve the above technical problem, the present application discloses a method for manufacturing a chip, which includes:
providing an initial wafer; the initial wafer comprises a plurality of initial chips and alignment chips; each initial chip in the plurality of initial chips is provided with an electrode array;
carrying out electroplating pretreatment on the first surface of the initial wafer to obtain a treated wafer; the first surface is provided with the electrode array;
coating a barrier layer on the first surface of the processed wafer, and patterning the barrier layer; the patterned barrier layer comprises a plurality of first through hole arrays and second through hole arrays; the plurality of first through hole arrays correspond to the plurality of electrode arrays; the second through hole array is positioned on the alignment chip; and the difference between the cross-sectional area of the second through hole array and the cross-sectional area of the first through hole array is less than or equal to a first threshold;
preparing welding spots in first through holes of the first through hole arrays by using an electroplating process, and preparing alignment points in second through holes of the second through hole arrays;
and removing the barrier layer to obtain the target wafer-level chip with a plurality of welding spot arrays and alignment spot arrays on the surface.
Optionally, the height of the second through hole array is equal to the height of the first through hole array;
the difference value between the array pitch of the second through hole array and the array pitch of the first through hole array is smaller than or equal to a second threshold value.
Optionally, in the packaging process, the packaging device may determine, based on the position of the alignment point array, the position of the chip to be packaged having a corresponding position relationship with the alignment point array by identifying the position of the alignment point array.
Optionally, the step of performing electroplating pretreatment on the first surface of the initial wafer to obtain a processed wafer includes:
preparing a dielectric layer on the first surface of the initial wafer; the dielectric layer comprises a plurality of third through hole arrays, and each third through hole array in the plurality of third through hole arrays is used for exposing the corresponding electrode array;
preparing an electroplating seed layer on the dielectric layer; the electroplating seed layer comprises a plurality of groove arrays, and each groove array in the groove arrays corresponds to one electrode array.
Optionally, preparing a solder joint in a first through hole of the plurality of first through hole arrays by using an electroplating process, and preparing a contraposition point in a second through hole of the second through hole array; removing the barrier layer to obtain a target wafer-level chip with a plurality of welding spot arrays and alignment spot arrays on the surface, wherein the method comprises the following steps:
preparing first welding columns in first through holes of the first through hole arrays by using an electroplating process, and preparing second welding columns in second through holes of the second through hole arrays;
removing the electroplating seed layer and the barrier layer outside the first welding column and the second welding column;
and performing reflow treatment on the first welding column and the second welding column to obtain the target wafer-level chip with the surface provided with a plurality of welding spot arrays and alignment spot arrays.
Optionally, after performing reflow processing on the first solder column and the second solder column to obtain a target wafer-level chip with a surface having a plurality of solder joint arrays and alignment point arrays, the method further includes:
covering a protective film on the first surface of the target wafer-level chip to obtain a wafer to be ground; the protective film can fill array gaps in the welding spot array and the alignment point array and gaps between the welding spot array and the alignment point array; the thickness of the protective film is larger than the heights of the welding spot array and the alignment point array;
and grinding a second surface opposite to the first surface to obtain a ground wafer.
Optionally, after the second surface opposite to the first surface is ground to obtain a ground wafer, the method further includes:
and carrying out slicing processing on the ground wafer to obtain a target chip.
Optionally, the thickness of the dielectric layer ranges from 3 to 10 micrometers.
Optionally, the material of the dielectric layer includes a low-temperature cured polymer material or a high-temperature cured polymer material.
The application also discloses a chip which is prepared based on any one of the preparation methods of the chip.
By adopting the technical scheme, the preparation method of the chip provided by the application has the following beneficial effects:
according to the preparation method of the chip, the initial wafer is electroplated to obtain a processed wafer; the initial wafer comprises an initial chip and an alignment chip; coating a barrier layer on the processed wafer, and forming a welding spot or a through hole of a contraposition point which needs to be formed by electroplating in the follow-up step through patterning the barrier layer; because the region on the alignment chip for playing the role of packaging alignment is an alignment point, and the cross sectional area of the alignment point is close to that of the welding spot, the height difference of the two structures after electroplating backflow is small, the uniformity of the plane where the two structures are located is improved, and the uniformity of subsequent grinding of the wafer is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart of an alternative chip fabrication process of the present application;
FIG. 2 is a schematic cross-sectional view of an alternative initial wafer of the present application;
FIG. 3 is a schematic view of an alternative post-processing wafer configuration of the present application;
FIG. 4 is a schematic diagram of an alternative initial wafer with a dielectric layer according to the present application;
FIG. 5 is a top view of an alternative post-processing wafer after patterning a barrier layer according to the present application;
FIG. 6 is a cross-sectional view of an alternative electroplated wafer of the present application;
FIG. 7 is a cross-sectional view of an alternative target wafer level chip of the present application;
FIG. 8 is a schematic view of an alternative post-polishing wafer configuration of the present application;
FIG. 9 is a schematic view of an alternative post-polishing wafer with the protective film removed according to the present application;
FIG. 10 is a top view of an alternative prior art alignment chip.
The following is a supplementary description of the drawings:
1-an electrode; 2-a passivation layer; 3-a dielectric layer; 4-electroplating a seed layer; 5-a groove; 6-a third via; 7-a barrier layer; 8-initial chip; 801-a first via array; 9-aligning the chip; 901-a second via array; 10-a first via; 11-a second via; 12-a first metal layer; 13-second metal layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, are used in an orientation or positional relationship based on that shown in the figures, which is for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and thus, are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
For purposes of the following detailed description, it is to be understood that the invention may assume various alternative variations and step sequences, except where expressly specified to the contrary. Moreover, other than in any operating examples, or where otherwise indicated, all numbers expressing, for example, quantities of ingredients used in the specification and claims are to be understood as being modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that may vary depending upon the desired properties to be obtained by the present invention. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
When a range of values is disclosed herein, the range is considered to be continuous and includes both the minimum and maximum values of the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values of the range is included. Further, when multiple range-describing features or characteristics are provided, the ranges may be combined. In other words, unless otherwise indicated, all ranges disclosed herein are to be understood to encompass any and all subranges subsumed therein. For example, a stated range from "1 to 10" should be considered to include any and all subranges between the minimum value of 1 and the maximum value of 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, and the like.
In the manufacturing process of the chip, because the manufacturing precision is high, particularly in the manufacturing packaging process, each chip to be packaged needs to be accurately positioned, however, in the packaging process of the wafer-level chip, because the wafer-level packaging is full-surface packaging, but defective products are generated in the packaging process, the detection marks are marked in the maps to distinguish good products from defective products, electrical properties or appearances can generate maps, the maps of the processes need to be superposed and finally need to be in one-to-one correspondence with the chips on the wafer, in order to quickly and accurately superpose the maps, and in the field of WL-CSP packaging, alignment mark chips need to be designed in the photoetching process, the mark point patterns and the surface layer patterns of the wafer are accurately aligned, the mask pattern is copied to the wafer, and the deviation is reduced; the alignment mark chip can be used as a reference point of the whole wafer and plays a key role in the use of a map formed in the packaging process. The obvious difference between the appearance of the alignment mark chip and the appearance of the effective chip can quickly enable the mark points in the map to correspond to the mark points of the wafer one by one, thereby being beneficial to the normal use of the map and improving the packaging efficiency. Therefore, in wafer level chips, the presence of a registration chip is essential for the most wafer reference point.
In the prior art, the counterpoint chip and the effective chip run through the whole process of chip manufacture together, especially in the electroplating process, the solder joint of the effective chip and the counterpoint figure of counterpoint chip are prepared simultaneously, in fact, because the solder joint area of the effective chip is less than the area of counterpoint figure, it is little to easily cause the little last tin volume of solder joint area in the electroplating process, and then make the height of final solder joint be less than the height of counterpoint figure, because solder joint and the planar homogeneity of counterpoint figure are poor, in the process of carrying out the abrasive disc to wafer level chip, stress concentration is easily produced, cause the abrasive disc homogeneity poor, even circumstances such as lobe of a leaf.
To this end, referring to fig. 1, fig. 1 is a flow chart illustrating an alternative chip fabrication process of the present application. The application provides a preparation method of a chip, which comprises the following steps:
s101: providing an initial wafer; the initial wafer comprises a plurality of initial chips 8 and alignment chips 9; each initial chip 8 of the plurality of initial chips 8 is provided with an electrode array.
Referring to fig. 2, fig. 2 is a cross-sectional view of an alternative initial wafer of the present application. The surface of the initial wafer is also provided with a passivation layer 2; the passivation layer 2 is provided with an opening for exposing the electrode 1 of the electrode array, and the passivation layer 2 is used for protecting the chip circuit.
Alternatively, the passivation layer 2 may have a local passivation structure as shown in fig. 2, or may be passivated over the entire surface, i.e., the passivation layer 2 is disposed on the entire surface of the wafer.
The initial wafer may be ready-made or may be formed and processed by a general chip processing technique as needed.
S102: performing electroplating pretreatment on the first surface of the initial wafer to obtain a treated wafer with a structure shown in fig. 3; the first surface is provided with the electrode array.
In one possible embodiment, step S102 can be specifically described as: preparing a dielectric layer 3 on the first surface of the initial wafer; the dielectric layer 3 comprises a plurality of third through hole arrays, and each third through hole array in the plurality of third through hole arrays is used for exposing a corresponding electrode array; preparing an electroplating seed layer 4 on the dielectric layer 3; the plating seed layer 4 includes a plurality of groove arrays, each of which corresponds to one electrode array.
It should be noted that one groove array corresponds to one electrode array, each groove array includes a plurality of grooves 5, and each groove 5 corresponds to one electrode 1; as can be seen from fig. 3, one electrode 1 of the electrode array is provided with a recess 5.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an alternative initial wafer with a dielectric layer according to the present application. Each initial chip 8 is provided with an electrode array, and the opening of the passivation layer 2 and the third through hole 6 of the dielectric layer 3 are all used for exposing a corresponding electrode 1, so that the subsequent electroplating treatment of the electrode 1 can be realized, and the electroplated welding spot is connected with an external circuit.
The dielectric layer 3 can be used as a buffer protection layer of a wafer, has a protection function and a stress buffering function, greatly improves the structural reliability of a product, can protect the surface of a chip from stress damage, enables the surface of the chip to be flatter, and is beneficial to improving the uniformity and the bonding force of a subsequent electroplating process.
In one possible embodiment, the thickness of the dielectric layer 3 is in a range of 3 to 10 μm.
In a possible embodiment, the material of the dielectric layer 3 includes a low-temperature cured polymer material or a high-temperature cured polymer material.
Optionally, the plating seed layer 4 may be prepared by sputtering, and may be formed by performing whole-surface sputtering on the first surface; the material of the plating seed layer 4 includes but is not limited to Ti/Cu, i.e. other conductive metals are also possible.
S103: coating a barrier layer 7 on the first surface of the processed wafer, and patterning the barrier layer 7; the patterned barrier layer 7 comprises a plurality of first via arrays 801 and second via arrays 901; the plurality of first via arrays 801 correspond to the plurality of electrode arrays; the second via array 901 is located on the alignment chip 9; and the difference between the cross-sectional area of the second through hole 11 of the second through hole array 901 and the cross-sectional area of the first through hole 10 of the first through hole array 801 is less than or equal to a first threshold.
In one possible embodiment, the height of the second via 11 of the second via array 901 is equal to the height of the first via 10 of the first via array 801; the difference between the array pitch of the second via array 901 and the array pitch of the first via array 801 is less than or equal to a second threshold.
Referring to fig. 5, fig. 5 is a top view of a processed wafer after an optional patterned barrier layer of the present application. The second via array 901 is used for forming an alignment point array after subsequent electroplating; the alignment dot array can be arranged in a cross shape as shown in fig. 5, or in other patterns, such as an L shape or a square shape, as desired. As long as it can be clearly distinguished from the rectangle formed by the first via array 801.
Optionally, the first threshold value is in a range of 0 to 5 square microns. Because the difference value between the cross-sectional area of the second through hole 11 and the cross-sectional area of the first through hole 10 is small, the tin coating amount in the subsequent electroplating process is close to or equal to each other, the difference between the height of the welding spot on the final initial chip 8 and the height of the alignment point on the alignment chip 9 is small, the grinding uniformity is improved, and the wafer is not easy to crack.
Optionally, the method for specifically patterning the barrier layer 7 includes: placing a mask plate on the barrier layer 7, wherein the mask plate is away from the barrier layer 7 by a preset distance, and carrying out exposure treatment; and developing the exposed wafer to realize the patterned barrier layer 7.
Optionally, the positions of the alignment chips 9 on the wafer and the number of the alignment chips 9 may be designed as required, for example, when the number of the alignment chips 9 is three, one may be disposed on each of two opposite sides of the wafer, and one may be disposed between the two alignment chips 9.
In the process of carrying out alignment exposure on the mask, the alignment chip 9 can be used as an alignment reference point, so that the mask and the wafer are accurately aligned, and the offset of the mask and the wafer is reduced.
S104: a solder joint is prepared in the first via hole 10 of the plurality of first via hole arrays 801 and a docking point is prepared in the second via hole 11 of the second via hole array 901 by using an electroplating process.
Optionally, referring to fig. 6, fig. 6 is a cross-sectional view of an optionally electroplated wafer of the present application. The structure of the welding spot and the structure of the contraposition spot obtained after electroplating are the same, namely the welding spot and the contraposition spot both comprise a first metal layer 12 and a second metal layer 13 which are laminated; the material of the first metal layer 12 includes but is not limited to copper, gold, silver, and the like; the material of the second metal layer 13 is tin, which facilitates flip chip bonding with an external circuit.
S105: and removing the barrier layer 7 to obtain the target wafer-level chip with a plurality of welding spot arrays and alignment spot arrays on the surface.
In one possible embodiment, steps S104-S105 can be described as follows: preparing first solder columns in first through holes 10 of the plurality of first through hole arrays 801 and second solder columns in second through holes 11 of the second through hole array 901 by using an electroplating process; removing the plating seed layer 4 outside the first solder column and the second solder column, and the barrier layer 7; and performing reflow processing on the first solder columns and the second solder columns to obtain a target wafer-level chip with a surface provided with a plurality of solder joint arrays and alignment point arrays, namely the structure shown in fig. 7.
Optionally, the first solder column includes a first metal layer 12 and a second metal layer 13 which are stacked; the second stud includes a first metal layer 12 and a second metal layer 13 that are laminated.
Because the melting point of the metal tin is low, the metal tin is spherical after reflow, the higher the tin amount is, the higher the tin height is after reflow, and because the cross-sectional area of each pair of points in the application is similar to that of a welding point, the amount of the electroplated tin is also similar, and after reflow treatment, the heights of the second metal layer 13 in the first welding column and the second metal layer 13 in the second welding column are also similar.
The alignment chip 9 plays a role as an alignment reference in the photolithography process, and in the packaging process, the packaging equipment can also determine the position of the chip to be packaged, which has a corresponding position relationship with the alignment point array, by identifying the position of the alignment point array, based on the position of the alignment point array, so that in the actual packaging process, a defective product may exist, in the actual packaging process, only the chip qualified in the previous process can be packaged and used as the chip to be packaged, and the position of the alignment chip 9 can be determined by determining the position of the alignment point array, so as to determine the position of the chip to be packaged.
In one possible embodiment, referring to fig. 8-9, fig. 8 is a schematic diagram of an alternative polished wafer structure of the present application; fig. 9 is a schematic diagram of an alternative polished wafer structure with the protective film removed according to the present application. After the reflow treatment, the preparation method further comprises: covering a protective film on the first surface of the target wafer-level chip to obtain a wafer to be ground; the protective film can fill array gaps in the welding spot array and the alignment point array and gaps between the welding spot array and the alignment point array; the thickness of the protective film is larger than the heights of the welding spot array and the alignment point array; and grinding a second surface opposite to the first surface to obtain a ground wafer.
Optionally, the protective film may be a BG film, and is used to protect the first surface of the wafer, where the protective film is required to completely cover the solder joints and the docking points, but the height of the protective film is not too high, which may make the protective film soft and unable to provide sufficient supporting force, and the protective film may collapse during grinding, which may affect uniformity of the silicon layer.
Optionally, the process of covering the protective film and grinding specifically includes: firstly, sticking a protective film, measuring the thickness of the protective film, grinding the wafer, determining the thickness of the ground wafer, and if the thickness of the ground wafer meets the preset condition (namely the thickness of the ground wafer meets the preset thickness), then uncovering the protective film to obtain the ground wafer.
In one possible embodiment, after preparing the polished wafer, the method further comprises: and carrying out slicing processing on the ground wafer to obtain a target chip.
According to the method, a large-area alignment graph (cross alignment graph in fig. 10) in the prior art is made into a dot matrix graph, and the cross sectional area of a welding spot on an initial chip 8 (namely an effective chip) is close to that of an alignment point, so that the height difference between the two formed by electroplating reflux is small, and the grinding uniformity can be improved.
The application also discloses a chip which is prepared based on any one of the preparation methods of the chip.
The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A method for manufacturing a chip, comprising:
providing an initial wafer; the initial wafer comprises a plurality of initial chips (8) and alignment chips (9); each initial chip (8) in the plurality of initial chips (8) is provided with an electrode array;
carrying out electroplating pretreatment on the first surface of the initial wafer to obtain a treated wafer; the first surface is provided with the electrode array;
coating a barrier layer (7) on the first surface of the processed wafer, and patterning the barrier layer (7); the patterned barrier layer (7) comprises a plurality of first via arrays (801) and second via arrays (901); the plurality of first via arrays (801) correspond to a plurality of the electrode arrays; the second through hole array (901) is positioned on the alignment chip (9); and the difference between the cross-sectional area of the second through hole (11) of the second through hole array (901) and the cross-sectional area of the first through hole (10) of the first through hole array (801) is less than or equal to a first threshold value;
preparing solder points in first through holes (10) of the plurality of first through hole arrays (801) and preparing alignment points in second through holes (11) of the second through hole array (901) by using an electroplating process;
and removing the barrier layer (7) to obtain the target wafer-level chip with the surface provided with a plurality of welding spot arrays and alignment spot arrays.
2. The production method according to claim 1, wherein a height of the second through-hole (11) of the second through-hole array (901) is equal to a height of the first through-hole (10) of the first through-hole array (801);
the difference value between the array pitch of the second through hole array (901) and the array pitch of the first through hole array (801) is smaller than or equal to a second threshold value.
3. The manufacturing method according to claim 1, wherein during the packaging process, the packaging equipment is capable of determining the position of the chip to be packaged having a corresponding position relationship with the alignment point array based on the position of the alignment point array by identifying the position of the alignment point array.
4. The method as claimed in claim 1, wherein the step of performing a plating pretreatment on the first surface of the initial wafer to obtain a processed wafer comprises:
preparing a dielectric layer (3) on the first surface of the initial wafer; the dielectric layer (3) comprises a plurality of third through hole arrays, and each third through hole array in the plurality of third through hole arrays is used for exposing the corresponding electrode array;
preparing an electroplating seed layer (4) on the dielectric layer (3); the electroplating seed layer (4) comprises a plurality of groove arrays, and each groove array in the groove arrays corresponds to one electrode array.
5. The manufacturing method according to claim 4, wherein the solder points are manufactured in first through holes (10) of the plurality of first through hole arrays (801) and the alignment points are manufactured in second through holes (11) of the second through hole array (901) by using an electroplating process; removing the barrier layer (7) to obtain a target wafer-level chip with a plurality of welding spot arrays and alignment spot arrays on the surface, wherein the target wafer-level chip comprises:
preparing first solder columns in first through holes (10) of the plurality of first through hole arrays (801) and preparing second solder columns in second through holes (11) of the second through hole array (901) by using an electroplating process;
removing the plating seed layer (4) outside the first welding column and the second welding column and the barrier layer (7);
and performing reflux treatment on the first welding column and the second welding column to obtain the target wafer-level chip with the surface provided with a plurality of welding spot arrays and alignment spot arrays.
6. The method as claimed in claim 5, wherein after the reflowing the first and second solder columns to obtain the target wafer-level chip having a surface with a plurality of solder pad arrays and alignment point arrays, the method further comprises:
covering a protective film on the first surface of the target wafer-level chip to obtain a wafer to be ground; the protective film can fill array gaps in the welding spot array and the alignment point array and gaps between the welding spot array and the alignment point array; the thickness of the protective film is larger than the heights of the welding spot array and the alignment point array;
and grinding a second surface opposite to the first surface to obtain a ground wafer.
7. The method as claimed in claim 6, wherein after the polishing process is performed on the second surface opposite to the first surface to obtain the polished wafer, the method further comprises:
and carrying out slicing processing on the ground wafer to obtain a target chip.
8. The manufacturing method according to claim 4, wherein the thickness of the dielectric layer (3) is in a range of 3 to 10 μm.
9. The manufacturing method according to claim 4, wherein the material of the dielectric layer (3) comprises a low-temperature cured polymer material or a high-temperature cured polymer material.
10. A chip produced based on the method according to any one of claims 1 to 9.
CN202210473968.0A 2022-04-29 2022-04-29 Chip preparation method and chip Pending CN114864414A (en)

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