CN1148621C - Rapid on chip voltage generator for low power integrated circuit - Google Patents
Rapid on chip voltage generator for low power integrated circuit Download PDFInfo
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- CN1148621C CN1148621C CNB988143682A CN98814368A CN1148621C CN 1148621 C CN1148621 C CN 1148621C CN B988143682 A CNB988143682 A CN B988143682A CN 98814368 A CN98814368 A CN 98814368A CN 1148621 C CN1148621 C CN 1148621C
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Abstract
The present invention relates to a rapid chip internal voltage generator for a low power integrated circuit. A chip internal voltage generating circuit is provided to be used in the integrated circuit, such as a flash memory element which use low power supply voltage. The voltage generating circuit comprises a first level testing device and a second level testing device (209 and 210) and a lifting drive (204), wherein the voltage generating circuit is responsible for the output of the testing devices and pump electricity at a first speed rate and a second speed rate.
Description
Technical field
The present invention relates to be used in chip, to produce voltage generating technique in the chip of a voltage in the supply voltage scope that does not provide this chip; More particularly, relate at the low power memory device, as flash memory, mask rom and SRAM go up to produce word voltage, and wherein supply voltage may needed to read voltage low than being used to read in the storer data.
Background technology
The operating voltage of the integrated circuit of past manufacturing generally is 5 volts, its scope range of the fluctuation of voltage is+and/-10%.Certainly, also can use the supply voltage of other type.At present a lot of demands of applications are that design can be operated in than the integrated circuit in the low suppling voltage scope.In general, low supply voltage can carry out low-power operation to these devices, and uses battery to power in mini-plant easily.For example, be defined as in about 2.7V and in 3.6V, carried out work at a low suppling voltage as a standard.Other lower supply voltage standard is also just under development.
But for some purpose, often circuit is operated in higher voltage in the design chips.For example, in storage component part, flash memory for example provides the word line of a gate voltage to be designed to work in 4V or the higher voltage that reads usually to memory cell.Like this, low supply voltage just is not enough to the direct voltage that provides sufficiently high, can drive word line to a chip.By comprising that in integrated circuit charge pump or other power voltage supply lifter provide higher operating voltage on chip, just can address this problem.For example, see U.S. Patent No. 5,511,020, be entitled as " BOOSTED REGULATED POWER SUPPLY WITH REFERENCETRACKING FOR MULTI-DENSITY ANDLOW VOLTAGE SUPPLYMEMORIES ".This ' 026 patent described an integrated circuit memory of the charge pump with the word line voltage that is configured to provide higher than supply voltage.In addition, this ' 026 patent has been described the interior charge pump of use chip provides a plurality of word line voltages to many level/storage component parts, so that the work tolerance limit that normally can obtain with using a standard supply voltage is compared, can between memory cell state, obtain bigger work tolerance limit.
With in the prior art a relevant problem of charge pump in the chip that is used for these purposes is to be difficult to produce one by the output level of fine rectification and don't sacrifice speed.In the storage component part of a plurality of level in every unit, perhaps concerning the very little voltage devices of the work tolerance limit that reads voltage, the good level particular importance of rectification.But it also is desirable can reading apace.A charge pump output is established to a needed time of the good level of rectification usually can be to a read operation, and other operation that perhaps needs the output that charge pump produced to operate produces a big delay.
Summary of the invention
So hope can provide voltage feed circuit in the chip, being used for integrated circuit, and can provide more accurate control, and can operate fast voltage in the chip.
The invention provides an integrated circuit, its power input is used to the supply voltage in the pre-assigned voltage scope that is received in, and comprise the parts that use than voltage in the high chip of this pre-assigned voltage scope on this integrated circuit, this integrated circuit comprises:
A voltage lifting circuit is connected to the input of this supply voltage and is connected to one and promotes signal, and this promotes circuit and can respond to this saltus step that promotes signal, promotes on this integrated circuit voltage in the chip on the node, and comprises
One or more level has respective electrical container and driving circuit, and described capacitor has the first terminal that is connected to the node on the integrated circuit, and has second terminal, and described driving circuit is connected to second terminal of capacitor;
This voltage lifting circuit has at least one level, its first pattern is this saltus step to be responded the driving circuit in the enabled stage, thereby promote speed with first and promote voltage in the chip, up to first threshold, its second pattern is that the driving circuit in the enabled stage is so that after reaching this first threshold, promote speed with second and promote voltage in the chip, up to second threshold value, and stop to promote near second threshold value time, wherein the second lifting speed ratio, the first lifting speed is low; With
A testing circuit, be connected to the node that receives voltage in this chip on this integrated circuit, and also be connected to this voltage lifting circuit, this testing circuit signals to this voltage lifting circuit, and when this node reaches first threshold in expression, and also signaling to this voltage lifting circuit, when this node reaches second threshold value in expression.
According to an aspect of the present invention, integrated circuit comprises:
A memory cell array;
A plurality of word lines are connected to column of memory cells in this array;
A plurality of bit lines are connected to the row of memory cell in this array;
One group of word line driver is connected to a plurality of word lines, and this word line drives and drive a word line voltage on the selected word line of a node on this integrated circuit, and this word line voltage is imported pre-specialized range height than supply voltage;
Logic detects an incident on this integrated circuit, produces a saltus step that promotes signal;
Wherein said node is connected to described word line driver.
The present invention also provides an integrated circuit memory, has a power input that is used to the supply voltage in the pre-assigned voltage scope that is received in, and comprising:
A memory cell array;
At least one address input;
A plurality of word lines are connected to column of memory cells in this array;
A plurality of bit lines are connected to the row of memory cell in this array;
One group of word line driver is connected to a plurality of word lines, and this word line drives and drive a word line voltage on the selected word line of a node on this integrated circuit, and this word line voltage is imported pre-specialized range height than supply voltage;
Logic, detect an incident on this integrated circuit, variation at least one address input is responded, produce a precharging signal, behind this precharging signal, produce first saltus step that promotes signal, produce second saltus step that this promotes signal after this first saltus step, wherein this first and second pre-charge circuit responds to this precharging signal;
A voltage lifting circuit is connected to the input of this supply voltage, and receives this and promote signal, and this voltage lifting circuit is lifted at the word line voltage on the node on this integrated circuit, and this voltage lifting circuit comprises:
The first order, comprise first capacitor with first and second terminals, have an anode of second terminal that is connected to this capacitor and be connected to a diode of the negative electrode of the node on this integrated circuit, and a driver is connected to the first terminal of this capacitor, and provides first skip signal to this first capacitor; With
The second level, comprise second capacitor with the first terminal that is connected to the node on this integrated circuit, this second capacitor has second terminal, second driver is connected to this logic and is connected to second terminal of this second capacitor, and by provide electric current with first rate up to reaching first threshold, provide electric current up to reaching second threshold value with second speed, this second driver provides second saltus step that promotes signal to second terminal of this capacitor, wherein this first threshold is to reach in the time of lacking than 5 nanoseconds after second saltus step, and the second speed ratio first rate is low;
First pre-charge circuit, be connected to the anode of this diode, with one second pre-charge circuit that is connected to this node, before first skip signal, this second pre-charge circuit is pre-charged to a trigger voltage with the first terminal and this node of this second capacitor; With
A testing circuit is connected to the node that receives voltage in this chip on this integrated circuit, and also is connected to this voltage lifting circuit.This testing circuit signals to this voltage lifting circuit, and when this node reaches this first threshold in expression, and signaling to this voltage lifting circuit, when this node reaches this second threshold value in expression; Wherein this testing circuit comprises:
First detecting device, be connected to this node, provide one first control signal to this voltage lifting circuit in very first time that this node reaches first threshold at interval, this very first time at interval in, this voltage lifting circuit continuation promotes with first rate; With
Second detecting device is connected to this node, and in reaching one second time interval of second threshold value, this node provides one second control signal to this voltage lifting circuit, in this second time interval, this voltage lifting circuit continues to promote with second speed, so that the voltage that the voltage ratio that voltage increased in second time interval in the chip of this node is increased in very first time interval is few.
Description of drawings
Can be according to detailed description and claims of these figure and back, clearer others of the present invention and advantage.
Fig. 1 comprises the block diagram that an integrated circuit memory devices of circuit is provided according to voltage in the chip of the present invention.
Fig. 2 is the block diagram that employed in the system of Fig. 1, of the present invention word line promotes circuit.
Fig. 3 is a sequential chart that is used to describe the present invention's operation.
Fig. 4 is a circuit diagram according to a preferred implementation of lifting circuit of the present invention.
Fig. 5 is a circuit diagram of logic that is used to produce the employed skip signal of lifting circuit of Fig. 4.
Fig. 6 is a circuit diagram of a voltage level detector using with the combination of circuits of Fig. 4.
Fig. 7 is a circuit diagram of employed one second voltage level detector of the circuit of Fig. 4.
Fig. 8 is a circuit diagram of the employed pre-charge circuit of the circuit of Fig. 4.
Fig. 9 is a circuit diagram of employed one second pre-charge circuit of the circuit of Fig. 4.
Embodiment
With reference to figure 1-9, describe embodiments of the present invention in detail, wherein Fig. 1 is a synoptic chart that comprises a flash memory element of voltage feed circuit in the chip that is used to produce the read mode word line voltage.Like this, Fig. 1 has shown an integrated circuit.This integrated circuit comprises that being adjusted to a supply voltage that receives a supply voltage VDD imports 10.In an illustrative embodiments, this supply voltage is 2.7 to 3.6V.In addition, provide a ground input 11.Other input and output pin is included on this integrated circuit, comprises address input 12, and the control signal input is 13 and output enable inputs 14 of a chip enable input and data I/O pin 15 for example.
This integrated circuit comprises a flash memory array 16, comprises the floating boom transistor, a ROM cell array, for example mask rom unit, perhaps other memory cell.Array 16 comprises for example represented word line of arrow 17 of a plurality of usefulness.Word line is driven by a wordline decoder, this wordline decoder comprises a plurality of parts, comprise wordline decoder part 0, wordline decoder part 1, wordline decoder part 2, wordline decoder part 3, wordline decoder part 4, wordline decoder part 5, wordline decoder part 6, wordline decoder part 7 is in this example.In addition, column decoder and data input/output circuit 18 are connected in the array 16 with the represented a plurality of bit lines of arrow 19.This column decoder 18 and this wordline decoder 20 are controlled from input 12 addresses that received, address.The feature of this address is to comprise row address on online 21, comprises column address on online 22, and they drive wordline decoder 20 and column decoder 18 respectively.In addition, word line pre decoder 23 is comprised and is connected to address wire 12.Produce on this word line pre decoder online 24 and select control signal SEL (0-7), these select control signal to be provided to wordline decoder part 0-7 respectively.In this example, high 3 bits of the row address of the address on the line 12 part are used to control word line pre decoder 23, and select a specific wordline decoder part from wordline decoder 20.
Like this, as shown in Figure 1, the word line voltage that the present invention is used for the read mode of a flash memory element produces.The present invention's scope that is particularly suitable for for example is 2.7 flash memories to the low suppling voltage of 3.6V.The present invention also is suitable for ROM array and other need be at the device of a node booster tension, for example the node 30 on this integrated circuit.
Fig. 2 provides a word line voltage according to the present invention to promote a synoptic diagram block diagram of circuit.This circuit comprises an address change testing circuit 200, its receives as address input, on the integrated circuit, produce conduct is exported, address change detection signal ATD on online 201, produce one first address change on online 202 and detect generation one second address change detection pulse ATD2ND on the pulse ATD1ST and online 203.This second pulse ATD2ND on the line 203 is connected to the logic module 204 that a first order promotes driver and comprises a pumping capacitor C1.This pumping capacitor is connected to the anode of diode 205.The negative electrode of diode 205 is connected to the node 206 that produces voltage AVX.One second level promotes driver and logic module 207 also is connected to pulse ATD2ND that receives on the line 203 and the address change detection signal ATD that receives on the line 201.The output of second level module 207 promotes signal with one on the line 208 and is provided to a capacitor C2.One second terminal of this capacitor is connected to node 206, and produces generation one second control signal CT1SP on the one first control signal CT1 and online 212 on the difference online 211.These signals are provided to second level module 207, and the saltus step of the lifting signal on the line 208 is responded and the charge rate of control capacitor C2.
Word line voltage generator among Fig. 2 also comprises one first pre-charge circuit 215 and one second pre-charge circuit 216.This first and second pre-charge circuit 215,216 is pre-charged to a level near supply voltage with the anode of diode 205 and node 206, so that realize lifting process.Control signal comprises a chip enable CEL signal on the line 217, and on the line 218 one enables to be ready on signal ENRDYB and the line 219 one and enables address change detection signal ENATD and be provided to these pre-charge circuits.In addition, these pre-charge circuits respond to the first address change pulse ATD1ST signal on the line 202.
Fig. 3 is a sequential chart of the level of the AVX signal on this address change detection signal and the node 206.
Among Fig. 3, the address that is input to this address change detection signal is by represented with track 300.Address change detection signal on the line 201 is represented with track 301, and first address change detects pulse ATD1ST by represented with track 302, and second address change detects pulse by represented with track 303.The level of voltage AVX on the node 206 is by represented with track 304.
In this example, the level of the AVX signal on the line 304 from as point is 310 represented, about supply voltage level VDD.In the time 311, the address modification in the input of this integrated circuit.This impels at 311, one address change detection signals constantly and jumps to a high level state, and constantly 312, jumps to a low level state.The interval of ATD on the line 301 between the moment 311 and 312 approximately was 20 nanoseconds, in this example.This address change testing circuit 200 produces one in 311 beginnings constantly and in 312 one first pulses that finish constantly, and is represented as the ATD1ST signal on the line 302.This ATD2ND signal 313 is jumping to high level state constantly, 314 is changing to low level state constantly, and 314 near the moment 312 constantly.
The precharge that the lifting of node AVX is impelled from 311 ATD1ST pulse constantly.In the track 304 of Fig. 3, this precharge does not reflect that any level of AVX signal changes.But if before atd signal, this AVX signal is not precharged to the VDD level, and then, its level will be thus lifted near VDD.This pre-charge circuit also preconditioning capacitor C1 to rise to the level that is higher than VDD.
In the moment 313, the rising edge of ATD2ND signal, first order lifting pumping impels a saltus step on the capacitor C1.This anode with diode 205 rises to the level of node 206, and comprises an increase of AVX signal, and is represented as zone 315 between the moment 313 and 312.
Constantly 312, at the negative edge of atd signal, second level pumping the track 304 of 312 back constantly precipitous regional 316 in, make to promote signal 208 high speed saltus steps.In the moment 317, voltage level detector B 210 detects this AVX signal and has crossed a first threshold.This impels second level pumping to switch to a lower lifting speed, as just the zone 319 at the track 304 of 317 back constantly is represented.
In the moment 318, level detector A 209 detects this voltage level AVX and has reached a final threshold value, and produces control signal CT1 on online 211.This impels the pulling speed of second level pumping 207 to stop.
In this example, the fast lifting between the moment 312 and the moment 317 is lacked than 2 nanoseconds at interval, perhaps lacks than about 5 nanoseconds.Constantly 317 with 318 track 319 constantly during lowly promote rate interval and lack than about 10 nanoseconds, perhaps lack than about 20 nanoseconds.
Generally speaking, the low speed that promotes during the interval 319 allows feedback circuit to have more time to come that the final level of AVX signal is had more accurate control.Fast lifting speed during interval 316 has been quickened lifting process greatly, and does not sacrifice the accuracy of cut-off level.
Fig. 4,5,6,7,8 and 9 provide a detailed circuit diagram of voltage lifting circuit in a preferred embodiment of the invention.Fig. 4 has shown first order pumping and second level pumping.This first order pumping receives the second pulse ATD2ND on online 400.This signal passes through phase inverter 401, phase inverter 402, and phase inverter 403 and phase inverter 404 are provided to the first terminal of capacitor C1.Like this, the rising edge of the pulse ATD2ND on online 400, the signal on the first terminal of capacitor C1 changes to a high value from a low level value.Second terminal of capacitor C1 is connected to the anode of diode 405.The negative electrode of diode 405 is connected to the node 406 that produces AVX voltage.
Second level pumping comprises the second pulse ATD2ND on the line 400 and the address change detection signal ATD on the line 410.These signals are used as input and are provided to a rejection gate 411, and this rejection gate 411 provides input to a phase inverter 412.The output of phase inverter 412 is provided to the input that resets of a set-SR latch 413 that resets, and as an input of a rejection gate 414.An effectively low chip enable signal CEB 415 is provided to the set input of SR latch 413.The output of this SR latch is one second input of rejection gate 414.The output of rejection gate 414 drives phase inverter 416, and this phase inverter 416 drives phase inverter 417 again successively.Phase inverter 417 provides input to phase inverter 418 and phase inverter 419.The output of phase inverter 419 is connected to a first terminal of capacitor 420.One second terminal of capacitor 420 is connected to the source electrode of N channel transistor 421.The drain electrode of N channel transistor 421 is connected to supply voltage VDD.The grid of transistor 421 receives a control signal ENATD on the line 422.In addition, capacitor 420 is connected to the anode of a diode 423.The negative electrode of diode 423 is connected to node 406.At the duration of work of pump circuit, the control signal on the line 422 is drawn high the supply voltage level with the anode of diode 423.This circuit comprises phase inverter 419, capacitor 420 and transistor 421, and this transistor 421 is connected to 406 by diode 423, and this circuit working is under a precharge capacity.When this ENATD signal was low level, CEB set latch 413 impelled the output of phase inverter 419 to change.By capacitor 420 and diode 423, this rises to a pre-charge level with node 406, to help pre-charging functions.
When this address change sense enable signal is high level, enable to promote by phase inverter 418.Phase inverter 418 drives a two-mode phase inverter 425.The output of this two-mode phase inverter is a lifting signal that is connected to a capacitor C2 on the line 426.The Section Point of capacitor C2 is provided to terminal 406.This two-mode driver 425 has a supply voltage terminal that is connected to current source circuit, and this current source circuit comprises transistor 428,429, and 430 and 431.In this example, transistor 428 and 429 comprises that its width is 3 microns, and its length is 5 microns p channel transistor.In corresponding diode structure, transistor 428 and 429 grid and drain electrode are joined together.Transistorized N potential well is connected to their corresponding sources.Draw effect on a little less than these transistors provide one for the supply voltage terminal of driver 425, float to avoid it.
Lifting speed on the node 426 directly reflects by the capacitor C2 on the node 406, the track 304 of its mode such as Fig. 3.
CT1 and CT1SP control signal on transistor 430 and 431 the grid are produced by the level detector as shown in Fig. 6 and 7.This ATD1ST pulse and ATD2ND pulse are produced by circuit shown among Fig. 5.
Shown among Fig. 8 and 9, be used for setting up the pre-charge circuit that promotes operation and be connected to this and promote circuit at circuit.This first pre-charge circuit 490 is connected to the anode of diode 405.One second charging circuit 491 is connected to the node 406 at the negative electrode place that is positioned at diode 405.
ENRDYB, CEL, the control signal that CEB and ENATD control signal are to use the standard design logic to be produced.
Among Fig. 5, ATD1ST and ATD2ND signal are produced, and respond so that an address change on the line 500 is detected atd signal.For example, U.S. Patent Application Serial Number No.08/751 as co-applications, 513, be entitled as in " an address change testing circuit " shown, this atd signal is produced, this patent is on November 15th, 1996 application, and the people invented by Yin Liu etc., should invention when invention by the inventor all, at present, own for this same assignee.After an address signal changed, as shown in Figure 3, in this preferred implementation system, the ATD pulse of about 20 nanoseconds was produced.This signal is applied to a single-shot trigger circuit that comprises NAND door 501 and phase inverter 502.The input of atd signal line 500 is connected to the input of phase inverter 502, and is connected to an input of NADN door 501.The output of phase inverter 502 is connected to second input of Sheffer stroke gate 501.The output of NAND door 501 is provided to a phase inverter 503.Provide ATD1ST signal in the output of this phase inverter 503 online 436.This ATD1ST signal is provided to one second single-shot trigger circuit that comprises phase inverter 504 and rejection gate 505.This ATD1ST signal is connected to the input of phase inverter 504, and the output of phase inverter 504 is connected to an input of rejection gate 505.In addition, this ATD1ST signal is connected to second input of rejection gate 505.The output of rejection gate 505 is connected to the set input of a SR latch 506.In addition, the output of rejection gate 505 is connected to an input of rejection gate 507.Second input of rejection gate 507 is the atd signals on the line 500.The output of rejection gate 507 is connected to the input that resets of this SR latch 506.The output of SR latch 506 is connected to the input that resets of this SR latch 506.The Q output of SR latch 506 is connected to phase inverter 508, and this phase inverter 508 drives phase inverter 509 again successively.The output of phase inverter 509 is the ATD2ND signals on the line 400.
The first shown level detector produces this CT1SP signal among Fig. 6.The second shown level detector of Fig. 7 produces the CT1 signal.The triggering level of CT1SP signal is AVX, and it is lower than the triggering level of CT1 signal.This detecting device among Fig. 6 is enabled by the output of rejection gate 600, and the input of this rejection gate 600 is the CEB signals on the line 601, ATD1ST signal on the line 436 and the CT1 signal on the line 700.The output of rejection gate 600 is connected to the grid of transistor 603 by phase inverter 602.In addition, the output of phase inverter 600 is connected to the grid of transistor 604.When the output of rejection gate 600 was high level, transistor 604 was opened, and transistor 603 is closed, and enabled the operation of level detection circuit.
This level detection circuit comprises one first electric current pin, its receive as input, from the AVX signal of node 406.This node is connected to the source electrode and the N potential well of p channel transistor 605.The grid of p channel transistor 605 and drain electrode are connected to the source electrode and the N potential well of p channel transistor 606.The grid of transistor 606 and drain electrode are connected to the drain electrode of transistor 604.The source electrode of transistor 604 is connected to the drain electrode and the grid of N channel transistor 607.The source electrode of N channel transistor 607 is connected to ground.
The second electric current pin of this level detector electric current comprises a first node that is connected to this electric VDD that powers.The source electrode of a p channel transistor 610 and a p channel transistor 611 is connected to this supply voltage.The grid of transistor 610 and drain electrode are connected to the drain electrode of transistor 612.The grid of transistor 611 is connected to the output of phase inverter 613, and the input of phase inverter 613 is the SBCTL1 signals on the line 614, and this SBCTL1 signal is that the output from phase inverter 602 provides.Like this, when the SBCTL1 signal was high level, the signal on the grid of transistor 611 was a low level, made the electric current of an increase flow through this circuit.
The source electrode of transistor 612 is connected to ground.The grid of transistor 612 is connected to the grid of transistor 604, and its connected mode is a current mirror mode.In addition, the grid of the grid of transistor 612 and transistor 607 is connected to the drain electrode of transistor 603.Node NISP on the drain electrode of transistor 612 is used as input and is connected to a phase inverter 615.The output of this phase inverter 615 is connected to the S input of a SR latch 616.The input that resets of this SR latch 616 is connected to the ATD1ST signal that receives on the line 436.The Q output of SR latch 616 is connected to phase inverter 617, and this phase inverter 617 drives phase inverter 618.The output of phase inverter 618 is the control signal CT1SP on the line 620.At work, when signal AVX increased, the electric current that flows through the current mirror pin of detecting device increased.When the electric current that flows through transistor 610 increased, voltage NISP just descended.When NISP voltage drops to when lower than the tripping point of phase inverter 615, latch 616 is set and produces the CT1SP signal.
Fig. 7 has shown the level detector that is used to produce the CT1 signal.This level detector is enabled by the output of a rejection gate 701, and the CEB signal that this rejection gate 701 receives on the line 601 receives the ATD1ST signal on the line 436.The output of rejection gate 701 is connected to the grid of N channel transistor 702, is connected to the input of phase inverter 703.The output of phase inverter 703 is connected to the grid of N channel transistor 704.The drain electrode of transistor 704 is connected to node 705.The source electrode of transistor 704 is connected to ground.Like this, when the output of rejection gate 701 became high level, this circuit was enabled by closing transistor 704 and opening transistor 702.In addition, the output of phase inverter 703 produces control signal SBCTL, and this control signal SBCTL is provided to the input of phase inverter 706.A high level in the input of phase inverter 706 is opened transistor 707.
This level detector comprises the one first electric current pin that is connected to voltage AVX on the node 406.Node 406 is connected to the source electrode and the N potential well of p channel transistor 708.The grid of transistor 708 and drain electrode are connected to the source electrode and the N potential well of p channel transistor 709.The grid of transistor 709 and drain electrode are connected to the source electrode and the N potential well of transistor 710 and are connected to the source electrode and the N potential well of transistor 711.The grid of transistor 710 is connected to the control signal CT1 that receives on the line 700.The drain electrode of the grid of transistor 711 and drain electrode and transistor 710 is connected to the grid and the drain electrode of N channel transistor 712.The source electrode of transistor 712 is connected to the grid and the drain electrode of one three potential well N channel transistor 713.The isolation potential well of transistor 713 is connected to AVX node 406.The P potential well of transistor 713 and source electrode are connected to the drain electrode of transistor 702.The source electrode of transistor 702 is connected to the drain electrode and the grid of the transistor 714 of node 705.The source electrode of transistor 714 is connected to ground.
The second electric current pin of this level detector comprises transistor 707, and the source electrode of transistor 707 is connected to supply voltage, and its drain electrode is connected to the drain electrode of transistor 715.The source electrode of transistor 715 is connected to ground.The pre-transistor 714 of the grid of transistor 715 is connected to 705 together.In addition, the source electrode of transistor 716 is connected to supply voltage, and its grid and drain electrode are connected to the drain electrode of transistor 715.
The working method of this circuit such as top with reference to figure 6 description, except threshold value is higher.Like this, when voltage level AVX increased, the electric current that flows through the current mirror pin increased.When this electric current reached a specific current value, the voltage on the input node NI of phase inverter 717 reached the tripping point of this phase inverter.The output of phase inverter 717 is connected to the set input of a SR latch 718.The Q output of SR latch 718 is connected to phase inverter 719, and phase inverter 719 drives phase inverter 720 conversely.The output of phase inverter 720 is the CT1 signals on the line 700.The input that resets on the SR latch 718 receives the ATD1ST signal on online 436.
When the CT1 signal became high level, transistor 710 was closed.This has reduced the electric current that flows through level detector, and has saved the energy of this circuit.
Here shown level sensitive circuit is formed this preferred implementation.The level sensitive circuit method that much can be utilized according to the present invention is arranged.Should understand, because according to the present invention during the first order of pumping, the AVX voltage level increases fast, therefore use the circuit of Fig. 6 and 7, perhaps the level detector of other type detects when the AVX level is floating to be moved, and is related, be very important less than the delay of 1 nanosecond order to closing accurately.According to the present invention, by when this level reaches desirable cut-off level, reduce promoting speed, solved with the timing of these detecting devices be tuned in a nanosecond or the scope still less, with the lift level of AVX signal ability by the end of a preferred predetermined level.Like this, between the CT1SP signal and the relative timing that finally reaches lifting be not too important.According to the present invention, avoided the condition of an overshoot, and allowed fast lifting.
Fig. 8 has shown first pre-charge circuit 490.It receives an ATD pulse ATD1ST signal that enables on atd signal and the reception line 436 as on the line 435 of input signal.These signals are provided to a Sheffer stroke gate 437 as input, and the output of Sheffer stroke gate 437 has driven phase inverter 438.The output of phase inverter 438 is connected to the source electrode and the drain electrode of the transistor 439 that has connected capacitor.The grid of transistor 439 is connected to the grid of N channel transistor 440.The source electrode of N channel transistor 440 is connected to line 432, and line 432 is connected to the anode of diode 405, and the drain electrode of transistor 440 is connected to supply voltage VDD.The grid of transistor 440 is comprised that a circuit of p channel transistor 441 setovers, the source electrode of this p channel transistor 441 is connected to supply voltage VDD, its grid is connected to the control signal ENRDYB on the line 442, and its drain electrode is connected to the anode of a diode 443.The negative electrode of diode 443 is connected to the grid of transistor 440.The drain electrode of a transistor 444 is connected to the grid of transistor 440, and its source electrode is connected to ground.The grid of transistor 446 is connected to the control signal ENRDYB on the line 442.At work, the grid of transistor 440 responds to a low signal on the ENRDYB terminal on the line 442, is connected to a level, and this level is that transistor 441 below supply voltage and the voltage drop on the diode 443 are determined.When the control signal CEL on the line 445 became high level, this node was connected to ground.Similarly, when this control signal ENRDYB became high level, this node was connected to ground by transistor 446.
In addition, pre-charge circuit comprises transistor 450, and the grid and the drain electrode of transistor 450 are connected to supply voltage, and its source electrode is connected to the anode of diode 405 by line 430.This transistor 450 that connects into diode maintains low threshold voltage drop than VDD with the voltage of this node when beginning.This ATD1ST is responded, and the grid of transistor 440 is raised so that the threshold value pressure drop on transistor 440 and 450 is compensated, so that the anode of diode 405 is drawn high the VDD level.
Second pre-charge circuit is displayed among Fig. 9, and similar with first pre-charge circuit.It receives the ATD1ST signal on ENATD signal on the line 435, the conduct input and the reception line 436.These signals are used as input and are provided to a Sheffer stroke gate 457, and this Sheffer stroke gate 457 drives phase inverter 458.Phase inverter 458 is connected to the source electrode and the drain electrode of the transistor 459 that has connected a capacitor.The grid of transistor 459 is connected to the grid of transistor 460.The grid of transistor 460 is also comprised, and the circuit of p channel transistor 461 setovers, and the source electrode of p channel transistor 461 is connected to supply voltage VDD, and its drain electrode is connected to the grid of transistor 460 by diode 462.Transistor 463 and 464 is N channel transistors, and their drain electrode is connected to the grid of transistor 460, and their source electrode is connected to ground.The grid of transistor 463 receives the CEL control signal on online 445.The grid of the grid of transistor 461 and transistor 464 receives as control signal ENRDYB input, on the line 442.
Second pre-charge circuit also comprises transistor 470, and the grid of transistor 470 and drain electrode are connected to supply voltage VDD, and its source electrode is connected to line 431, is connected to node 406 again.
In this exemplary circuit, the relative size of the circuit block of Fig. 4-9 and parameter are as shown in the following table:
| Capacitor C1 | 150 pico farads |
| Capacitor C2 | 250 pico farads |
| Capacitor 420 | 40 pico farads |
| Phase inverter 425 | P channel width: 250 microns P channel lengths: 0.5 micron N channel width: 250 microns N channel lengths: 0.5 micron |
| Transistor 430 | 0.5 micron of 50 microns length of width |
| Transistor 431 | 0.5 micron of 250 microns length of width |
| Transistor 421 | 1.3 microns of 460 microns length of width |
| Transistor 441 | 0.5 micron of 10 microns length of width |
| Transistor 440 | 1.3 microns of 950 microns length of width |
| Transistor 450 | 95 microns of width |
| 1.3 microns of length | |
| Transistor 439 | 46 microns of 91.4 microns length of width |
| Transistor 446 | 1 micron of 4 microns length of width |
| Transistor 444 | 30 microns of 2 microns length of width |
| Transistor 459 | 46 microns of 91.4 microns length of width |
| Transistor 464 | 1 micron of 4 microns length of width |
| Transistor 463 | 30 microns of 2 microns length of width |
| Transistor 461 | 0.5 micron of 10 microns length of width |
| Transistor 460 | 1.3 microns of 940 microns length of width |
| Transistor 470 | 1.3 microns of 47 microns length of width |
| Transistor 605 | 1.5 microns of 200 microns length of width |
| Transistor 606 | 1.5 microns of 200 microns length of width |
| Transistor 604 | 1.5 microns of 200 microns length of width |
| Transistor 607 | 1 micron of 50 microns length of width |
| Transistor 610 | 50 microns of 3 microns length of width |
| Transistor 611 | 0.5 micron of 20 microns length of width |
| Transistor 612 | 1 micron of 300 microns length of width |
| Transistor 702 | 1.5 microns of 200 microns length of width |
| Transistor 708 | 1.5 microns of 200 microns length of width |
| Transistor 709 | 1.5 microns of 200 microns length of width |
| Transistor 710 | 1.5 microns of 50 microns length of width |
| Transistor 711 | 1.5 microns of 200 microns length of width |
| Transistor 712 | 1.5 microns of 200 microns length of width |
| Transistor 714 | 1 micron of 50 microns length of width |
| Transistor 707 | 0.5 micron of 20 microns length of width |
| Transistor 716 | 50 microns of 3 microns length of width |
| Transistor 715 | 1 micron of 300 microns length of width |
Top transistor size that proposes and capacitor parameters are the expressions of a specific implementations designing of the requirement according to a certain semiconductor devices.To any given situation, the various variations in these transistorized relative sizes and the parts are suitable.But they only are to increase understanding to the work of this exemplary circuit as a details.
So a two-mode that discloses the read operation that is suitable for flash memories and other storage component part promotes circuit.This circuit also is fit to other environment, wherein wishes to have a lifting fast and a cut-off level accurately can be arranged.For example, concerning multi-level-cell, accurate cut-off level is more important, and multi-level-cell depends on the very strict tolerance limit of the word line voltage of the various level that are used to read this unit.
The aforementioned description of a preferred embodiment of the present invention is provided, and is used for showing and describing.The present invention is not limited to disclosed precise forms.Obviously, concerning these those of skill in the art, can carry out a lot of modifications and variations.Scope of the present invention is defined by following claims and their equivalence.
Claims (21)
1. integrated circuit, its power input are used to the supply voltage in the pre-assigned voltage scope that is received in, and comprise the parts that use than voltage in the high chip of this pre-assigned voltage scope on this integrated circuit, and this integrated circuit comprises:
A voltage lifting circuit is connected to the input of this supply voltage and is connected to one and promotes signal, and this promotes circuit and can respond to this saltus step that promotes signal, promotes on this integrated circuit voltage in the chip on the node, and comprises
One or more level, have the respective electrical container (C1, C2) and driving circuit (204,207), described capacitor have the node that is connected on the integrated circuit (206, the first terminal AVX), and have second terminal, and described driving circuit is connected to second terminal of capacitor;
This voltage lifting circuit has at least one level (C2,207), and its first pattern is, this saltus step is responded, driving circuit in the enabled stage promotes voltage in the chip thereby promote speed with first, up to first threshold, its second pattern is, driving circuit in the enabled stage promotes speed with second and promotes voltage in the chip, up to second threshold value so that after reaching this first threshold, and stop to promote near second threshold value time, wherein the second lifting speed ratio, the first lifting speed is low; With
A testing circuit (209,210), be connected to the node that receives voltage in this chip on this integrated circuit, and also be connected to this voltage lifting circuit, this testing circuit signals to this voltage lifting circuit, and when this node reaches first threshold in (CT1SP) expression, and also signaling to this voltage lifting circuit, when this node reaches second threshold value in (CT1) expression.
2. integrated circuit as claimed in claim 1, wherein testing circuit comprises:
First detecting device (209), be connected to this node, provide first control signal to this voltage lifting circuit in very first time that this node reaches first threshold at interval, this very first time at interval in, this voltage lifting circuit continuation promotes with first rate; With
Second detecting device (210) is connected to this node, and in reaching second time interval of second threshold value, this node provides second control signal to this voltage lifting circuit, in this second time interval, this voltage lifting circuit continues to promote with second speed, so that the voltage that the voltage ratio that voltage increased in second time interval in the chip of this node is increased in very first time interval is few.
3. integrated circuit as claimed in claim 1, wherein driving circuit comprises:
A phase inverter (425), an one input are connected to arrive and receive this lifting signal, and an output is connected to second terminal of this capacitor, and has first and second power supply terminals; With
A current source (428-431) is connected in first and second power supply terminals, and has with first rate and first pattern of electric current is provided and has second pattern that electric current is provided with second speed.
4. integrated circuit as claimed in claim 1, wherein voltage lifting circuit comprises:
The first order, comprise first capacitor (C1) with first and second terminals, have an anode of second terminal that is connected to this capacitor and be connected to the diode (205) of the negative electrode of the node on this integrated circuit, and a driving circuit (204) is connected to the first terminal of this capacitor, and provides first skip signal to this first capacitor; With
The second level, comprise second capacitor (C2) with the first terminal that is connected to the node on this integrated circuit, this second capacitor has second terminal, second driving circuit (207) is connected to second terminal of this second capacitor, and by during first pattern, providing electric current (208) with first rate, provide electric current with second speed during second pattern, this second driving circuit provides the saltus step that promotes signal to second terminal of this capacitor.
5. integrated circuit as claimed in claim 4, first pre-charge circuit (215) that comprises the anode that is connected to diode, with second pre-charge circuit (216) that is connected to this node, before first skip signal, this second pre-charge circuit is pre-charged to a trigger voltage with the first terminal and this node of this second capacitor.
6. integrated circuit as claimed in claim 5, comprise at least one address input (ADDR), wherein this logic (200) comprises a circuit, this circuit responds to the variation at least one address input and produces a precharging signal (ATD1ST), behind precharging signal, produce first variable signal (ATD2ND), produce the variation (ATD negative edge) that promotes signal behind this first variable signal, wherein first and second pre-charge circuits respond to this precharging signal.
7. integrated circuit as claimed in claim 4, comprise at least one address input (ADDR), wherein this logic (200) comprises the variation in the input of at least one address is responded and produces first variable signal, and produces the circuit of the variation that promotes signal behind first variable signal.
8. integrated circuit as claimed in claim 4 comprises logic (200), and an incident is responded, and produces the saltus step of first skip signal and lifting signal.
9. integrated circuit as claimed in claim 1, wherein this voltage lifting circuit reaches first threshold in this promotes 5 nanoseconds of signal saltus step.
10. integrated circuit as claimed in claim 1, wherein this voltage lifting circuit perhaps still less, reaches first threshold in this promotes 2 nanoseconds of signal saltus step.
11. integrated circuit as claimed in claim 1 comprises:
A memory cell array (16);
A plurality of word lines (17) are connected to column of memory cells in this array;
A plurality of bit lines (19) are connected to the row of memory cell in this array;
One group of word line driver (20) is connected to a plurality of word lines, drives a word line voltage on the selected word line of the node (AVX, 30) of this word line driving on this integrated circuit, and this word line voltage is imported pre-specialized range height than supply voltage;
Logic (33) detects an incident on this integrated circuit, produces a saltus step that promotes signal;
Wherein said node is connected to described word line driver.
12. as the integrated circuit of claim 11, comprise at least one address input (12), wherein this logic (33) comprises that variation at least one address input responds and produces a circuit of the variation that promotes signal (ATD, 35).
13. as the integrated circuit of claim 11, wherein this memory cell array comprises ROM cell.
14. as the integrated circuit of claim 11, wherein this memory cell array comprises the floating-gate memory unit.
15. as the integrated circuit of claim 11, wherein this promotes circuit in this promotes 5 nanoseconds of signal saltus step, reaches first threshold.
16. as this integrated circuit of claim 11, wherein this promotes circuit in this promotes 2 nanoseconds of signal saltus step, perhaps still less, reaches first threshold.
17. an integrated circuit memory has a power input that is used to the supply voltage in the pre-assigned voltage scope that is received in, and comprising:
A memory cell array;
At least one address input;
A plurality of word lines are connected to column of memory cells in this array;
A plurality of bit lines are connected to the row of memory cell in this array;
One group of word line driver is connected to a plurality of word lines, and this word line drives and drive a word line voltage on the selected word line of a node on this integrated circuit, and this word line voltage is imported pre-specialized range height than supply voltage;
Logic, detect an incident on this integrated circuit, variation at least one address input is responded, produce a precharging signal, behind this precharging signal, produce first saltus step that promotes signal, produce second saltus step that this promotes signal after this first saltus step, wherein this first and second pre-charge circuit responds to this precharging signal;
A voltage lifting circuit is connected to the input of this supply voltage, and receives this and promote signal, and this voltage lifting circuit is lifted at the word line voltage on the node on this integrated circuit, and this voltage lifting circuit comprises:
The first order, comprise first capacitor with first and second terminals, have an anode of second terminal that is connected to this capacitor and be connected to a diode of the negative electrode of the node on this integrated circuit, and a driver is connected to the first terminal of this capacitor, and provides first skip signal to this first capacitor; With
The second level, comprise second capacitor with the first terminal that is connected to the node on this integrated circuit, this second capacitor has second terminal, second driver is connected to this logic and is connected to second terminal of this second capacitor, and by provide electric current with first rate up to reaching first threshold, provide electric current up to reaching second threshold value with second speed, this second driver provides second saltus step that promotes signal to second terminal of this capacitor, wherein this first threshold is to reach in the time of lacking than 5 nanoseconds after second saltus step, and the second speed ratio first rate is low;
First pre-charge circuit, be connected to the anode of this diode, with one second pre-charge circuit that is connected to this node, before first skip signal, this second pre-charge circuit is pre-charged to a trigger voltage with the first terminal and this node of this second capacitor; With
A testing circuit is connected to the node that receives voltage in this chip on this integrated circuit, and also is connected to this voltage lifting circuit.This testing circuit signals to this voltage lifting circuit, and when this node reaches this first threshold in expression, and signaling to this voltage lifting circuit, when this node reaches this second threshold value in expression; Wherein this testing circuit comprises:
First detecting device, be connected to this node, provide one first control signal to this voltage lifting circuit in very first time that this node reaches first threshold at interval, this very first time at interval in, this voltage lifting circuit continuation promotes with first rate; With
Second detecting device is connected to this node, and in reaching one second time interval of second threshold value, this node provides one second control signal to this voltage lifting circuit, in this second time interval, this voltage lifting circuit continues to promote with second speed, so that the voltage that the voltage ratio that voltage increased in second time interval in the chip of this node is increased in very first time interval is few.
18. as the integrated circuit memory of claim 17, wherein this second driver comprises:
A phase inverter, an one input are connected to arrive and receive this lifting signal, and an output is connected to second terminal of this capacitor, and this phase inverter has first and second power supply terminals; With
A current source is connected in first and second power supply terminals, and has with first rate and first pattern of electric current is provided and has second pattern that electric current is provided with second speed.
19. as the integrated circuit memory of claim 17, wherein this memory cell array comprises ROM cell.
20. as the integrated circuit memory of claim 17, wherein this memory cell array comprises the floating-gate memory unit.
21., wherein in 2 nanoseconds of this second saltus step, perhaps still less, reach first threshold as the integrated circuit memory of claim 17.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US1998/024766 WO2000029919A1 (en) | 1998-11-18 | 1998-11-18 | Rapid on chip voltage generation for low power integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1327552A CN1327552A (en) | 2001-12-19 |
| CN1148621C true CN1148621C (en) | 2004-05-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB988143682A Expired - Lifetime CN1148621C (en) | 1998-11-18 | 1998-11-18 | Rapid on chip voltage generator for low power integrated circuit |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1151365B1 (en) |
| JP (1) | JP4394835B2 (en) |
| CN (1) | CN1148621C (en) |
| DE (1) | DE69823888T2 (en) |
| HK (1) | HK1042954A1 (en) |
| WO (1) | WO2000029919A1 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6646950B2 (en) * | 2001-04-30 | 2003-11-11 | Fujitsu Limited | High speed decoder for flash memory |
| WO2004109711A1 (en) * | 2003-06-05 | 2004-12-16 | Fujitsu Limited | Semiconductor memory having booster circuit for redundant memory |
| CN1323434C (en) * | 2003-09-02 | 2007-06-27 | 台湾积体电路制造股份有限公司 | Method for mfg. intergration flash memory and high-voltage assembly |
| US7466620B2 (en) * | 2006-01-04 | 2008-12-16 | Baker Mohammad | System and method for low power wordline logic for a memory |
| US7529117B2 (en) * | 2007-03-07 | 2009-05-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Design solutions for integrated circuits with triple gate oxides |
| CN101620886B (en) * | 2008-07-02 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Word line supercharger for flash memory |
| JP5808937B2 (en) * | 2011-04-20 | 2015-11-10 | ラピスセミコンダクタ株式会社 | Internal power supply voltage generation circuit and internal power supply voltage generation method for semiconductor memory |
| CN108958639B (en) * | 2017-05-19 | 2021-07-06 | 华邦电子股份有限公司 | Flash memory storage device |
| JP2021149999A (en) | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | Semiconductor storage device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR910004737B1 (en) * | 1988-12-19 | 1991-07-10 | 삼성전자 주식회사 | Back bias voltage generating circuit |
| KR0172337B1 (en) * | 1995-11-13 | 1999-03-30 | 김광호 | Semiconductor memory device |
| US5708387A (en) * | 1995-11-17 | 1998-01-13 | Advanced Micro Devices, Inc. | Fast 3-state booster-circuit |
| JPH09320267A (en) * | 1996-05-28 | 1997-12-12 | Oki Micro Design Miyazaki:Kk | Boosting circuit driving method and boosting circuit |
-
1998
- 1998-11-18 JP JP2000582864A patent/JP4394835B2/en not_active Expired - Lifetime
- 1998-11-18 CN CNB988143682A patent/CN1148621C/en not_active Expired - Lifetime
- 1998-11-18 EP EP98960305A patent/EP1151365B1/en not_active Expired - Lifetime
- 1998-11-18 DE DE69823888T patent/DE69823888T2/en not_active Expired - Lifetime
- 1998-11-18 WO PCT/US1998/024766 patent/WO2000029919A1/en active IP Right Grant
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2002
- 2002-06-13 HK HK02104437A patent/HK1042954A1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| EP1151365B1 (en) | 2004-05-12 |
| HK1042954A1 (en) | 2002-08-30 |
| EP1151365A1 (en) | 2001-11-07 |
| DE69823888T2 (en) | 2004-10-21 |
| WO2000029919A1 (en) | 2000-05-25 |
| CN1327552A (en) | 2001-12-19 |
| JP2003517719A (en) | 2003-05-27 |
| DE69823888D1 (en) | 2004-06-17 |
| EP1151365A4 (en) | 2002-01-30 |
| JP4394835B2 (en) | 2010-01-06 |
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