CN114859608A - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
- Publication number
- CN114859608A CN114859608A CN202210389700.9A CN202210389700A CN114859608A CN 114859608 A CN114859608 A CN 114859608A CN 202210389700 A CN202210389700 A CN 202210389700A CN 114859608 A CN114859608 A CN 114859608A
- Authority
- CN
- China
- Prior art keywords
- array substrate
- conductive particles
- bonding
- substrate
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000002245 particle Substances 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 239000004973 liquid crystal related substance Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application discloses array substrate and preparation method, display panel thereof, wherein, array substrate, including the base plate, the base plate includes display area and nation fixed area, be provided with the pixel on the display area, array substrate still includes conductive particle, be provided with the pad on the nation fixed area, the pad has the bellying, part conductive particle set up in on the bellying. Through the mode, the contact area between the bonding pad and the conductive particles can be reduced, and therefore the pressure required when the conductive particles are crushed can be reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
With the development of the photoelectric Display technology and the semiconductor manufacturing technology, a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has become the mainstream of a Display device due to its advantages of lightness, thinness, energy saving, high Display quality, and the like, and the manufacturing process is mature and stable. In order to enable the display to normally display a desired image, a bonding (driving) driving IC, a PCB board, and other control elements are required on the LCD panel. Currently, anisotropic conductive Adhesive (ACF) is commonly used as a material for connecting a bonding pad of an LCD panel to a control device, and the material needs to apply a large pressure during bonding to crush conductive particles in the ACF (the conductive particles in the ACF are covered with an insulating material to prevent the conductive particles in the ACF from being conducted with each other in a horizontal direction, and the conductive particles in the ACF can be normally conducted in a vertical direction after being crushed). However, the pressure required is relatively high, which can result in damage to the edge structure of the panel.
Disclosure of Invention
The technical problem mainly solved by the application is to provide an array substrate, a preparation method thereof and a display panel, so as to reduce pressure applied by bonding timing and improve product yield.
For solving the technical problem, a first technical scheme that this application adopted provides an array substrate, which comprises a substrate, the base plate includes area of occurrence and nation fixed area, be provided with the pixel on the area of occurrence, array substrate still includes conductive particle, be provided with the pad on the nation fixed area, the pad has the bellying, part conductive particle set up in on the bellying.
Wherein the boss comprises at least one metal post.
The metal column is in a sharp-pricked structure, and the tip of the metal column faces the conductive particles.
Wherein the number of the bonding pads is at least two; an insulating groove is formed between every two adjacent bonding pads, part of the conductive particles are arranged in the insulating groove, and the conductive particles in the insulating groove and the conductive particles outside the insulating groove are separated by the insulating groove.
Wherein the height of the bonding pad is smaller than that of the insulation groove.
In order to solve the above technical problem, a second technical solution adopted by the present application is to provide a display panel, where the display panel includes: a color film substrate; the array substrate is arranged opposite to the color film substrate; the liquid crystal layer is clamped between the color film substrate and the array substrate; wherein, the array substrate is any one of the array substrates.
In order to solve the above technical problem, a third technical solution adopted by the present application is to provide a method for manufacturing an array substrate, where the method for manufacturing an array substrate includes: providing a substrate, and determining a display area and a bonding area of the substrate; manufacturing a patterned first metal layer on the substrate, wherein the first metal layer in the bonding area comprises a pad with a bulge part; manufacturing a first insulating layer on the first metal layer; etching the first insulating layer of the bonding area to expose the protruding part outside the first insulating layer; manufacturing elements of the display area; and adding conductive particles into the bonding area, wherein part of the conductive particles are arranged on the convex part.
Wherein the boss comprises at least one metal post; the metal column is in a vertical bar structure, or the metal column is in a sharp thorn-shaped structure, and the tip of the metal column faces the conductive particles.
Wherein the number of the bonding pads is at least two; the etching the first insulating layer of the bonding region to expose the protruding portion outside the first insulating layer includes: and etching the first insulating layer of the bonding area, and processing the first insulating layer of the bonding area into a groove shape to form an insulating groove between two adjacent bonding pads.
Wherein the height of the bonding pad is smaller than that of the insulation groove.
The beneficial effect of this application is: being different from the prior art, the application provides an array substrate and a preparation method thereof, display panel, array substrate includes the base plate, the base plate includes display area and bonding area, be provided with the pixel on the display area, array substrate still includes conductive particle, through will set up the pad on bonding area, the pad has the bellying, partial conductive particle sets up on the bellying, can reduce the area of contact between pad and the conductive particle, make the pressure increase, thereby can reduce the required pressure when the bonding breaks conductive particle, avoid panel edge structure impaired, thereby improve the product yield.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic cross-sectional structure diagram of a first embodiment of an array substrate of the present application;
FIG. 2 is a schematic cross-sectional view of a second embodiment of an array substrate of the present application;
FIG. 3 is a schematic cross-sectional view of a third embodiment of an array substrate of the present application;
FIG. 4 is a schematic flow chart illustrating a first embodiment of a method for fabricating an array substrate according to the present application;
fig. 5 is a schematic cross-sectional view of the structure of fig. 4 after step S43 is completed;
fig. 6 is a schematic cross-sectional view of the completed step S44 in fig. 4;
FIG. 7 is a schematic top view of the structure of FIG. 4 after step S46 is completed;
fig. 8 is a schematic view of the cross-sectional structure of the PP of fig. 7.
10, an array substrate; 100. a substrate; 101. conductive particles; 102. a pad; 1020. a boss portion; 103. an insulating groove; 104. a first metal layer; 105. a first insulating layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plural" includes at least two in general, but does not exclude the presence of at least one.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Referring to fig. 1, fig. 1 is a schematic cross-sectional structure diagram of an array substrate according to a first embodiment of the present application. In this embodiment, the array substrate 10 includes a substrate 100, the substrate 100 includes a display area a-a and a bonding area B-B, pixels (not shown) are disposed on the display area a-a, the array substrate 10 further includes conductive particles 101, a pad 102 is disposed on the bonding area B-B, the pad 102 has a protrusion 1020, and a portion of the conductive particles 101 is disposed on the protrusion 1020.
Through the manner, the bonding pad 102 is arranged on the bonding area B-B, the bonding pad 102 is provided with the protruding portion 1020, and part of the conductive particles 101 are arranged on the protruding portion 1020, so that the contact area between the bonding pad 102 and the conductive particles 101 can be reduced, the pressure intensity is increased, the bonding pressure required when the insulating layer covering the conductive particles 101 is crushed can be reduced, the damage of the edge structure of the array substrate 10 is avoided, and the product yield is improved.
In a preferred embodiment, the boss 1020 includes at least one metal post. Specifically, the metal pillar may have a vertical bar structure, and by providing the protrusion 1020 of the pad 102 in the form of the metal pillar, the contact area between the pad 102 and the conductive particle 101 may be reduced, so that the pressure required when the conductive particle 101 is crushed during bonding may be reduced. Alternatively, the protrusion 1020 of the pad 102 may be in the form of a plurality of metal posts arranged such that the conductive particles 101 are easily disposed on the protrusion 1020 of the pad 102.
Referring to fig. 2, fig. 2 is a schematic cross-sectional structure diagram of an array substrate according to a second embodiment of the present application. In this embodiment, the array substrate 10 includes a substrate 100, the substrate 100 includes a display area a-a and a bonding area B-B, pixels are disposed on the display area a-a, the array substrate 10 further includes conductive particles 101, a pad 102 is disposed on the bonding area B-B, the pad 102 has a protrusion 1020, a portion of the conductive particles 101 is disposed on the protrusion 1020, the protrusion 1020 includes at least one metal pillar, and the metal pillar is a spike-shaped structure, for example, a cone-shaped structure, and a tip of the metal pillar faces the conductive particles 101. By changing the metal shape of the pad 102 region from the original plane shape to the pointed structure, the contact area between the pad 102 and the conductive particles 101 can be reduced, so that the pressure is increased, the bonding pressure required when the insulating layer covering the conductive particles 101 is crushed can be reduced, and other structures of the array substrate 10 are prevented from being damaged.
Referring to fig. 3, fig. 3 is a schematic cross-sectional structure diagram of a third embodiment of an array substrate according to the present application. In this embodiment, the array substrate 10 includes a substrate 100, the substrate 100 includes a display area a-a and a bonding area B-B, pixels are disposed on the display area a-a, the array substrate 10 further includes conductive particles 101, a pad 102 is disposed on the bonding area B-B, the pad 102 has a protrusion 1020, and a portion of the conductive particles 101 is disposed on the protrusion 1020. The number of pads 102 is at least two; an insulating groove 103 is arranged between two adjacent bonding pads 102, part of the conductive particles 101 are arranged in the insulating groove 103, and the conductive particles 101 in the insulating groove 103 are separated from the conductive particles 101 outside the insulating groove 103 by the insulating groove 103. By arranging the insulating groove 103 between the two adjacent bonding pads 102, the insulating groove 103 can separate the conductive particles 101 on the two adjacent bonding pads 102, so that the problem of short circuit caused by left-right conduction between the conductive particles 101 crushed by bonding on the two adjacent bonding pads 102 can be avoided, and the product yield is improved. In addition, because the insulating groove 103 is arranged between two adjacent pads 102, part of the conductive particles 101 are arranged in the insulating groove 103, and the conductive particles 101 in the insulating groove 103 are separated from the conductive particles 101 outside the insulating groove 103 by the insulating groove 103, the probability that the conductive particles 101 in the insulating groove 103 are crushed during bonding is low, so that the probability that the conductive particles 101 on two adjacent pads 102 are conducted left and right to cause short circuit can be further reduced, and the product yield is improved.
In a preferred embodiment, with continued reference to fig. 3, the height of the bonding pad 102 is less than the height of the insulating trench 103. It can be understood that, by arranging the insulating groove 103 higher than the pads 102, the conductive particles 101 on two adjacent pads 102 can be better isolated by the outer wall of the insulating groove 103, and the risk of short circuit caused by left-right conduction of the conductive particles 101 on two adjacent pads 102 is further reduced.
The present application also provides a display panel, which includes: a color film substrate; the array substrate is arranged opposite to the color film substrate; and the liquid crystal layer is clamped between the color film substrate and the array substrate. The array substrate is any one of the array substrates 10.
The present application further provides a method for manufacturing an array substrate, which is used for manufacturing the array substrate 10. Referring to fig. 4, fig. 4 is a schematic flow chart illustrating a method for manufacturing an array substrate according to a first embodiment of the present disclosure. The preparation method of the array substrate of the embodiment includes the following steps:
step S41: providing a substrate, and determining a display area and a bonding area of the substrate. The array substrate comprises a display area and a bonding area, the display area is used for setting pixels, the bonding area is used for wiring, and the bonding area further comprises the bonding area.
Step S42: and manufacturing a patterned first metal layer on the substrate, wherein the first metal layer in the bonding area comprises a pad with a bulge. The first metal layer in the bonding region may be a gate metal layer, and the first metal layer in the bonding region may be a pad, that is, the pad in the bonding region and the gate metal layer in the display region may be formed at the same time, and specifically, a metal film layer (Cu, Mo, Al, Ti, etc.) may be formed on the substrate by PVD (Physical Vapor Deposition), and then a patterned first metal layer may be formed by photolithography, etching, or the like, where the first metal layer in the display region is a normal pattern, the first metal layer in the bonding region is a pad, and the pad has a protrusion.
Specifically, the boss includes at least one metal post; in one embodiment, the metal posts are vertical bar-shaped structures, and in another embodiment, the metal posts are spike-shaped structures, and the tips of the spike-shaped structures face the conductive particles.
Step S43: and manufacturing a first insulating layer on the first metal layer. Referring to fig. 5, fig. 5 is a schematic cross-sectional structure of the first metal layer 104 after step S43 in fig. 4, after the first metal layer 104 is formed, a first insulating layer 105 may be formed by CVD (Chemical Vapor Deposition), coating, or the like, where the first insulating layer 105 is an inorganic (SiO2, SiNx) insulating layer to cover the first metal layer 104.
Step S44: and etching the first insulating layer of the bonding area to expose the protruding part outside the first insulating layer. After the first metal layer of the bonding area is covered by the first insulating layer, the first insulating layer of the bonding area may be etched through processes of photolithography, etching, and the like, so that each pad of the bonding area is exposed outside the first insulating layer.
In other embodiments, the first insulating layer may be covered on only the first metal layer of the display region in step S43, and the first insulating layer is not formed in the bonding region, in which case step S44 may be skipped directly.
Step S45: and manufacturing elements of the display area. After the first insulating layer is manufactured in the display area, elements such as an active layer, a source electrode, a drain electrode and the like can be further manufactured on the first insulating layer; in addition, after the elements in the display region are manufactured, an organic insulating layer may be formed in the display region by CVD, coating, or the like. In other embodiments, the order of step S45 and step S44 may be reversed, or performed simultaneously. In another embodiment, the pad of the bonding region may be formed simultaneously with the source and drain metal layer (S/D).
Step S46: and adding conductive particles into the bonding area, wherein part of the conductive particles are arranged on the convex part. Specifically, conductive adhesive is coated on the bonding area of the bonding area, conductive particles are contained in the conductive adhesive, therefore, part of the conductive particles are coated on the protruding portion of the bonding pad, and the outer layer of the conductive particles is coated with a layer of insulating material, so that normal conduction can be achieved only in the vertical direction after the conductive particles are crushed.
In such a way, the bonding pad is arranged on the bonding area and provided with the protruding portion, and partial conductive particles are arranged on the protruding portion, so that the contact area between the bonding pad and the conductive particles can be reduced, the pressure intensity is increased, the bonding pressure required when the insulating layer covering the conductive particles is crushed can be reduced in the manufacturing process of the array substrate, the damage of the edge structure of the array substrate is avoided, and the product yield is improved.
In a preferred embodiment, the number of pads is at least two; the step S44 may specifically include: and etching the first insulating layer of the bonding area, and processing the first insulating layer of the bonding area into a groove shape to form an insulating groove between two adjacent bonding pads. Referring to fig. 6, fig. 6 is a schematic cross-sectional structure of the bonding region B-B after step S44 in fig. 4 is completed, and it can be understood that, by performing etching processing on the first insulating layer 105 of the bonding region B-B through photolithography, etching, and other processes, in addition to exposing each pad 102 of the bonding region B-B to the first insulating layer 105, the first insulating layer 105 between two adjacent pads 102 may be etched into a groove shape to form an insulating groove 103, so, referring to fig. 7 and 8, fig. 7 is a schematic top view structure of the bonding region B-B after step S46 in fig. 4 is completed, fig. 8 is a schematic cross-sectional structure of PP in fig. 7, and when the conductive particles 101 are added in step S46, a part of the conductive particles 101 are disposed in the insulating groove 103, and the conductive particles 101 in the insulating groove 103 are separated from the conductive particles 101 outside the insulating groove 103 by the insulating groove 103.
In an embodiment, the height of the pad is less than that of the insulating groove, and it can be understood that the insulating groove is set to be higher than the pad, so that the conductive particles on two adjacent pads can be better isolated by the outer wall of the insulating groove, and the risk of short circuit caused by left-right conduction of the conductive particles on two adjacent pads is further reduced.
According to the scheme, the insulating groove is formed between the two adjacent bonding pads, and the insulating groove can separate the conductive particles on the two adjacent bonding pads, so that the problem of short circuit caused by left-right conduction between the conductive particles crushed by bonding on the two adjacent bonding pads can be avoided, and the product yield is improved; in addition, because the insulating groove is arranged between the two adjacent bonding pads, part of the conductive particles are arranged in the insulating groove, and the conductive particles in the insulating groove and the conductive particles outside the insulating groove are separated by the insulating groove, the probability that the conductive particles in the insulating groove are crushed during bonding is low, the probability that the conductive particles on the two adjacent bonding pads are conducted left and right to cause short circuit can be further reduced, and the product yield is further improved.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. The array substrate comprises a substrate, wherein the substrate comprises a display area and a bonding area, pixels are arranged on the display area, the array substrate is characterized by further comprising conductive particles, bonding pads are arranged on the bonding area, the bonding pads are provided with protrusions, and the conductive particles are arranged on the protrusions.
2. The array substrate of claim 1, wherein the protrusion comprises at least one metal post.
3. The array substrate of claim 2, wherein the metal pillars are spike-shaped structures, and the tips of the metal pillars face the conductive particles.
4. The array substrate of claim 1, wherein the number of the pads is at least two; an insulating groove is formed between every two adjacent bonding pads, part of the conductive particles are arranged in the insulating groove, and the conductive particles in the insulating groove and the conductive particles outside the insulating groove are separated by the insulating groove.
5. The array substrate of claim 4, wherein the height of the pad is less than the height of the insulating trench.
6. A display panel, comprising:
a color film substrate;
the array substrate is arranged opposite to the color film substrate;
the liquid crystal layer is clamped between the color film substrate and the array substrate;
wherein the array substrate is the array substrate of any one of claims 1 to 5.
7. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate, and determining a display area and a bonding area of the substrate;
manufacturing a patterned first metal layer on the substrate, wherein the first metal layer in the bonding area comprises a pad with a bulge part;
manufacturing a first insulating layer on the first metal layer;
etching the first insulating layer of the bonding area to expose the protruding part outside the first insulating layer;
manufacturing elements of the display area;
and adding conductive particles into the bonding area, wherein part of the conductive particles are arranged on the convex part.
8. The method of claim 7, wherein the protrusion comprises at least one metal pillar;
the metal column is in a vertical bar structure, or the metal column is in a sharp thorn-shaped structure, and the tip of the metal column faces the conductive particles.
9. The method for manufacturing an array substrate according to claim 7, wherein the number of the bonding pads is at least two;
the etching the first insulating layer of the bonding region to expose the protruding portion outside the first insulating layer includes:
and etching the first insulating layer of the bonding area, and processing the first insulating layer of the bonding area into a groove shape to form an insulating groove between two adjacent bonding pads.
10. The method of manufacturing an array substrate of claim 9,
the height of the bonding pad is smaller than that of the insulation groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210389700.9A CN114859608A (en) | 2022-04-13 | 2022-04-13 | Array substrate, preparation method thereof and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210389700.9A CN114859608A (en) | 2022-04-13 | 2022-04-13 | Array substrate, preparation method thereof and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114859608A true CN114859608A (en) | 2022-08-05 |
Family
ID=82632528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210389700.9A Pending CN114859608A (en) | 2022-04-13 | 2022-04-13 | Array substrate, preparation method thereof and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114859608A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008083365A (en) * | 2006-09-27 | 2008-04-10 | Citizen Miyota Co Ltd | Liquid crystal display device |
| CN206210798U (en) * | 2016-10-31 | 2017-05-31 | 昆山国显光电有限公司 | A kind of FPC, TFT substrate and package assembling |
| CN208273349U (en) * | 2018-05-31 | 2018-12-21 | 云谷（固安）科技有限公司 | Flexible circuit board and its bonding structure and flexible display apparatus |
| CN109216582A (en) * | 2018-08-27 | 2019-01-15 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof and display device |
| CN110943110A (en) * | 2019-11-25 | 2020-03-31 | 武汉华星光电半导体显示技术有限公司 | Display device |
| CN211980057U (en) * | 2020-04-02 | 2020-11-20 | 深圳柔宇显示技术有限公司 | Binding structure and display panel |
-
2022
- 2022-04-13 CN CN202210389700.9A patent/CN114859608A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008083365A (en) * | 2006-09-27 | 2008-04-10 | Citizen Miyota Co Ltd | Liquid crystal display device |
| CN206210798U (en) * | 2016-10-31 | 2017-05-31 | 昆山国显光电有限公司 | A kind of FPC, TFT substrate and package assembling |
| CN208273349U (en) * | 2018-05-31 | 2018-12-21 | 云谷（固安）科技有限公司 | Flexible circuit board and its bonding structure and flexible display apparatus |
| CN109216582A (en) * | 2018-08-27 | 2019-01-15 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof and display device |
| CN110943110A (en) * | 2019-11-25 | 2020-03-31 | 武汉华星光电半导体显示技术有限公司 | Display device |
| CN211980057U (en) * | 2020-04-02 | 2020-11-20 | 深圳柔宇显示技术有限公司 | Binding structure and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101398094B1 (en) | Liquid crystal display and array substrate | |
| JP4422648B2 (en) | Liquid crystal display device and manufacturing method thereof | |
| CN101566769B (en) | Liquid crystal display and manufacture method therefor | |
| US7312112B2 (en) | Transistor array substrate fabrication for an LCD | |
| KR100500779B1 (en) | Thin film transistor array substrate and manufacturing method of the same | |
| JP2009133954A (en) | Liquid crystal display device and method for manufacturing liquid crystal display device | |
| KR20070072179A (en) | Method for fabricating liquid crystal display device | |
| US10598995B2 (en) | Array substrate, fabrication method, and corresponding display panel and electronic device | |
| EP2784575B1 (en) | Manufacturing method for electronic paper active substrate | |
| US20130114017A1 (en) | Array substrate and method for manufacturing the same, and display device | |
| US6847413B2 (en) | Liquid crystal display device and method for manufacturing the same | |
| CN107797352A (en) | Array base palte, display panel, the preparation method of display device and array base palte | |
| TWI253539B (en) | Liquid crystal display | |
| CN103293803B (en) | Array base palte and manufacture method thereof for FFS mode liquid crystal display | |
| CN114859608A (en) | Array substrate, preparation method thereof and display panel | |
| US20070004069A1 (en) | Liquid crystal display device and fabricating method thereof | |
| KR100527086B1 (en) | Method for manufacturing liquid crystal display device | |
| KR101023715B1 (en) | Method for fabricating of Liquid Crystal Display Device | |
| KR100710158B1 (en) | Method for fabricating of liquid crystal display device | |
| JPH09244547A (en) | Production of display device | |
| KR100336897B1 (en) | Manufacturing Method of Thin Film Transistor Liquid Crystal Display Device | |
| JP2000187241A (en) | Liquid crystal display device and its manufacture | |
| KR100698043B1 (en) | Method for Forming Liquid Crystal Display Device | |
| KR20030058327A (en) | array panel of liquid crystal display and manufacturing method thereof | |
| KR20050054280A (en) | Liquid crystal display device and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |