CN114843262A - Electrostatic surge protection circuit for low-power-consumption power management chip - Google Patents
Electrostatic surge protection circuit for low-power-consumption power management chip Download PDFInfo
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- 238000002347 injection Methods 0.000 claims abstract description 124
- 239000007924 injection Substances 0.000 claims abstract description 124
- 238000002513 implantation Methods 0.000 claims abstract description 59
- 230000003071 parasitic effect Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 claims description 57
- 229910052751 metal Inorganic materials 0.000 claims description 57
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- 239000004065 semiconductor Substances 0.000 claims description 2
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- 238000013461 design Methods 0.000 abstract description 6
- 239000007943 implant Substances 0.000 description 28
- 238000010586 diagram Methods 0.000 description 11
- 102100037069 Doublecortin domain-containing protein 1 Human genes 0.000 description 7
- 101000954712 Homo sapiens Doublecortin domain-containing protein 1 Proteins 0.000 description 7
- 238000004590 computer program Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 102100037070 Doublecortin domain-containing protein 2 Human genes 0.000 description 4
- 101000954709 Homo sapiens Doublecortin domain-containing protein 2 Proteins 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
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- 230000002457 bidirectional effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/005—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection avoiding undesired transient conditions
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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Abstract
The invention relates to an electrostatic surge protection circuit for a low-power-consumption power management chip, which comprises a P substrate, a first deep N well and a second deep N well which are sequentially stacked, wherein the first deep N well and the second deep N well are arranged at intervals; a first P well and a second P well are sequentially arranged on the first deep N well at intervals; a third P well is arranged on the second deep N well; a plurality of injection regions are arranged on the first P well, the second P well and the third P well, a plurality of injection regions are arranged between the first P well and the second P well, and a plurality of injection regions are also arranged on two sides of the third P well; the implantation region includes an N + implantation region and a P + implantation region. The protection circuit has the advantages that the occupied area is small, parasitic effects are few, the starting voltage of the protection circuit can be adjusted by arranging the P well and arranging the injection region in the P well, the electrostatic surge protection requirements of different power domains of the power management chip are met, and meanwhile, the protection circuit can form a multi-interdigital interconnection layout by utilizing a structural stacking design method.
Description
Technical Field
The invention relates to the field of electrostatic discharge protection and surge resistance of integrated circuits, in particular to an electrostatic surge protection circuit for a low-power-consumption power management chip.
Background
In recent years, with the vigorous development of the internet of things industry, the consumer electronics market has shown great demand for wearable devices based on battery power supply, such as smart watches and bluetooth headsets. In order to extend the service life of a product, a power management Integrated Circuit (IC) that performs functions of converting, distributing, detecting, and the like of electric energy in an electronic product must have characteristics such as high performance, low power consumption, and high integration. And because the power management IC is easy to generate the risk of gate oxide breakdown or metal wire fusing under the impact of large-intensity static electricity or surge current in a short time, the function of the power management chip is invalid, and the wide application of the power management chip is seriously influenced.
With the continuous progress of integrated circuit process nodes, a semiconductor device gate oxide layer becomes thinner continuously, the chip integration level becomes higher and higher, a common power management IC in the market at present is more fragile when being impacted by electrostatic surge, and the proportion of power management chip failure caused by electrostatic surge is increased increasingly. Especially, the power management IC suitable for intelligent wearable equipment has the working characteristics of ultralow working voltage, ultralow power consumption and overlong standby time, so that the difficulty of electrostatic and surge protection design is further increased.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an electrostatic surge protection circuit for a low-power-consumption power management chip, which is small in occupied area and small in parasitic effect, can adjust the starting voltage of the protection circuit by arranging a P well and arranging an injection region in the P well, and realizes the electrostatic surge protection requirements of different power domains of the power management chip, and meanwhile, by utilizing a structural stacking design method, the protection circuit can form a multi-interdigital interconnection layout.
In order to solve the technical problem, the invention provides an electrostatic surge protection circuit for a low-power-consumption power management chip, which comprises a P substrate, a first deep N well and a second deep N well which are sequentially stacked, wherein the first deep N well and the second deep N well are arranged at intervals; a first P well and a second P well are sequentially arranged on the first deep N well at intervals; a third P well is arranged on the second deep N well; a plurality of injection regions are arranged on the first P well, the second P well and the third P well, a plurality of injection regions are arranged between the first P well and the second P well, and a plurality of injection regions are also arranged on two sides of the third P well; the implantation region includes an N + implantation region and a P + implantation region.
Preferably, the first P-well, the second P-well and the third P-well cooperate to form a symmetrical structure.
Preferably, the first P-well, the second P-well and the third P-well are all polygonal structures, so as to reduce parasitic effects at edges of the well region, enhance electrical symmetry characteristics under the action of forward and reverse electrical stress, and enhance electrostatic surge current discharge capability of the protection circuit.
Preferably, a first N + injection region and a first P + injection region are sequentially arranged on the first P well at intervals from left to right; a fourth P + injection region and a fourth N + injection region are sequentially arranged on the second P well from left to right at intervals; a second N + injection region, a second P + injection region, a third P + injection region and a third N + injection region are sequentially arranged between the first P well and the second P well; a seventh P + injection region, a seventh N + injection region, a sixth N + injection region and a sixth P + injection region are sequentially arranged on the third P well at intervals from left to right; an eighth P + injection region and an eighth N + injection region are sequentially arranged on the left side of the third P well from left to right at intervals; and a fifth N + injection region and a fifth P + injection region are sequentially arranged on the right side of the third P well from left to right at intervals.
The first N + injection region, the second N + injection region, the third N + injection region, the fourth N + injection region, the fifth N + injection region, the sixth N + injection region, the seventh N + injection region, the eighth N + injection region, the first P + injection region, the second P + injection region, the third P + injection region, the fourth P + injection region, the fifth P + injection region, the sixth P + injection region, the seventh P + injection region and the eighth P + injection region are matched to form a symmetrical layout.
Preferably, the metal composition further comprises first to eighth metals; the eighth P + injection region is connected with the first N + injection region through a first metal; the eighth N + injection region is connected with the first P + injection region through a second metal; the seventh P + injection region is connected with the second N + injection region through a third metal; the seventh N + injection region and the second P + injection region are connected through a fourth metal; the sixth N + injection region and the third P + injection region are connected through a fifth metal, and the sixth P + injection region and the third N + injection region are connected through a sixth metal; the fifth N + injection region and the fourth P + injection region are connected through a seventh metal, and the fifth P + injection region and the fourth N + injection region are connected through an eighth metal.
Preferably, a first electrode is led out of the first metal, and the first electrode is used as a first electric stress end; the fourth metal is connected with the fifth metal, a second electrode is led out from the connection position of the fourth metal and the fifth metal, and the second electrode is used as a second electrical stress end; and a third electrode is led out from the eighth metal and is used as a third electrical stress end.
The protection circuit has the advantages that forward or reverse electrical stress is applied to the electrical stress end of the protection circuit, and completely same current leakage paths exist in the circuit, so that bidirectional electrostatic and surge protection can be realized, the area of a device can be reduced, and the robustness of unit area can be improved.
Preferably, the first electrical stress end is connected with a first I/O port of the power management chip; the second electrical stress is connected with a VSS port of the power management chip; the third electrical stress end is connected with a second I/O port of the power management chip. And electrostatic and surge protection between the first I/O port and the VSS port and between the second I/O port and the VSS port in the protection circuit is formed, and the protection circuit has a plurality of diode leakage current paths under the action of forward and reverse electrostatic surge stress.
By applying a stacked structure design method, the protection circuit can form a multi-interdigital interconnection layout to form a multi-channel electrostatic surge protection scheme for a low-power-consumption power management chip, and electrostatic surge protection of multiple ports between multiple I/O ports and VSS in the power management chip is realized.
Preferably, different direction electrical stress is applied to the first I/O port or the second I/O port of the power management chip.
Preferably, the number of the injection regions in the first P-well, the second P-well and the third P-well can be adjusted, and the starting voltage of the protection circuit can be adjusted by increasing the number of the P-wells and the embedded N + and P + injection regions therein, so as to meet the electrostatic surge protection requirements of different power domains of the power management IC.
The second deep N well can be removed according to the actual requirement of a protection circuit in the power management chip, so that four diode conduction paths are formed between the first electrical stress end and the third electrical stress end, and the adjustability of the trigger voltage is realized on the basis of small layout level variation.
Preferably, the wearable device comprises the electrostatic surge protection circuit facing the low-power-consumption power management chip.
Compared with the prior art, the technical scheme of the invention has the following advantages:
1. the invention has small occupied area, and the protection circuit can form a multi-interdigital interconnection layout by utilizing a structure stacking design method.
2. The first P well, the second P well and the third P well are all provided with a plurality of injection regions, a plurality of injection regions are arranged between the first P well and the second P well, and a plurality of injection regions are also arranged on two sides of the third P well; by increasing the embedding quantity of the P wells and the N + and P + injection regions inside the P wells, the starting voltage of the protection circuit can be adjusted, and the electrostatic surge protection requirements of different power domains of the power management IC are met.
3. According to the invention, the first P trap, the second P trap and the third P trap are designed into a polygonal layout, so that the parasitic effect on the edge of the well region can be reduced, and the electrostatic surge current discharge capacity of the protection circuit is enhanced.
Drawings
In order that the manner in which the present invention is more fully understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, wherein:
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic view of a metal interconnect according to the present invention;
FIG. 3 is a schematic diagram of an application circuit of the present invention;
fig. 4 is an equivalent circuit schematic of the present invention.
The specification reference numbers indicate: 101-P substrate, 102-first deep N well, 103-second deep N well, 104-first P well, 105-second P well, 106-third P well, 107-first N + injection region, 109-second N + injection region, 112-third N + injection region, 114-fourth N + injection region, 116-fifth N + injection region, 118-sixth N + injection region, 119-seventh N + injection region, 121-eighth N + injection region, 108-first P + injection region, 110-second P + injection region, 111-third P + injection region, 113-fourth P + injection region, 115-fifth P + injection region, 117-sixth P + injection region, 120-seventh P + injection region, 122-eighth P + injection region;
201-first metal, 202-second metal, 203-third metal, 204-fourth metal, 205-fifth metal, 206-sixth metal, 207-seventh metal, 208-eighth metal.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
The invention discloses a low-power consumption power management chip oriented electrostatic surge protection circuit, which is shown in figure 1 and comprises the following components:
The P-substrate 101, the first deep N-well 102 and the second deep N-well 103 are stacked in sequence from bottom to top, and a certain distance is provided between the first deep N-well 102 and the second deep N-well 103.
Preparing the first P well 104 and the second P well 105 in the surface region of the first deep N well 102 from left to right in sequence; and a certain distance is arranged between the first P well 104 and the second P well 105. A third P well 106 is arranged on the second deep N well 103;
the first P well 104, the second P well 105 and the third P well 106 are all provided with a plurality of injection regions, a plurality of injection regions are arranged between the first P well 104 and the second P well 105, and a plurality of injection regions are also arranged on two sides of the third P well 106, wherein the injection regions comprise an N + injection region and a P + injection region, so that the parasitic capacitance of the protection circuit can be reduced, the surface current conduction uniformity is enhanced, and the static and surge protection capability is improved.
Specifically, a first N + implantation region 107 and a first P + implantation region 108 are sequentially formed in the surface region of the first P well 104 from left to right, and a certain distance is provided between the first N + implantation region 107 and the first P + implantation region 108.
The fourth P + implantation region 113 and the fourth N + implantation region 114 are sequentially formed in the surface region of the second P well 105 from left to right, and a certain distance is provided between the fourth P + implantation region 113 and the fourth N + implantation region 114.
The second N + implantation region 109, the second P + implantation region 110, the third P + implantation region 111, and the third N + implantation region 112 are sequentially formed from left to right in the surface region between the first P well 104 and the second P well 105105.
The seventh P + implantation region 120, the seventh N + implantation region 119, the sixth N + implantation region 118, and the sixth P + implantation region 117 are sequentially formed in the surface region of the third P well 106 from left to right. A certain distance is provided between the seventh P + implantation region 120 and the seventh N + implantation region 119, between the seventh N + implantation region 119 and the sixth N + implantation region 118, and between the sixth N + implantation region 118 and the sixth P + implantation region 117.
In the left surface region of the third P well 106, the eighth P + implantation region 122 and the eighth N + implantation region 121 are sequentially formed from left to right, and a certain distance is provided between the eighth P + implantation region 122 and the eighth N + implantation region 121.
In the right surface region of the third P well 106, a fifth N + implantation region 116 and a fifth P + implantation region 115 are sequentially formed from left to right, and a certain distance is provided between the fifth N + implantation region 116 and the fifth P + implantation region 115.
Preferably, the first P-well 104, the second P-well 105 and the third P-well 106 cooperate to form a symmetrical structure; the first N + implant region 107, the second N + implant region 109, the third N + implant region 112, the fourth N + implant region 114, the fifth N + implant region 116, the sixth N + implant region 118, the seventh N + implant region 119, the eighth N + implant region 121, the first P + implant region 108, the second P + implant region 110, the third P + implant region 111, the fourth P + implant region 113, the fifth P + implant region 115, the sixth P + implant region 117, the seventh P + implant region 120, and the eighth P + implant region 122 cooperate to form a symmetrical layout.
Preferably, the first P well 104, the second P well 105 and the third P well 106 are designed to be polygonal layouts, so that the parasitic effect at the edge of the well region can be reduced, and the electrostatic surge current discharge capability of the protection circuit can be enhanced.
The invention can increase the embedding quantity of each P well and the N + and P + injection regions inside the P wells so as to adjust the starting voltage of the protection circuit and realize the electrostatic surge protection requirements of different power domains of the power management chip.
Referring to fig. 2, a metal wiring diagram of an example of the present invention includes first to eighth metals.
Specifically, the eighth P + implantation region 122 and the first N + implantation region 107 are connected by a first metal 201; the eighth N + implantation region 121 and the first P + implantation region 108 are connected by a second metal 202; the seventh P + implant region 120 and the second N + implant region 109 are connected by a third metal 203; the seventh N + implant region 119 and the second P + implant region 110 are connected by a fourth metal 204; the sixth N + implant region 118 and the third P + implant region 111 are connected by a fifth metal 205, and the sixth P + implant region 117 and the third N + implant region 112 are connected by a sixth metal 206; the fifth N + implant region 116 and the fourth P + implant region 113 are connected by a seventh metal 207, and the fifth P + implant region 115 and the fourth N + implant region 114 are connected by an eighth metal 208.
A first electrode is led out of the first metal 201 and serves as a first electrical stress terminal. The fourth metal 204 is connected with the fifth metal 205, a second electrode is led out from the connection position of the fourth metal 204 and the fifth metal 205, and the second electrode is used as a second electrical stress end. A third electrode is led out of the eighth metal 208 and serves as a third electrical stress terminal.
By using the structure stacking design method, the protection circuit can form a multi-interdigital interconnection layout.
The applied circuit diagram of the present invention is shown in fig. 3, and includes: the buck converter module DCDC1, the buck converter module DCDCC2, the input power port IN _ DCDC1 of the buck converter DCDC1, the input power port IN _ DCDC2 of the buck converter DCDC2, the first I/O port of the buck converter DCDC1, the second I/O port of the buck converter DCDC2, the inductors L1 and L2, the capacitors C1, C2, C3 and C4, the feedback voltage port FB1 of the buck converter module DCDC1 and the feedback voltage port FB2 of the buck converter module DCDC 2. By connecting the first electrical stress terminal to the first I/O port of buck converter DCDC1, the second electrical stress terminal to the VSS port of buck converter DCDC1, buck converter DCDC2, and the third electrical stress terminal to the second I/O port of buck converter DCDC 2.
Namely: the first electrical stress end is connected with a first I/O port of the power management chip, and the second electrical stress end is connected with a VSS port of the power management chip; the third electrical stress end is connected with the second I/O port of the power management chip so as to realize the electrostatic surge protection circuit facing the power management chip, and realize electrostatic and surge protection between the first I/O port and the VSS port and between the second I/O port and the VSS port in the protection circuit, and the protection circuit has a plurality of diode discharge current paths under the action of forward and reverse electrostatic surge stress.
The forward or reverse electrical stress is applied to each electrical stress end, and the same current leakage paths exist in the circuit, so that bidirectional electrostatic and surge protection can be realized, the area of the device is reduced, and the robustness of the unit area is improved.
Preferably, in practical application, the second deep N-well 103 may be removed according to actual requirements of a protection circuit inside the power management chip, four diode conduction paths are formed between the first electrical stress end and the third electrical stress end, and adjustability of the trigger voltage is achieved on the basis of small layout level variation.
The obtained current leakage paths are completely the same for applying electrical stress in different directions on the first I/O port or the second I/O port.
As shown in fig. 4, when a forward electrical stress acts on the first I/O port, the VSS port is grounded, and the second I/O port is floated, the eighth P + injection region 122, the second deep N-well 103 and the third P-well 106 form a PNP transistor T1, the second deep N-well 103, the third P-well 106 and the seventh N + injection region 119 form an NPN transistor T2, and the PNP transistor T1 and the NPN transistor T2 form a positive feedback network of an SCR structure, which can effectively improve the robustness of the protection circuit. The low-voltage trigger path of the protection circuit can be realized by a multi-diode trigger path formed by a diode formed by an emitter region and a collector region of the PNP transistor T1, a diode D1 formed by the first P well 104 and the first deep N well 102, and a diode D2 formed by the third P well 106 and the seventh N + injection region 119. And applying electrical stress in different directions to the first I/O port, the VSS port or the second I/O port, wherein the obtained current leakage paths are completely the same.
The invention further provides wearable equipment which comprises the electrostatic surge protection circuit facing the low-power-consumption power management chip, so that the reliability of the wearable equipment is improved, and the service life of the wearable equipment is prolonged.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. The utility model provides a towards low-power consumption power management chip's electrostatic surge protection circuit which characterized in that includes:
the semiconductor device comprises a P substrate, a first deep N well and a second deep N well which are sequentially stacked, wherein the first deep N well and the second deep N well are arranged at intervals;
a first P well and a second P well are sequentially arranged on the first deep N well at intervals; a third P well is arranged on the second deep N well;
a plurality of injection regions are arranged on the first P well, the second P well and the third P well, a plurality of injection regions are arranged between the first P well and the second P well, and a plurality of injection regions are also arranged on two sides of the third P well; the implantation region includes an N + implantation region and a P + implantation region.
2. The low-power-consumption power management chip-oriented electrostatic surge protection circuit according to claim 1, wherein the first P-well, the second P-well and the third P-well cooperate to form a symmetrical structure.
3. The electrostatic surge protection circuit for the low-power-consumption power management chip according to claim 1, wherein the first P-well, the second P-well and the third P-well are all polygonal structures so as to reduce parasitic effects at edges of well regions and enhance electrostatic surge current discharge capability of the protection circuit.
4. The electrostatic surge protection circuit facing the low-power-consumption power management chip according to claim 1, wherein a first N + injection region and a first P + injection region are sequentially arranged on the first P well from left to right at intervals; a fourth P + injection region and a fourth N + injection region are sequentially arranged on the second P well from left to right at intervals; a second N + injection region, a second P + injection region, a third P + injection region and a third N + injection region are sequentially arranged between the first P well and the second P well;
a seventh P + injection region, a seventh N + injection region, a sixth N + injection region and a sixth P + injection region are sequentially arranged on the third P well from left to right at intervals;
an eighth P + injection region and an eighth N + injection region are sequentially arranged on the left side of the third P well from left to right at intervals; and a fifth N + injection region and a fifth P + injection region are sequentially arranged on the right side of the third P well at intervals from left to right.
5. The low-power-consumption power management chip-oriented electrostatic surge protection circuit according to claim 4, further comprising first to eighth metals;
the eighth P + injection region is connected with the first N + injection region through a first metal; the eighth N + injection region is connected with the first P + injection region through a second metal; the seventh P + injection region is connected with the second N + injection region through a third metal; the seventh N + injection region and the second P + injection region are connected through a fourth metal; the sixth N + injection region and the third P + injection region are connected through a fifth metal, and the sixth P + injection region and the third N + injection region are connected through a sixth metal; the fifth N + injection region and the fourth P + injection region are connected through a seventh metal, and the fifth P + injection region and the fourth N + injection region are connected through an eighth metal.
6. The low-power-consumption power management chip-oriented electrostatic surge protection circuit according to claim 5, wherein a first electrode is led out from the first metal, and the first electrode is used as a first electrical stress end;
the fourth metal is connected with the fifth metal, a second electrode is led out from the connection position of the fourth metal and the fifth metal, and the second electrode is used as a second electrical stress end;
and a third electrode is led out from the eighth metal and is used as a third electrical stress end.
7. The low power consumption power management chip-oriented electrostatic surge protection circuit according to claim 6, wherein the first electrical stress terminal is connected to a first I/O port of the power management chip; the second electrical stress is connected with a VSS port of the power management chip; the third electrical stress end is connected with a second I/O port of the power management chip.
8. The low power consumption power management chip-oriented electrostatic surge protection circuit according to claim 7, wherein different direction electrical stresses are applied to the first I/O port or the second I/O port of the power management chip.
9. The electrostatic surge protection circuit for the low-power-consumption power management chip according to claim 1, wherein the number of injection regions in the first P-well, the second P-well and the third P-well can be adjusted to meet the electrostatic surge protection requirements of different power domains of the power management chip.
10. A wearable device, characterized by comprising the low power consumption power management chip oriented electrostatic surge protection circuit of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210499551.1A CN114843262B (en) | 2022-05-09 | 2022-05-09 | Electrostatic surge protection circuit for low-power-consumption power management chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210499551.1A CN114843262B (en) | 2022-05-09 | 2022-05-09 | Electrostatic surge protection circuit for low-power-consumption power management chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116314182A (en) * | 2023-03-28 | 2023-06-23 | 江南大学 | Bidirectional electrostatic surge protection circuit applied to low-power consumption LDO chip |
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| CN108109997A (en) * | 2017-12-15 | 2018-06-01 | 江南大学 | A kind of method that low pressure ESD protection performance is improved using trap cutting techniques |
| CN109698195A (en) * | 2018-12-28 | 2019-04-30 | 江南大学 | A kind of small hysteresis bidirectional transient voltage suppressor and its application |
| US20200091138A1 (en) * | 2018-05-17 | 2020-03-19 | Jiangnan University | Esd protection device with bidirectional diode string-triggering scr structure |
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| WO2021233083A1 (en) * | 2020-05-18 | 2021-11-25 | 深圳市晶扬电子有限公司 | Low-power-consumption bidirectional scr device for esd protection, and electrostatic protection circuit |
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| CN108109997A (en) * | 2017-12-15 | 2018-06-01 | 江南大学 | A kind of method that low pressure ESD protection performance is improved using trap cutting techniques |
| US20200091138A1 (en) * | 2018-05-17 | 2020-03-19 | Jiangnan University | Esd protection device with bidirectional diode string-triggering scr structure |
| CN109698195A (en) * | 2018-12-28 | 2019-04-30 | 江南大学 | A kind of small hysteresis bidirectional transient voltage suppressor and its application |
| KR102142156B1 (en) * | 2019-07-18 | 2020-08-06 | 단국대학교 산학협력단 | Dual Structure Electrostatic Discharge Protection Device with High Holding Voltage |
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| CN116314182A (en) * | 2023-03-28 | 2023-06-23 | 江南大学 | Bidirectional electrostatic surge protection circuit applied to low-power consumption LDO chip |
| CN116314182B (en) * | 2023-03-28 | 2024-05-31 | 江南大学 | Bidirectional electrostatic surge protection circuit applied to low-power consumption LDO chip |
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| CN114843262B (en) | 2022-11-08 |
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