CN114843243A - Packaging structure - Google Patents
Packaging structure Download PDFInfo
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- CN114843243A CN114843243A CN202210532501.9A CN202210532501A CN114843243A CN 114843243 A CN114843243 A CN 114843243A CN 202210532501 A CN202210532501 A CN 202210532501A CN 114843243 A CN114843243 A CN 114843243A
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- holes
- carrier
- hole
- package structure
- sectional area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
The invention discloses a packaging structure, which comprises a carrier and at least one interconnection structure. The carrier has at least one first through hole and a plurality of second through holes. The first through hole is close to the central area of the carrier, the second through hole is close to the peripheral area of the carrier, and the sectional area of the first through hole is smaller than the total sectional area of the second through hole. The interconnection structure is located on the carrier and covers the first through hole and the second through hole.
Description
Technical Field
The invention relates to a packaging structure.
Background
With the increasing progress of Integrated Circuit (IC) manufacturing technology, the demand for packaging and manufacturing processes is increased, and the technologies currently applied to the field of Chip packaging are various, such as Fan-out Panel level packaging (FOPLP), Chip Scale Packaging (CSP), Direct Chip Attached packaging (DCA), Multi-Chip Module packaging (MCM), and other flip-Chip packaging modules, or a Chip stacking technology for three-dimensionally stacking and integrating chips into a three-dimensional integrated circuit (3 DIC).
However, due to the material characteristics of the insulating board body for die bonding, the insulating board body is easily deformed by Thermal expansion and contraction during the heat treatment (Thermal cycle) of the package manufacturing process, so that the wiring layer therein is displaced. Although the supporting board may be adhered to one side of the insulating board, the insulating board may be warped (warp) and deformed after the supporting board is removed, so that the subsequent solder bumps may not be effectively or precisely bonded to the circuit layer.
Disclosure of Invention
One aspect of the present invention is a package structure.
According to some embodiments of the present invention, a package structure includes a carrier and at least one interconnect structure. The carrier has at least one first through hole and a plurality of second through holes. The first through hole is close to the central area of the carrier, the second through hole is close to the peripheral area of the carrier, and the sectional area of the first through hole is smaller than the total sectional area of the second through hole. The interconnection structure is located on the carrier and covers the first through hole and the second through hole.
In some embodiments, the diameter of the first through hole is the same as the diameter of each second through hole, and the density of the first through holes is less than that of the second through holes.
In some embodiments, the diameter of the first through holes is larger than the diameter of each second through hole, and the number of the first through holes is smaller than the number of the second through holes.
In some embodiments, the diameter of the first through holes is smaller than the diameter of each second through hole, and the number of the first through holes is smaller than the number of the second through holes.
In some embodiments, the carrier has a plurality of first through holes, and the total cross-sectional area of the first through holes is smaller than the total cross-sectional area of the second through holes.
In some embodiments, the diameter of each first through hole is smaller than the diameter of each second through hole, and the number of the first through holes is greater than the number of the second through holes.
In some embodiments, the package structure further includes a plurality of metal fillers. The metal filling material is respectively positioned in the first part of the first through hole and the first part of the second through hole, wherein the metal filling material is not arranged in the second part of the first through hole and the second part of the second through hole.
In some embodiments, the total cross-sectional area of the second portion of the first through-hole is smaller than the total cross-sectional area of the second portion of the second through-hole.
In some embodiments, the package structure includes two interconnect structures, and the carrier is located between the two interconnect structures. The two interconnect structures each include a dielectric layer and a conductive line disposed in the dielectric layer. The two wires of the two interconnection structures are respectively and electrically connected with two ends of one of the metal filling materials.
In some embodiments, the metal filler has a different coefficient of thermal expansion than the carrier.
In some embodiments, the coefficient of thermal expansion of the metal filler is greater than the coefficient of thermal expansion of the carrier.
In some embodiments, the package structure further includes a plurality of metal fillers. The metal filling material is respectively positioned in the first parts of the first through hole and the second through hole, wherein the second part of the second through hole is free of the metal filling material.
In some embodiments, the package structure further includes a plurality of metal fillers. The metal filling material is respectively positioned in the first through hole and the second through hole, wherein the diameter of the metal filling material in the first through hole is smaller than that of the metal filling material in the second through hole.
In some embodiments, the interconnect structure includes a dielectric layer and a conductive line in the dielectric layer. One of the second through holes is overlapped with the conductive line in the vertical direction.
In some embodiments, the first through hole and the second through hole are parallel to each other.
In the above embodiments of the present invention, since the carrier has at least one first through hole near the central region of the carrier and a plurality of second through holes near the peripheral region of the carrier, and the cross-sectional area of the first through hole is smaller than the total cross-sectional area of the second through holes, when the carrier and different material layers (e.g. interconnect structures) thereon have different thermal expansion coefficients and warp (warp) occurs, the warp amount of the carrier can be changed by the design of the first through hole and the second through hole, so that the peripheral region of the carrier has more space shrinkage and the warp amount of the carrier is reduced. Therefore, the displacement of the wires in the interconnection structure caused by heat treatment during formation, Bonding (Bonding) and Molding (Molding) of the interconnection structure can be avoided, and the solder bumps can be accurately bonded on the wires of the interconnection structure.
Drawings
Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 to 3 are cross-sectional views illustrating steps of forming a package structure according to an embodiment of the invention;
fig. 4 to 10 are cross-sectional views of package structures according to various embodiments of the present invention;
FIGS. 11-13 are cross-sectional views of steps of forming a package structure according to another embodiment of the present invention;
fig. 14 to 16 are cross-sectional views of package structures according to various embodiments of the present invention.
Description of the symbols
100,100 a-100 k packaging structure
110 carrier
112 top surface
114 bottom surface
120,120a interconnect structure
122 dielectric layer
124, conducting wire
130 metal filler
C central region
d1, d2, d3, d4 diameter
O1 first Via
O11 first Via
O12 first Via
O2 second through hole
O21 second through hole
O22 second through hole
P is the peripheral zone
Detailed Description
The following disclosure of embodiments provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are merely examples and are not intended to be limiting. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Spatially relative terms, such as "below … …", "below … …", "below", "above … …", "upper", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.
Fig. 1-3 illustrate cross-sectional views of various steps of forming a package structure 100 according to an embodiment of the invention. Referring to fig. 1 and 2, the carrier 110 has a top surface 112 and a bottom surface 114 opposite to each other. The material of the carrier 110 may be glass, but is not limited thereto. The carrier 110 has a central region C and a peripheral region P surrounding the central region C. The carrier 110 may be drilled to form at least one first via O1 and a plurality of second vias O2, such that the physical structure of the carrier 110 is changed to improve warpage. The first via O1 and the second via O2 penetrate the top surface 112 and the bottom surface 114 of the carrier 110, and the first via O1 and the second via O2 may be parallel to each other. In addition, the first through hole O1 is close to the central region C of the carrier 110, the second through hole O2 is close to the peripheral region P of the carrier 110, and the cross-sectional area of the first through hole O1 is smaller than the total cross-sectional area of the second through holes O2. The positions and the numbers of the first through holes O1 and the second through holes O2 may be changed according to different warpage resistance requirements, and fig. 2 is only an example.
Referring to fig. 3, after the first via O1 and the second via O2 are formed, an interconnection structure 120 covering the first via O1 and the second via O2 may be formed on the top surface 112 of the carrier 110, so as to obtain the package structure 100. Interconnect structure 120 may include a dielectric layer 122 and a conductive line 124 disposed in dielectric layer 122. In the present embodiment, the conductive line 124 may be a Redistribution line (RDL), which may be made of copper or other suitable metal for transmitting an electrical signal; the material of the dielectric layer 122 may be Epoxy (Epoxy) or Polyimide (PI), but is not limited thereto. The second via O2 may overlap the second conductive line 124 in the vertical direction, or overlap the dielectric layer 122 in the vertical direction, which is not intended to limit the invention.
Specifically, since the carrier 110 has at least one first through hole O1 near the central area C of the carrier 110 and a plurality of second through holes O2 near the peripheral area P of the carrier 110, and the cross-sectional area of the first through hole O1 is smaller than the total cross-sectional area of the second through holes O2, when the carrier 110 and different material layers (e.g., the interconnect structure 120) thereon have different thermal expansion coefficients and warp (warp), the design of the first through hole O1 and the second through hole O2 can change the warp amount of the carrier 110, so that the peripheral area P of the carrier 110 has more space shrinkage and further reduces the warp amount of the carrier 110. In this way, the wires 124 in the interconnect structure 120 can be prevented from being displaced due to heat treatment during formation, Bonding (Bonding) of the chip, and Molding (Molding) of the chip, so that the solder bumps can be precisely bonded on the wires 124 of the interconnect structure 120.
In the present embodiment, the diameter d1 of the first through hole O1 and the diameter d2 of each second through hole O2 may be the same, that is, the size of the first through hole O1 and the second through hole O2 are the same. Further, the density of the first through holes O1 is less than the density of the second through holes O2. With such a design, the cross-sectional area of the first through-hole O1 may be smaller than the total cross-sectional area of the second through-holes O2.
It is to be understood that the connection, materials and functions of the elements described above will not be repeated and are described in detail. In the following description, other forms of package structures will be described.
Fig. 4 to 10 illustrate cross-sectional views of package structures 100a to 100g according to various embodiments of the present invention. Referring to fig. 4, the embodiment of fig. 3 is different in that the package structure 100a includes an interconnect structure 120a in addition to the interconnect structure 120. Interconnect structures 120,120a are located on top surface 112 and bottom surface 114 of carrier 110, respectively. That is, the carrier 110 is positioned between the two interconnect structures 120,120 a.
Referring to fig. 5, the package structure 100b includes a carrier 110 and an interconnect structure 120, which is different from the embodiment of fig. 3 in that the diameter d1 of the first via O1 of the carrier 110 of the package structure 100b is larger than the diameter d2 of each second via O2, and the number of the first vias O1 is smaller than the number of the second vias O2. In the present embodiment, the number of the first through holes O1 is 1, and the number of the second through holes O2 is 5, but the present invention is not limited thereto. With such a design, the cross-sectional area of the first through hole O1 may be smaller than the total cross-sectional area of the second through hole O2, so that the surrounding area P of the carrier 110 of the package structure 100b has more space to shrink and further reduce the warpage of the carrier 110.
Referring to fig. 6, the embodiment of fig. 5 is different in that the package structure 100c includes an interconnect structure 120a in addition to the interconnect structure 120. Interconnect structures 120,120a are located on top surface 112 and bottom surface 114 of carrier 110, respectively. That is, the carrier 110 of the package structure 100c is located between the two interconnect structures 120,120 a.
Referring to fig. 7, the package structure 100d includes a carrier 110 and an interconnect structure 120. The carrier 110 of the package structure 100d has a plurality of first vias O1, and the total cross-sectional area of the first vias O1 is smaller than the total cross-sectional area of the second vias O2. In addition, the diameter d1 of each first through hole O1 is smaller than the diameter d2 of each second through hole O2, and the number of the first through holes O1 is greater than the number of the second through holes O2. In the present embodiment, the number of the first through holes O1 is 4, and the number of the second through holes O2 is 3, but the present invention is not limited thereto. With such a design, the total cross-sectional area of the first through hole O1 may be smaller than the total cross-sectional area of the second through hole O2, so that the surrounding area P of the carrier 110 of the package structure 100d has more space to shrink and further reduce the warpage of the carrier 110.
Referring to fig. 8, a difference from the embodiment of fig. 7 is that the package structure 100e of fig. 8 includes an interconnect structure 120a in addition to the interconnect structure 120. Interconnect structures 120,120a are located on top surface 112 and bottom surface 114 of carrier 110, respectively. That is, the carrier 110 of the package structure 100e is located between the two interconnect structures 120,120 a. Further, in the present embodiment, the number of the first through holes O1 is 6, the number of the second through holes O2 is 5, and the total sectional area of the first through holes O1 is smaller than the total sectional area of the second through holes O2.
Referring to fig. 9, the package structure 100f includes a carrier 110 and an interconnect structure 120. Interconnect structure 120 is located on top surface 112 of carrier 110. The carrier 110 of the package structure 100f has at least one first via O1 and a plurality of second vias O2, and the total cross-sectional area of the first vias O1 is smaller than the total cross-sectional area of the second vias O2. In addition, the diameter d1 of the first through hole O1 is smaller than the diameter d2 of each second through hole O2, and the number of the first through holes O1 is smaller than the number of the second through holes O2. In the present embodiment, the number of the first through holes O1 is 1, and the number of the second through holes O2 is 3, but the present invention is not limited thereto. With such a design, the cross-sectional area of the first through hole O1 may be smaller than the total cross-sectional area of the second through hole O2, so that the surrounding area P of the carrier 110 of the package structure 100f has more space to shrink and further reduce the warpage of the carrier 110.
Referring to fig. 10, the embodiment of fig. 9 is different in that the package structure 100g includes an interconnect structure 120a in addition to the interconnect structure 120. Interconnect structures 120,120a are located on top surface 112 and bottom surface 114 of carrier 110, respectively. That is, the carrier 110 of the package structure 100g is located between the two interconnect structures 120,120 a. Further, in the present embodiment, the number of the second through holes O2 is 5, and the sectional area of the first through hole O1 is smaller than the total sectional area of the second through holes O2.
Fig. 11 to 13 are cross-sectional views illustrating steps of forming a package structure 100h according to another embodiment of the invention. Referring to fig. 11 and 12, the carrier 110 may be drilled to form a first via O11 and a plurality of second vias O21 and O22. The first via O11 is near the central region C of the carrier 110 and the second vias O21, O22 are near the peripheral region P of the carrier 110. The positions and the numbers of the first through holes O11 and the second through holes O21, O22 may be changed according to different requirements for warp resistance, and fig. 11 is only an example.
In one embodiment, the carrier 110 has a single first through hole O11 and second through holes O21, O22 of different diameters. The diameter d4 of the second through hole O21 is larger than the diameter d3 of the second through hole O22, and the diameter d1 of the first through hole O11 is substantially the same as the diameter d3 of the second through hole O22. In the subsequent manufacturing process, a plurality of metal fillers 130 may be filled in the first via O11 and the second via O21, such that the metal fillers 130 are located in the first via O11 and the second via O21 (i.e., in the first portion of the second via), and no metal filler is located in the second via O22 (i.e., in the second portion of the second via). Such a design allows the cross-sectional area (e.g. 0) of the metal-free filler 130 of the first through hole O11 to be smaller than the total cross-sectional area (e.g. the total cross-sectional area of the second through hole O22) of the metal-free filler 130 of the second through holes O21 and O22, and allows the Coefficient of Thermal Expansion (CTE) of the carrier 110 to be changed to improve warpage.
In the present embodiment, the material of the metal filler 130 may be copper, aluminum or other suitable metals, and the thermal expansion coefficient of the metal filler 130 is different from that of the carrier 110, for example, the thermal expansion coefficient of the metal filler 130 is greater than that of the carrier 110.
In another embodiment, the carrier 110 also has a first via O12 (shown in phantom). The first via O12 has a diameter d1 and is proximate to the central region C of the carrier 110. The metal filler 130 is located in the first via O11 and the second via O21 (i.e., in the first portion of the first via and the first portion of the second via), and the metal filler 130 is absent in the first via O12 and the second via O22 (i.e., in the second portion of the first via and the second portion of the second via). By such a design, the total cross-sectional area of the first through holes O11 and O12 without the metal filler 130 (e.g., the cross-sectional area of the first through hole O12) is smaller than the total cross-sectional area of the second through holes O21 and O22 without the metal filler 130 (e.g., the total cross-sectional area of the second through hole O22), so that the thermal expansion coefficient of the carrier 110 is changed to improve the warpage.
Referring to fig. 13, after the structure of fig. 12 is formed, an interconnection structure 120 covering the first through holes O11, O12, the second through holes O21, O22 and the metal filler 130 may be formed on the top surface 112 of the carrier 110, so as to obtain a package structure 100 h. In the present embodiment, the conductive line 124 of the interconnect structure 120 may be vertically overlapped and electrically connected to the metal filler 130, but the invention is not limited thereto.
Fig. 14 to 16 are cross-sectional views illustrating package structures 100i to 100k according to various embodiments of the present invention. Referring to fig. 14, the embodiment of fig. 13 is different in that the package structure 100i includes an interconnect structure 120a in addition to the interconnect structure 120. Interconnect structures 120,120a are located on top surface 112 and bottom surface 114 of carrier 110, respectively. That is, the carrier 110 of the package structure 100i is located between the two interconnect structures 120,120 a. In the present embodiment, the first via O11 and the right second via O21 are filled with the metal filler 130, and the right second via O22 is filled with the metal filler 130. By such a design, the cross-sectional area of the first through hole O11 of the metal-free filler 130 is smaller than the total cross-sectional area of the second through holes O21 and O22 of the metal-free filler 130, so that the thermal expansion coefficient of the carrier 110 is changed to improve the warpage. In this embodiment, the two conductive wires 124 of the two interconnect structures 120 and 120a can be electrically connected to two ends of the metal filling material 130 respectively to conduct.
Referring to fig. 15, the package structure 100j includes a carrier 110, a plurality of metal fillers 130 and an interconnect structure 120. The carrier 110 has at least a first through hole O1 and a plurality of second through holes O2. The metal filling material 130 is respectively located in the first via O1 and the second via O2, that is, all of the first via O1 and the second via O2 are filled with the metal filling material 130. In this embodiment, the first through hole O1 and the metal filler 130 therein have a diameter d1, the second through hole O2 and the metal filler 130 therein have a diameter d2, and the diameter d1 of the metal filler 130 in the first through hole O1 is smaller than the diameter d2 of the metal filler 130 in the second through hole O2. With such a design, the cross-sectional area of the metal filler 130 in the first through hole O1 can be smaller than the total cross-sectional area of the metal filler 130 in the second through hole O2, thereby reducing the warpage of the carrier 110. The interconnect structure 120 is located on the top surface 112 of the carrier 110, and the conductive line 124 of the interconnect structure 120 may vertically overlap the second via O2.
Referring to fig. 16, the difference between the embodiment of fig. 15 and the package structure 100k further includes an interconnect structure 120a, and the number of the second vias O2 and the metal fillers 130 is larger. Interconnect structures 120,120a are located on top surface 112 and bottom surface 114 of carrier 110, respectively. That is, the carrier 110 of the package structure 100k is located between the two interconnect structures 120,120 a. With such a design, the cross-sectional area of the metal filler 130 in the first through hole O1 can be smaller than the total cross-sectional area of the metal filler 130 in the second through hole O2, thereby reducing the warpage of the carrier 110.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (15)
1. A package structure, comprising:
a carrier having at least one first via and a plurality of second vias, wherein the first via is near a central region of the carrier, the second vias are near a peripheral region of the carrier, and a cross-sectional area of the first via is smaller than a total cross-sectional area of the second vias; and
at least one interconnection structure is positioned on the carrier and covers the first through hole and the second through holes.
2. The package structure of claim 1, wherein the diameter of the first via is the same as the diameter of each of the second vias, and the density of the first vias is less than the density of the second vias.
3. The package structure of claim 1, wherein the diameter of the first through hole is larger than the diameter of each of the second through holes, and the number of the first through holes is smaller than the number of the second through holes.
4. The package structure of claim 1, wherein the diameter of the first through hole is smaller than the diameter of each of the second through holes, and the number of the first through holes is smaller than the number of the second through holes.
5. The package structure of claim 1, wherein the carrier has a plurality of the first through holes, and a total cross-sectional area of the first through holes is smaller than a total cross-sectional area of the second through holes.
6. The package structure of claim 5, wherein the diameter of each of the first through holes is smaller than the diameter of each of the second through holes, and the number of the first through holes is greater than the number of the second through holes.
7. The package structure of claim 5, further comprising:
and a plurality of metal filling materials respectively positioned in the first parts of the first through holes and the second through holes, wherein the metal filling materials are not arranged in the second parts of the first through holes and the second parts of the second through holes.
8. The package structure of claim 7, wherein a total cross-sectional area of the second portion of the first vias is less than a total cross-sectional area of the second portion of the second vias.
9. The package structure of claim 7, comprising two of the interconnection structures, wherein the carrier is located between the two interconnection structures, wherein each of the two interconnection structures comprises a dielectric layer and a conductive line located in the dielectric layer, and the two conductive lines of the two interconnection structures are electrically connected to two ends of one of the metal fillings, respectively.
10. The package structure of claim 7, wherein the metal fillers have a different coefficient of thermal expansion than the carrier.
11. The package structure of claim 7, wherein the coefficient of thermal expansion of the metallic fillers is greater than the coefficient of thermal expansion of the carrier.
12. The package structure of claim 1, further comprising:
and a plurality of metal filling materials respectively positioned in the first through holes and the first parts of the second through holes, wherein the metal filling materials are not arranged in the second parts of the second through holes.
13. The package structure of claim 1, further comprising:
and a plurality of metal fillers respectively positioned in the first through hole and the second through holes, wherein the diameter of the metal filler in the first through hole is smaller than that of the metal fillers in the second through holes.
14. The package structure of claim 1, wherein the interconnect structure comprises a dielectric layer and a conductive line in the dielectric layer, one of the second vias vertically overlapping the conductive line.
15. The package structure of claim 1, wherein the first via and the second vias are parallel to each other.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110141035 | 2021-11-03 | ||
| TW110141035A TWI761297B (en) | 2021-11-03 | 2021-11-03 | Package structure |
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| CN114843243A true CN114843243A (en) | 2022-08-02 |
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| CN202210532501.9A Pending CN114843243A (en) | 2021-11-03 | 2022-05-10 | Packaging structure |
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| JP2012009473A (en) * | 2010-06-22 | 2012-01-12 | Panasonic Corp | Semiconductor device and manufacturing method of the same |
| JP5609617B2 (en) * | 2010-12-17 | 2014-10-22 | 富士通株式会社 | Electronic component, method for manufacturing the electronic component, electronic device, and method for manufacturing the electronic device |
| JP6492768B2 (en) * | 2015-02-27 | 2019-04-03 | 富士通株式会社 | Electronic device and solder mounting method |
| JP2016174101A (en) * | 2015-03-17 | 2016-09-29 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
| US9397048B1 (en) * | 2015-03-23 | 2016-07-19 | Inotera Memories, Inc. | Semiconductor structure and manufacturing method thereof |
| KR20200077250A (en) * | 2018-12-20 | 2020-06-30 | 엘지디스플레이 주식회사 | Display device and appartus for fabricating display device |
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| TWI761297B (en) | 2022-04-11 |
| TW202320274A (en) | 2023-05-16 |
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