CN114843196A - Electrode conductive pillar bonded wafer fabrication method - Google Patents

Abstract

The invention provides a method for manufacturing an electrode conductive column bound wafer, which comprises the following steps: s1, manufacturing the conductive copper foil into a patterned copper foil; s2 wafer binding; s3 filling an insulating protective layer; s4, pasting the front side of the protective film; s5, thinning the wafer; s6 tearing the film; s7 back metallization; s8 dicing the package. The ultra-thin wafer processing is realized through the front design process and the back thinning process of the chip, the power density of the chip can be improved, the thermal resistance is reduced, and the packaging volume is reduced. And through thickening the metal layer and protecting the insulating layer, the wafer strength is improved, and the wafer breakage probability is reduced. The product is suitable for various power device chip Diodes, triodes, MOSFETs, IGBTs, TVSs, SCRs, GTOs, SiC Diodes, SiC MOSFETs, GaN MOSFETs and the like.

Description

Electrode conductive pillar bonded wafer fabrication method

technical field

The invention relates to the field of electronic component manufacturing, in particular to a method for manufacturing an electrode conductive column-bound wafer.

Background technique

Integrated circuit chips are constantly developing in the direction of high density and thinness. In order to meet the requirements, wafers need to be thinned and cut. Wafer thinning technology is the key technology of stacked chip packaging, and the thinning process, as an important process in chip production, has a great impact on the production quality of chips. In the current wafer thinning process, the wafer is generally thinned to a predetermined thickness range, and then the wafer is cut into individual chips. However, with the development of the chip industry, the thickness of the chip is getting thinner and thinner. According to the current thinning process, the wafer is easily broken during the thinning process because it is too thin, which greatly affects the production quality. lead to lower yield.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is that in the current wafer thinning process, the wafer is generally thinned to a predetermined thickness range first, and then the wafer is cut into individual chips. However, with the development of the chip industry, the thickness of the chip is getting thinner and thinner. According to the current thinning process, the wafer is easily broken during the thinning process because it is too thin, which greatly affects the production quality. As a result, the yield is reduced, and the present invention provides a method for manufacturing a wafer with electrode conductive pillars bound to solve the above problem.

The technical solution adopted by the present invention to solve the technical problem is as follows: a method for manufacturing a wafer with electrode conductive column binding type, comprising the following steps: S1, the conductive copper foil is made into a patterned copper foil; S2, the wafer is bound, and the pattern is Brush the solder paste on the copper foil, bind the wafer on the patterned copper foil, and perform high temperature sintering; S3 is filled with an insulating protective layer, and an insulating material is filled between the patterned copper foils to form an insulating protective layer ; S4 protective film is applied on the front, and the protective film is applied on the patterned copper foil; S5 wafer thinning, the wafer is thinned to 10-200um; S6 peeling film, the protective film is thinned Tear off from the patterned copper foil; S7 backside metallization, metallize the backside of the wafer to form a backside electrode; S8 dicing and packaging.

Further: in S1, the conductive copper foil is formed into a patterned copper foil by stamping or etching, and the conductive copper foil can be replaced with a tin-plated copper sheet or a nickel-plated copper sheet.

Further: the thickness of the conductive copper foil is 3-500um.

Further: in S3, the insulating material is polyimide or solder mask green oil.

The beneficial effect of the present invention is that the electrode conductive column-bound wafer fabrication method of the present invention realizes ultra-thin wafer processing through the chip front design process and the back thinning process, which can improve the power density of the chip, reduce the thermal resistance, and reduce the package volume. . And by thickening the metal layer and protecting the insulating layer, the strength of the wafer is improved and the probability of wafer breakage is reduced. Making the product suitable for various power device chips such as diodes, triodes, MOSFETs, IGBTs, TVS, SCRs, GTOs, SiC Diodes, SiC MOSFETs, GaN MOSFETs, etc.

Description of drawings

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

1 is a schematic structural diagram of a method for manufacturing an electrode conductive column-bound wafer according to the present invention;

FIG. 2 is a perspective structural view.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention. On the contrary, embodiments of the present invention include all changes, modifications and equivalents falling within the spirit and scope of the appended claims.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", " Rear, Left, Right, Vertical, Horizontal, Top, Bottom, Inner, Outer, Axial, Radial, Circumferential, etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limiting the invention.

Furthermore, the terms "first," "second," etc. are used for descriptive purposes only and should not be construed to indicate or imply relative importance. In the description of the present invention, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection. Ground connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations. Also, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

Any description of a process or method in the flowcharts or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing a specified logical function or step of the process , and the scope of the preferred embodiments of the present invention includes alternative implementations in which the functions may be performed out of the order shown or discussed, including performing the functions substantially concurrently or in the reverse order depending upon the functions involved, which should It is understood by those skilled in the art to which the embodiments of the present invention belong.

As shown in FIG. 1 and FIG. 2 , the present invention provides a method for manufacturing a wafer with electrode conductive pillars bonded, including the following steps: S1, the conductive copper foil is made into a patterned copper foil; S2, wafer bonding, in the pattern Brush the solder paste on the copper foil, bind the wafer on the patterned copper foil, and perform high temperature sintering; S3 is filled with an insulating protective layer, and an insulating material is filled between the patterned copper foils to form an insulating protective layer ; S4 protective film is applied on the front, and the protective film is applied on the patterned copper foil; S5 wafer thinning, the wafer is thinned to 10-200um; S6 peeling film, the protective film is thinned Tear off from the patterned copper foil; S7 backside metallization, metallize the backside of the wafer to form a backside electrode; S8 dicing and packaging.

In S1, the conductive copper foil is formed into a patterned copper foil by stamping or etching, and the conductive copper foil can be replaced with a tin-plated copper sheet or a nickel-plated copper sheet. The thickness of the conductive copper foil is 3-500um. In S3, the insulating material is polyimide or solder mask green oil.

This solution realizes ultra-thin wafer processing through the chip front design process and the back thinning process, which can improve the power density of the chip, reduce the thermal resistance, and reduce the package volume. Making the product suitable for various power device chips such as diodes, triodes, MOSFETs, IGBTs, TVS, SCR, GTO, SiC Diodes, SiC MOSFETs, GaN MOSFETs, etc.

This scheme forms a conductive seed layer, or a solderable layer (Ag or Cu, Sn, Ni, Ti, Au, etc.) by sputtering or electron beam evaporation or chemical plating without backside metallization of the wafers produced by the fab. ), or by electroless nickel-gold plating technology, a solderable metal layer is formed on the surface of the chip electrode, and then etched 3-500um thick copper sheet or tin-plated, nickel-plated copper sheet is used as the conductive column material, and brushed on the copper sheet at the same time Solder paste is applied, and the wafer-level alignment and binding are performed, and then the copper sheet is welded to the chip by high-temperature sintering, and the exposed metal seed layer is cleaned and corroded, and then the gap between the metal columns is filled with insulating material. Curing increases the overall thickness of the wafer by 10-500um, which is convenient for the backside to be thinned.

This scheme has the following advantages:

1. Through the process of thickening the metal conductive layer on the front, the internal resistance of the chip due to the wire bonding process is increased, and the thermal resistance is increased.

2. By thickening the metal layer and protecting the insulating layer, the strength of the wafer is improved and the probability of wafer breakage is reduced.

3. Replace the lead process of traditional packaging by thickening the metal layer on the front to reduce the resistance value and improve the heat dissipation.

4. Through the front support, reduce the thickness of the substrate on the back of the wafer as much as possible, directly reduce the on-resistance or on-voltage drop, etc., reduce the thermal resistance of the semiconductor material itself, and improve the heat dissipation speed.

5. Through the actual finished product test, the chip size can be reduced by 40%.

6. The chip cost is reduced by about 30%, which greatly reduces the customer's use cost.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of such terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Taking the above ideal embodiments according to the present invention as inspiration, and through the above description, relevant personnel can make various changes and modifications without departing from the technical idea of the present invention. The technical scope of the present invention is not limited to the contents in the specification, and the technical scope must be determined according to the scope of the claims.

Claims (4)

1. The method for manufacturing the electrode conductive column bonded wafer is characterized by comprising the following steps of:

s1, making the conductive copper foil into a patterned copper foil;

s2, binding the wafer, brushing solder paste on the patterned copper foil, binding the wafer on the patterned copper foil, and sintering at high temperature;

s3 filling the insulation protection layer, and filling insulation materials between the patterned copper foils to form the insulation protection layer;

s4, pasting the front side of the protective film, and pasting the protective film on the patterned copper foil;

s5, thinning the wafer to 10-200 um;

s6, tearing the protective film from the patterned copper foil;

s7, back metallization, wherein the back of the wafer is metallized to form a back electrode;

s8 dicing the package.

2. The method for fabricating an electrode-conductive pillar bonded wafer as claimed in claim 1, wherein: in S1, the conductive copper foil is made into a patterned copper foil by stamping or corrosion forming, and the conductive copper foil can be replaced by a tin-plated copper sheet or a nickel-plated copper sheet.

3. The method for fabricating an electrode-conductive pillar bonded wafer as claimed in claim 1, wherein: the thickness of the conductive copper foil is 3-500 um.

4. The method for fabricating an electrode-conductive pillar bonded wafer as claimed in claim 1, wherein: in S3, the insulating material is polyimide or solder resist green oil.

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