CN114843196A - Electrode conductive column binding type wafer manufacturing method - Google Patents
Electrode conductive column binding type wafer manufacturing method Download PDFInfo
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- CN114843196A CN114843196A CN202210200435.5A CN202210200435A CN114843196A CN 114843196 A CN114843196 A CN 114843196A CN 202210200435 A CN202210200435 A CN 202210200435A CN 114843196 A CN114843196 A CN 114843196A
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- copper foil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/11019—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a method for manufacturing an electrode conductive column bound wafer, which comprises the following steps: s1, manufacturing the conductive copper foil into a patterned copper foil; s2 wafer binding; s3 filling an insulating protective layer; s4, pasting the front side of the protective film; s5, thinning the wafer; s6 tearing the film; s7 back metallization; s8 dicing the package. The ultra-thin wafer processing is realized through the front design process and the back thinning process of the chip, the power density of the chip can be improved, the thermal resistance is reduced, and the packaging volume is reduced. And through thickening the metal layer and protecting the insulating layer, the wafer strength is improved, and the wafer breakage probability is reduced. The product is suitable for various power device chip Diodes, triodes, MOSFETs, IGBTs, TVSs, SCRs, GTOs, SiC Diodes, SiC MOSFETs, GaN MOSFETs and the like.
Description
Technical Field
The invention relates to the field of electronic element manufacturing, in particular to an electrode conductive column binding type wafer manufacturing method.
Background
Integrated circuit chips are continuously developed towards high density, light weight and thin shape, and in order to meet the requirements, wafers need to be thinned and cut. The wafer thinning technology is a key technology for packaging the stacked chips, and the thinning process is an important process for chip production and has a great influence on the production quality of the chips. In the current wafer thinning process, the wafer is generally thinned to a predetermined thickness range, and then the wafer is cut into individual chips. However, with the development of the chip industry, the thickness of the chip is thinner and thinner, the direct thinning treatment is performed according to the current thinning process, and the wafer is easy to be broken in the thinning process due to too thin, so that the production quality is greatly influenced, and the yield is reduced.
Disclosure of Invention
The invention aims to solve the technical problem that in the current wafer thinning process, the wafer is generally thinned to a preset thickness range, and then the wafer is cut into single chips. However, with the development of the chip industry, the thickness of the chip is thinner and thinner, the direct thinning treatment is performed according to the current thinning procedure, the wafer is easy to be broken in the thinning process due to too thin, the production quality is greatly influenced, and the yield is reduced.
The technical scheme adopted by the invention for solving the technical problem is as follows: a method for manufacturing an electrode conductive column bonded wafer comprises the following steps: s1, manufacturing the conductive copper foil into a patterned copper foil; s2, binding the wafer, brushing solder paste on the patterned copper foil, binding the wafer on the patterned copper foil, and sintering at high temperature; s3 filling the insulation protection layer, and filling insulation materials between the patterned copper foils to form the insulation protection layer; s4, pasting the front side of the protective film, and pasting the protective film on the patterned copper foil; s5, thinning the wafer to 10-200 um; s6, tearing the protective film from the patterned copper foil; s7, back metallization, wherein the back of the wafer is metallized to form a back electrode; s8 dicing the package.
Further: in S1, the conductive copper foil is made into a patterned copper foil by stamping or corrosion forming, and the conductive copper foil can be replaced by a tin-plated copper sheet or a nickel-plated copper sheet.
Further: the thickness of the conductive copper foil is 3-500 um.
Further: in S3, the insulating material is polyimide or solder resist green oil.
The method for manufacturing the electrode conductive column binding type wafer has the advantages that the ultrathin wafer processing is realized through the front design process and the back thinning process of the chip, the power density of the chip can be improved, the thermal resistance is reduced, and the packaging volume is reduced. And through thickening the metal layer and protecting the insulating layer, the wafer strength is improved, and the wafer breakage probability is reduced. The product is suitable for various power device chip Diodes, triodes, MOSFETs, IGBTs, TVSs, SCRs, GTOs, SiC Diodes, SiC MOSFETs, GaN MOSFETs and the like.
Drawings
The invention is further illustrated with reference to the following figures and examples.
FIG. 1 is a schematic structural diagram of a method for manufacturing an electrode-conductive pillar bonded wafer according to the present invention;
fig. 2 is a perspective view.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. On the contrary, the embodiments of the invention include all changes, modifications and equivalents coming within the spirit and terms of the claims appended hereto.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", and the like, indicate orientations and positional relationships based on the orientations and positional relationships shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be considered as limiting the present invention.
Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as being fixed or detachable or integrally connected; can be mechanically or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
As shown in fig. 1 and fig. 2, the present invention provides a method for manufacturing an electrode-conductive pillar bonded wafer, including the following steps: s1, manufacturing the conductive copper foil into a patterned copper foil; s2, binding the wafer, brushing solder paste on the patterned copper foil, binding the wafer on the patterned copper foil, and sintering at high temperature; s3 filling the insulation protection layer, and filling insulation materials between the patterned copper foils to form the insulation protection layer; s4, pasting the front side of the protective film, and pasting the protective film on the patterned copper foil; s5, thinning the wafer to 10-200 um; s6, tearing the protective film from the patterned copper foil; s7, back metallization, wherein the back of the wafer is metallized to form a back electrode; s8 dicing the package.
In S1, the conductive copper foil is made into a patterned copper foil by stamping or corrosion forming, and the conductive copper foil can be replaced by a tin-plated copper sheet or a nickel-plated copper sheet. The thickness of the conductive copper foil is 3-500 um. In S3, the insulating material is polyimide or solder resist green oil.
According to the scheme, the ultra-thin wafer processing is realized through the front design process and the back thinning process of the chip, the power density of the chip can be improved, the thermal resistance is reduced, and the packaging volume is reduced. The product is suitable for various power device chip Diodes, triodes, MOSFETs, IGBTs, TVSs, SCRs, GTOs, SiC Diodes, SiC MOSFETs, GaN MOSFETs and the like.
According to the scheme, the wafer coming out of a wafer factory is not subjected to back metallization, a conductive seed layer is formed through a sputtering or electron beam evaporation or chemical plating mode, or a weldable layer (Ag or Cu, Sn, Ni, Ti and Au) is formed, or a weldable metal layer is formed on the surface of a chip electrode through a chemical nickel-gold plating technology, then an etched copper sheet with the thickness of 3-500um or tinned is used as a conductive column material, meanwhile, tin paste is brushed on the copper sheet, wafer-level alignment binding is carried out, then the copper sheet is welded with the chip through high-temperature sintering, the exposed metal seed layer is cleaned and corroded, then a gap between metal columns is filled through a cloth insulating material, and then solidification is carried out, so that the whole thickness of the wafer is increased by 10-500um, and back gold thinning is facilitated.
The scheme has the following advantages:
1. the internal resistance and the thermal resistance of the chip caused by the routing process are improved by the process of thickening the metal conducting layer on the front surface.
2. By thickening the metal layer and the protective insulating layer, the strength of the wafer is improved, and the breakage probability of the wafer is reduced.
3. The front surface is thickened with the metal layer to replace the lead process of the traditional packaging, so that the conductive resistance is reduced, and the heat dissipation is improved.
4. Through front support, the thickness of the substrate on the back of the wafer is reduced as much as possible, the on-resistance or on-voltage drop and other modes are directly reduced, the self thermal resistance of the semiconductor material is reduced, and the heat dissipation speed is improved.
5. Through actual product testing, the chip size can be reduced by 40%.
6. The cost of the chip is reduced by about 30 percent, and the use cost of a client is greatly reduced.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic representation of the term does not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (4)
1. The method for manufacturing the electrode conductive column bonded wafer is characterized by comprising the following steps of:
s1, making the conductive copper foil into a patterned copper foil;
s2, binding the wafer, brushing solder paste on the patterned copper foil, binding the wafer on the patterned copper foil, and sintering at high temperature;
s3 filling the insulation protection layer, and filling insulation materials between the patterned copper foils to form the insulation protection layer;
s4, pasting the front side of the protective film, and pasting the protective film on the patterned copper foil;
s5, thinning the wafer to 10-200 um;
s6, tearing the protective film from the patterned copper foil;
s7, back metallization, wherein the back of the wafer is metallized to form a back electrode;
s8 dicing the package.
2. The method for fabricating an electrode-conductive pillar bonded wafer as claimed in claim 1, wherein: in S1, the conductive copper foil is made into a patterned copper foil by stamping or corrosion forming, and the conductive copper foil can be replaced by a tin-plated copper sheet or a nickel-plated copper sheet.
3. The method for fabricating an electrode-conductive pillar bonded wafer as claimed in claim 1, wherein: the thickness of the conductive copper foil is 3-500 um.
4. The method for fabricating an electrode-conductive pillar bonded wafer as claimed in claim 1, wherein: in S3, the insulating material is polyimide or solder resist green oil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210200435.5A CN114843196A (en) | 2022-03-02 | 2022-03-02 | Electrode conductive column binding type wafer manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210200435.5A CN114843196A (en) | 2022-03-02 | 2022-03-02 | Electrode conductive column binding type wafer manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| CN114843196A true CN114843196A (en) | 2022-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210200435.5A Pending CN114843196A (en) | 2022-03-02 | 2022-03-02 | Electrode conductive column binding type wafer manufacturing method |
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| CN (1) | CN114843196A (en) |
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2022
- 2022-03-02 CN CN202210200435.5A patent/CN114843196A/en active Pending
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