CN114840071A - Sequential control circuit and method - Google Patents
Sequential control circuit and method Download PDFInfo
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- CN114840071A CN114840071A CN202210334294.6A CN202210334294A CN114840071A CN 114840071 A CN114840071 A CN 114840071A CN 202210334294 A CN202210334294 A CN 202210334294A CN 114840071 A CN114840071 A CN 114840071A
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- 238000000034 method Methods 0.000 title claims abstract description 31
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
Abstract
The embodiment of the application provides a sequential control circuit and a sequential control method, wherein the sequential control circuit comprises: the level of the first signal terminal is used for responding to a first sudden change and descending at a first speed from the normal working level of the signal to be controlled under the condition that the power supply source of the integrated circuit generates the first sudden change; a level of the second signal terminal for falling at a second speed from a normal operating level of the reference signal in response to the first abrupt change in the power supply of the integrated circuit in the case of said first abrupt change; and the time sequence control unit is used for conducting the first signal end and the second signal end under the condition that the second speed is higher than the first speed and the difference value between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to a preset level, so that the level of the current signal to be controlled is reduced at a third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the signal to be controlled in time sequence comparison is a target time difference so as to realize time sequence control of the signal to be controlled.
Description
Technical Field
The present disclosure relates to Integrated Circuits (ICs), and more particularly, to a timing control Circuit and method.
Background
In the related IC technology, a power-off timing sequence of an IC is controlled by a Programmable Array logic (FPGA), and the FPGA can be implemented only when standby power is needed; in the case of sudden power-off of the IC power supply, the power-off timing of the IC cannot be guaranteed, which may cause unexpected problems.
Disclosure of Invention
Embodiments of the present application are intended to provide a timing control circuit and method.
In a first aspect, an embodiment of the present application provides a timing control circuit, where the circuit includes: the timing control circuit comprises a first signal end, a second signal end and a timing control unit which is bridged between the first signal end and the second signal end; the first signal end is connected with a signal to be controlled on the integrated circuit; the second signal end is connected with a reference signal on the integrated circuit;
the level of the first signal terminal is used for responding to a first sudden change when a power supply source of the integrated circuit generates the first sudden change and descending at a first speed from the normal working level of the signal to be controlled;
the level of the second signal terminal is used for responding to the first sudden change and descending at a second speed from the normal working level of the reference signal under the condition that the power supply of the integrated circuit generates the first sudden change;
the time sequence control unit is used for conducting the first signal end and the second signal end under the condition that the second speed is higher than the first speed and the difference value between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to a preset level, so that the level of the current signal to be controlled is reduced at a third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal of the signal to be controlled is a target time difference so as to realize time sequence control of the signal to be controlled; the third speed is greater than the first speed.
In a second aspect, an embodiment of the present application provides a timing control method for an integrated circuit, where the integrated circuit includes a first signal terminal, a second signal terminal, and a timing control unit connected across the first signal terminal and the second signal terminal, the method includes:
a first sudden change of a power supply source of the integrated circuit; the first signal end responds to the first sudden change and descends at a first speed from the normal working level of the signal to be controlled; the second signal terminal is responsive to the first abrupt change to drop at a second rate from a normal operating level of the reference signal;
under the condition that the second speed is higher than the first speed and the difference value between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to a preset level, the timing control unit conducts the first signal end and the second signal end to enable the level of the current signal to be controlled to be reduced at a third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the timing comparison signal of the signal to be controlled is the target time difference so as to realize timing control on the signal to be controlled; the third speed is greater than the first speed.
In the embodiment of the application, by selecting the second signal end corresponding to the reference signal, and setting the timing control unit between the first signal end and the second signal end corresponding to the signal to be controlled, under the condition that the power supply source of the integrated circuit generates a first sudden change, the normal working level of the signal to be controlled is reduced at a first speed, and the normal working level of the reference signal is reduced at a second speed; under the condition that the second speed is higher than the first speed and the difference value between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to the preset level, the time sequence control unit conducts the first signal end and the second signal end, so that the level of the current signal to be controlled is reduced at a third speed, the difference value between the power-off time of the signal to be controlled and the power-off time of the signal to be controlled is a target time difference, the time sequence control of the signal to be controlled is realized, the power-off time sequence of the IC is ensured, and the problem that the IC cannot be expected is avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic structural diagram of a timing control circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating a structure of another timing control circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating a structure of another timing control circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another timing control circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a timing control circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of another timing control circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating a specific structure of a sequential circuit control circuit according to an embodiment of the present disclosure;
FIG. 8a is a waveform diagram of the level of the terminal A when the timing control circuit is not set in the case of sudden power down of the integrated circuit according to the embodiment of the present application;
FIG. 8B is a diagram illustrating a waveform of a voltage level at a node B in case of sudden power down of an integrated circuit according to an embodiment of the present application;
FIG. 8c is a diagram illustrating a level waveform of a node A when the timing control circuit is configured in case of sudden power down of the integrated circuit according to an embodiment of the present application;
FIG. 9a is a diagram illustrating a level waveform of a node A when the timing control circuit is not configured in case of sudden power down of the integrated circuit according to an embodiment of the present application;
FIG. 9b is a diagram illustrating a waveform of a voltage level at a node D in case of sudden power down of an integrated circuit according to an embodiment of the present application;
FIG. 9c is a diagram illustrating a level waveform of a node A when the timing control circuit is configured in case of sudden power down of the integrated circuit according to an embodiment of the present application;
fig. 10 is a schematic flowchart illustrating an implementation of a timing control method of an integrated circuit according to an embodiment of the present disclosure;
fig. 11 is a schematic flow chart illustrating an implementation of another timing control method for an integrated circuit according to an embodiment of the present disclosure;
fig. 12 is a schematic implementation flowchart of a timing control method for an integrated circuit according to an embodiment of the present disclosure.
Detailed Description
The present application will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the examples provided herein are merely illustrative of the present application and are not intended to limit the present application. In addition, the following examples are provided as partial examples for implementing the present application, not all examples for implementing the present application, and the technical solutions described in the examples of the present application may be implemented in any combination without conflict.
It should be noted that in the embodiments of the present application, the terms "comprises", "comprising" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a method or apparatus including a series of elements includes not only the explicitly recited elements but also other elements not explicitly listed or inherent to the method or apparatus. Without further limitation, the use of the phrase "including a. -. said." does not exclude the presence of other elements (e.g., steps in a method or elements in a device, such as portions of circuitry, processors, programs, software, etc.) in the method or device in which the element is included.
The term "and/or" herein is merely an association relationship describing an associated object, and means that there may be three relationships, e.g., U and/or W, which may mean: u exists alone, U and W exist simultaneously, and W exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of U, W, V, and may mean including any one or more elements selected from the group consisting of U, W and V.
In motherboard design, there are specific requirements for the power-up and power-down timing of the main IC. For example, signal 1 on the main IC needs to be powered down before signal 2 to avoid unnecessary motherboard issues. Normally, the power-off sequence of the main IC can be controlled by the FPGA, but the necessary backup power of the FPGA must be guaranteed. Therefore, when the power of the main IC is suddenly cut off, the power-off sequence of the main IC cannot be controlled, and the power-off sequence of the main IC may be incorrect, thereby causing some unexpected motherboard problems.
That is, even when the FPGA is provided with a backup power supply, the power-off timing of the main IC cannot be ensured. In a step of the present invention, even though the FPGA can control the power-off timing of the IC when the power supply is suddenly turned off, the FPGA has a problem of high cost.
In view of the above technical problem, an embodiment of the present application provides a timing control circuit, as shown in fig. 1, the timing control circuit 100 includes: a first signal terminal 101, a second signal terminal 102 and a timing control unit 103 connected between the first signal terminal 101 and the second signal terminal 102 in a bridge; the first signal terminal 101 is connected with a signal to be controlled on the integrated circuit; the second signal terminal 102 is connected to a reference signal on the integrated circuit;
the level of the first signal terminal 101 is used for responding to a first sudden change when a power supply source of the integrated circuit generates the first sudden change, and the level is reduced at a first speed from the normal working level of the signal to be controlled;
the level of the second signal terminal 102 is used for responding to the first sudden change and descending at a second speed from the normal working level of the reference signal under the condition that the power supply of the integrated circuit generates the first sudden change;
the timing control unit 103 is configured to, when the second speed is greater than the first speed and a difference between a current level of the signal to be controlled and a current level of the reference signal is greater than or equal to a preset level, turn on the first signal terminal 101 and the second signal terminal 102, so that the current level of the signal to be controlled decreases at a third speed, and a difference between a power-off time of the signal to be controlled and a power-off time of a timing comparison signal of the signal to be controlled is a target time difference, so as to implement timing control on the signal to be controlled; the third speed is greater than the first speed.
Here, the first signal terminal 101 may be any one of a plurality of signal terminals on an integrated circuit that needs to control a power-off timing. The second signal terminal 102 may be a signal terminal different from the first signal terminal selected from a plurality of signal terminals of the integrated circuit for use as a reference signal.
Here, the signal to be controlled may include at least one of: power supply, communication signal.
It will be appreciated that the first sudden change may be caused by a sudden loss of power to the power supply of the integrated circuit; the first abrupt change in the power supply of the integrated circuit may be a change in the power supply of the integrated circuit that rapidly drops from a normal operating level to zero.
In some possible embodiments, the normal operating level of the signal to be controlled is lower than the normal operating level of the reference signal. For example, the normal operating level of the signal to be controlled may be 1.8V (volts); the normal operating level of the reference signal may be 2.5V.
It is understood that the timing control unit 103 may be composed of hardware electronic components. The preset level is associated with the constituent elements of the timing control unit 103. In case the timing control unit 103 includes a diode, the preset level may be a forward turn-on voltage of the diode. Wherein the preset level may be 0.7V for a silicon diode and 0.3V for a germanium diode.
In one embodiment, the power-off timing requirement for the signal to be controlled in the IC may be that a difference between the power-off time of the signal to be controlled and the timing comparison of the signal to be controlled is a target time difference. That is, after the power-off of the signal to be controlled, the time sequence comparison signal of the signal to be controlled is powered off after the duration of the target time difference.
In some possible embodiments, the timing control unit turns on the first signal terminal and the second signal terminal when the second speed is greater than the first speed and when a difference between a current level of the signal to be controlled and a current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal terminal and the second signal terminal, and a level of the current signal to be controlled of the first signal terminal is decreased to the level of the current reference signal at a third speed that is greater than the first speed.
The embodiment of the application does not limit the magnitude relation between the third speed and the second speed, the third speed can be greater than the second speed or less than the second speed, and as long as after the signal to be controlled is accelerated from the first speed to the third speed, the power-off time difference of the signal can be compared with the time sequence of the signal to be controlled to be the target time difference.
In the embodiment of the application, by selecting the second signal end corresponding to the reference signal, and setting the timing control unit between the first signal end and the second signal end corresponding to the signal to be controlled, under the condition that the power supply source of the integrated circuit generates a first sudden change, the normal working level of the signal to be controlled is reduced at a first speed, and the normal working level of the reference signal is reduced at a second speed; under the condition that the second speed is higher than the first speed and the difference value between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to the preset level, the time sequence control unit conducts the first signal end and the second signal end, so that the level of the current signal to be controlled is reduced at a third speed, the difference value between the power-off time of the signal to be controlled and the power-off time of the signal to be controlled is a target time difference, the time sequence control of the signal to be controlled is realized, the power-off time sequence of the IC is ensured, and the problem that the IC cannot be expected is avoided.
Fig. 2 is a schematic diagram of another timing control circuit according to an embodiment of the present disclosure, and as shown in fig. 2, the timing control circuit 200 includes: a first signal terminal 201, a second signal terminal 202 and a diode 203 connected in series between said first signal terminal 201 and said second signal terminal 202; the first signal terminal 201 is connected with a signal to be controlled on the integrated circuit; the second signal terminal 202 is connected to a reference signal on the integrated circuit;
the level of the first signal terminal 201 is used for responding to a first sudden change when a power supply source of the integrated circuit generates the first sudden change, and the level is reduced at a first speed from the normal working level of the signal to be controlled;
the level of the second signal terminal 202 is used for responding to the first sudden change and descending at a second speed from the normal working level of the reference signal under the condition that the power supply of the integrated circuit generates the first sudden change; the second speed is a target speed corresponding to the target time difference;
the diode 203 is configured to be turned on when the second speed is greater than the first speed and when a difference between a current level of the signal to be controlled and a current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal end 201 and the second signal end 202, the current level of the signal to be controlled decreases at the third speed, and a difference between a power-off time of the signal to be controlled and a power-off time of the timing comparison signal is the target time difference, so as to implement timing control on the signal to be controlled.
In some possible embodiments, the target speed may be a falling speed that ensures a normal operating level of the reference signal when a difference between a power-off time of the signal to be controlled and a power-off time of the timing comparison signal of the signal to be controlled is a target time difference in a case where the timing control unit includes only a diode. For example, the target time difference may be 50 ms, and in the case where the power supply of the integrated circuit has a first sudden change and the reference signal on the second signal terminal is decreased from the normal operating level at the target speed, the off time of the signal to be controlled may be exactly 50 ms different from the timing comparison of the signal to be controlled.
It can be understood that, when a first sudden change occurs in a power supply of an integrated circuit, a signal to be controlled on a first signal terminal is decreased from a normal operating level at a first speed, a reference signal on a second signal terminal is decreased from the normal operating level at a second speed, the second speed is greater than the first speed, and when a difference between a level of the signal to be controlled and a level of a current reference signal is greater than or equal to a preset level, a diode is turned on, the first signal terminal and the second signal terminal form a loop, the level of the signal to be controlled is decreased to a fixed level (a conduction voltage drop of the diode) different from the current reference signal at three speeds and then is slowly decreased to zero, and a difference between a power-off time (a level is decreased to zero) of the signal to be controlled and a power-off time of the signal to be controlled is a target time difference.
In the embodiment of the present application, when a first sudden change occurs in a power supply of an integrated circuit, a speed of a reference signal of a selected second signal port falling from a normal operating level is relatively appropriate, and in a case where a target speed corresponding to a target time difference is exactly the same, a time sequence control of a signal to be controlled can be implemented only by arranging a diode between a first signal port and a second signal port.
Fig. 3 is a schematic diagram of a structure of another timing control circuit according to an embodiment of the present disclosure, and as shown in fig. 3, the timing control circuit 300 includes: a first signal terminal 301, a second signal terminal 302, a diode 303 connected in series between the first signal terminal 301 and the second signal terminal 302, and a delay circuit 304 connected in series between the diode 303 and the first signal terminal 301 or between the diode 303 and the second signal terminal 302;
the level of the first signal terminal 301 is used for responding to a first sudden change when a power supply source of the integrated circuit generates the first sudden change, and descending at a first speed from the normal working level of the signal to be controlled;
the level of the second signal terminal 302 is used for responding to the first sudden change and descending at a second speed from the normal working level of the reference signal under the condition that the power supply of the integrated circuit generates the first sudden change; the second speed is greater than the target speed;
the delay circuit 304 is configured to delay a first time; the first duration is determined according to the power-off time of the signal to be controlled corresponding to the second speed;
the diode 303 is configured to be turned on after delaying the first time when the second speed is greater than the first speed and when a difference between a current level of the signal to be controlled and a current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal end and the second signal end, the current level of the signal to be controlled decreases at the third speed, and a difference between a power-off time of the signal to be controlled and a power-off time of the timing comparison signal is the target time difference, so as to implement timing control on the signal to be controlled.
It will be appreciated that for the case where the second speed is greater than the target speed, it may be that in the case where the target time difference is 50 milliseconds and the power supply of the integrated circuit has a first sudden change, the level of the signal to be controlled drops too fast, resulting in a difference between the power-off time of the signal to be controlled and the power-off time of the signal to be controlled of greater than 50 milliseconds, for example, a difference between the power-off time of the signal to be controlled and the power-off time of the signal to be controlled of 60 milliseconds.
In some possible embodiments, the first duration is a difference between a power-off time of the signal to be controlled corresponding to the second speed and a target power-off time of the signal to be controlled. The target power-off time of the signal to be controlled is determined according to the difference value of the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal of the signal to be controlled as the target time difference. For example, the target time difference may be 5 seconds; the time sequence of the signal to be controlled is compared with the power-off time of the signal and can be 3 hours, 5 minutes and 20 seconds; then the target power-off time of the corresponding signal to be controlled is 3 hours, 5 minutes and 15 seconds; meanwhile, the power-off time of the signal to be controlled corresponding to the second speed is 3 hours, 5 minutes and 10 seconds, and the first time length is a difference (5 seconds) between 3 hours, 5 minutes and 15 seconds and 3 hours, 5 minutes and 10 seconds.
In the embodiment of the application, the delay circuit is arranged, so that the diode is conducted for the first time delay, the power-off time of the signal to be controlled and the power-off time difference of the time sequence comparison signal are the target time difference, and the time sequence control of the signal to be controlled is realized.
Fig. 4 is a schematic diagram of a structure of another timing control circuit according to an embodiment of the present disclosure, and as shown in fig. 4, the timing control circuit 400 includes: a first signal terminal 401, a second signal terminal 402, a diode 403 connected in series between the first signal terminal 401 and the second signal terminal 402, and at least one first delay circuit 404 connected in series between the diode 403 and the first signal terminal 401 or between the diode 403 and the second signal terminal 402;
the level of the first signal terminal 401 is used for responding to a first sudden change when a power supply source of the integrated circuit generates the first sudden change, and descending at a first speed from the normal working level of the signal to be controlled;
a level of the second signal terminal 402 for falling at a second rate from a normal operating level of the reference signal in response to the first abrupt change in the power supply of the integrated circuit in the case of the first abrupt change; the second speed is greater than the target speed;
each first delay circuit comprises a first resistor and a first capacitor; the first resistor is connected in series between the first signal end and the anode of the diode; the first capacitor is bridged between the first signal end and the common node and the grounding end of the diode;
each first delay circuit is used for delaying a second duration with first precision based on the impedance value of the first resistor and the capacitive reactance value of the first capacitor; the second time length is determined according to the number of the first delay circuits and the first time length; the first duration is determined according to the power-off time of the signal to be controlled corresponding to the second speed; the precision of the first duration is a first precision;
the diode 403 is configured to delay the first time period and then conduct the first time period when the second speed is greater than the first speed and when a difference between a current level of the signal to be controlled and a current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal end 401 and the second signal end 402, the current level of the signal to be controlled decreases at the third speed, and a difference between a power-off time of the signal to be controlled and a power-off time of the timing comparison signal is the target time difference, so as to implement timing control on the signal to be controlled.
Here, the first accuracy may be an accuracy in units of seconds. The first delay circuit is a delay circuit corresponding to a second duration of the first precision.
It can be understood that the delay time duration of the first delay circuit can be made to be the second time duration by selecting a suitable impedance value of the first resistor and a suitable capacitance value of the first capacitor.
In some possible embodiments, the second time period may be a quotient of the first time period divided by the number of the first delay circuits.
In the embodiment of the application, the corresponding at least one first delay circuit can be selected according to the first time length of the first precision, and the diode is enabled to be switched on for delaying the first time length of the first precision through the at least one first delay circuit, so that the precision of the difference between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal can meet the precision requirement of the target time difference, and the time sequence control of the signal to be controlled is realized.
Fig. 5 is a schematic diagram of a structure of a timing control circuit according to an embodiment of the present disclosure, and as shown in fig. 5, the timing control circuit 500 includes: a first signal terminal 501, a second signal terminal 502, a diode 503 connected in series between the first signal terminal 501 and the second signal terminal 502, and at least one second delay circuit 504 connected in series between the diode 503 and the first signal terminal 501 or between the diode 503 and the second signal terminal 502;
the level of the first signal terminal 501 is used for responding to a first sudden change when a power supply source of the integrated circuit generates the first sudden change, and descending at a first speed from the normal working level of the signal to be controlled;
the level of the second signal terminal 502 is used for responding to the first sudden change and descending at a second speed from the normal working level of the reference signal under the condition that the power supply of the integrated circuit generates the first sudden change; the second speed is greater than the target speed;
each second delay circuit comprises a second resistor, a second capacitor and a third capacitor; the second resistor is connected in series between the cathode of the diode and the second signal terminal; the second capacitor is bridged between the common node of the diode and the second resistor and the ground terminal; the third capacitor is in a cross-boundary between a common node of the second resistor and the second signal end and a ground end;
each second delay circuit is configured to delay a third duration of the second precision based on the impedance value of the second resistor, the capacitive reactance values of the second capacitor and the third capacitor; the third time length is determined according to the number of the second delay circuits and the first time length; the precision of the first duration is a second precision; the second precision is greater than the first precision;
the diode 503 is configured to conduct after delaying the first time when the second speed is greater than the first speed and when a difference between a current level of the signal to be controlled and a current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal terminal 501 and the second signal terminal 502, the current level of the signal to be controlled decreases at the third speed, and a difference between a power-off time of the signal to be controlled and a power-off time of the timing comparison signal is the target time difference, so as to implement timing control on the signal to be controlled.
Here, the second accuracy may be an accuracy in units of tenths of a second. The second delay circuit is a delay circuit corresponding to a third duration of the second precision.
It can be understood that the delay time of the second delay circuit can be made to be the third time by selecting a suitable impedance value of the second resistor and a suitable capacitive reactance value of the second capacitor and the third capacitor.
In some possible embodiments, the third time period may be the first time period divided by the number of second delay circuits.
In the implementation of the application, the corresponding at least one second delay circuit can be selected according to the first time length of the second precision, and the diode can be conducted through the at least one second delay circuit according to the first time length of the second precision, so that the accuracy of the difference between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal meets the accuracy requirement of the target time difference, and the time sequence control of the signal to be controlled is realized.
Fig. 6 is a schematic diagram of another timing control circuit according to an embodiment of the present disclosure, and as shown in fig. 6, the timing control circuit 600 includes: a first signal terminal 601, a second signal terminal 602, a diode 603 connected in series between said first signal terminal 601 and said second signal terminal 602, and at least one first delay circuit 604 and at least one second delay circuit 605 connected in series between said diode 603 and said first signal terminal 601 or said diode 603 and said second signal terminal 602;
the level of the first signal terminal 601 is used for responding to a first sudden change when a power supply source of the integrated circuit generates the first sudden change, and the level is reduced at a first speed from the normal working level of the signal to be controlled;
the level of the second signal terminal 602 is used for responding to the first sudden change and descending at a second speed from the normal working level of the reference signal under the condition that the power supply of the integrated circuit generates the first sudden change; the second speed is greater than the target speed;
at least one of the first delay circuits 604, configured to delay a first sub-duration of a first precision;
at least one of the second delay circuits 605, configured to delay a second sub-duration of a second precision;
the diode 603 is configured to be turned on after delaying a first sub-duration of the first precision and a second sub-duration of the second precision when the second speed is greater than the first speed and when a difference between a current level of the signal to be controlled and a current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal end 601 and the second signal end 602, the current level of the signal to be controlled decreases at the third speed, and a difference between a power-off time of the signal to be controlled and a power-off time of the timing comparison signal is the target time difference, so as to implement timing control on the signal to be controlled.
In the embodiment of the application, at least one first delay circuit corresponding to the first sub-duration of the first precision and at least one second delay circuit corresponding to the second sub-duration of the second precision are arranged, so that the first sub-duration of the first precision and the second sub-duration of the second precision are delayed by the diode, the power-off time of a signal to be controlled and the precision of the difference value of the power-off time of the signal compared by the time sequence can meet the precision requirement of the target time difference, the time sequence control of the signal to be controlled is realized, and the selection of the parameters of components in the first delay circuit and the second delay circuit is more flexible and diversified.
In the embodiment of the application, the purpose of controlling the power-off time sequence of the signal to be controlled is achieved by rapidly pulling down the level of the signal to be controlled through the characteristics of the diode at low cost.
Fig. 7 is a schematic diagram of a specific structure of a sequential circuit control circuit according to an embodiment of the present application, and as shown in fig. 7, the sequential circuit control circuit includes: a terminal A, a terminal B, a diode D1, a third resistor R3, a fourth resistor R4, a fourth capacitor C4 to a sixth capacitor C6; wherein R3 is connected in series between the terminals A and the positive electrode of D1; c4 is connected between the common node of R3 and D1 and the ground terminal; r4 is connected in series between the negative terminal of D1 and terminal B; c5 is connected between the common node of D1 and R4 and the ground terminal; c6 is connected across the common node of R4 and terminal B and ground.
Here, terminal a and terminal B are both signal ports on the integrated circuit; the terminal A is connected with a signal to be controlled; the normal working level of the signal to be controlled is 1.8V; the point B is connected with a reference signal; the normal working level of the reference signal is 2.5V; it can be seen that under normal power conditions on the integrated circuit, D1 is not conducting, i.e., D1 is off. However, under the condition that the power supply of the integrated circuit is suddenly powered off, because the capacitance effect at the end point a is large, the voltage drop curve of the signal to be controlled from 1.8V is slow, the comparison signal with the end C cannot meet the preset power-off time sequence requirement, and the power-off time sequence problem may be caused. For this purpose, other power supplies, which have a much faster drop speed in case of a sudden power failure of the power supply of the integrated circuit, can be used for connection to the B terminal.
Under the condition that a power supply source of an integrated circuit is suddenly powered off, the level of a terminal B is rapidly reduced from 2.5V, under the condition that the level of the terminal B is reduced to about 0.3V, the voltage at two ends of D1 reaches the conducting voltage, D1 is conducted, and therefore a loop is formed between the terminal A and the terminal B, so that the level of the terminal A can be rapidly pulled to the voltage level of about 0.3V (the voltages at the two ends can be different by the conducting voltage drop of a diode), and the purpose of meeting the requirement of a power-off time sequence is achieved.
In the embodiment of the application, the preset power-off timing requirement between the signal to be referred and the comparison signal of the terminal C can be met by adjusting the parameter values of R3, R4, C4, C5 and C6.
In the embodiment of the present application, the timing control circuit can be used not only for controlling the power supply of the integrated circuit, but also for controlling the signal, for example, resume, when the power supply of the integrated circuit is suddenly powered off, the timing control circuit can also ensure the accuracy of the timing as well as some timing requirements of some power supplies. That is, the terminals A and B are not limited to direct power, but can be connected to signals.
FIG. 8a is a diagram illustrating a level waveform of a node A when the timing control circuit is not configured in case of sudden power down of the integrated circuit according to an embodiment of the present application; as shown in fig. 8a, curve 801 is a waveform diagram of the level of the terminal a when the timing control circuit is not set in case of sudden power-off of the integrated circuit; it can be seen that when the timing control circuit is not provided, the power-off speed of the terminal a is relatively slow, and the level of the terminal a drops to zero at time t. FIG. 8B is a diagram illustrating a waveform of a voltage level at a node B in case of sudden power down of an integrated circuit according to an embodiment of the present application; as shown in fig. 8B, curve 802 is a waveform of the level at terminal B in the case of sudden power down of the integrated circuit; it can be seen that the power-off speed of the terminal B is relatively fast, and the level of the terminal B is reduced to 0.3V at time t 1; the level of endpoint B drops to zero at time t 2; FIG. 8c is a diagram illustrating a level waveform of a node A when the timing control circuit is configured in case of sudden power down of the integrated circuit according to an embodiment of the present application; as shown in fig. 8c, curve 803 is a waveform diagram of the level of terminal a when the timing control circuit is set in case of sudden power-off of the integrated circuit; it can be seen that in the case where the timing control circuit is provided, the level of the terminal a rapidly drops to around 0.3V at time t1 in the curve 803, and then the level of the terminal a drops to zero at time t 3. time t3 is a certain length of time earlier than time t.
FIG. 9a is a diagram illustrating a level waveform of a node A when the timing control circuit is not configured in case of sudden power down of the integrated circuit according to an embodiment of the present application; as shown in fig. 9a, a curve 901 is a waveform diagram of the level of the terminal a when the timing control circuit is not set in case of sudden power-off of the integrated circuit; FIG. 9b is a diagram illustrating a waveform of a voltage level at a node D in case of sudden power down of an integrated circuit according to an embodiment of the present application; as shown in fig. 9b, the curve 902 is a waveform of the level at the terminal D in case of sudden power off of the integrated circuit; wherein, the endpoint D is a comparison endpoint of the endpoint A; the power-off time of the end point D is t 4; FIG. 9c is a diagram illustrating a level waveform of a node A when the timing control circuit is configured in case of sudden power down of the integrated circuit according to an embodiment of the present application; curve 903 is a waveform of the level at terminal a when the timing control circuit is set in the event of a sudden power down of the integrated circuit.
The description of fig. 9a refers to fig. 8 a; FIG. 8c is a depiction of FIG. 9 c; as can be seen from fig. 9a, 9b and 9c, the power-off time of the terminal a is earlier than the power-off time of the terminal D; the time interval (t4-t3) of the power-off time of the endpoint A and the endpoint D meets the preset time requirement.
Based on the foregoing embodiments, the present application provides a timing control method for an integrated circuit, where the integrated circuit includes a first signal terminal, a second signal terminal, and a timing control unit bridged between the first signal terminal and the second signal terminal; as shown in fig. 10, the timing control method includes:
step S1001: generating a first sudden change in a power supply of the integrated circuit; the first signal end responds to the first sudden change and descends at a first speed from the normal working level of the signal to be controlled; the second signal terminal is responsive to the first abrupt change to drop at a second rate from a normal operating level of the reference signal;
step S1002: under the condition that the second speed is higher than the first speed and the difference value between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to a preset level, the timing control unit conducts the first signal end and the second signal end to enable the level of the current signal to be controlled to be reduced at a third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the timing comparison signal of the signal to be controlled is the target time difference so as to realize timing control on the signal to be controlled; the third speed is greater than the first speed.
Fig. 11 is a schematic flow chart illustrating an implementation of another timing control method of an integrated circuit according to an embodiment of the present disclosure, where, as shown in fig. 11, the integrated circuit includes a first signal terminal, a second signal terminal, and a timing control unit connected across the first signal terminal and the second signal terminal; the timing control unit comprises a diode; the time sequence control method comprises the following steps:
step S1101: generating a first sudden change in a power supply of the integrated circuit; the first signal end responds to the first sudden change and descends at a first speed from the normal working level of the signal to be controlled; the second signal terminal is responsive to the first abrupt change to drop at a second rate from a normal operating level of the reference signal; the second speed is a target speed corresponding to the target time difference;
step S1002: and the diode is conducted when the second speed is higher than the first speed and when the difference value between the current level of the signal to be controlled and the current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal end and the second signal end, the current level of the signal to be controlled is reduced at the third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal is used as a target time difference to realize time sequence control of the signal to be controlled.
Fig. 12 is a schematic flow chart illustrating an implementation of a timing control method of an integrated circuit according to an embodiment of the present application, where, as shown in fig. 12, the integrated circuit includes a first signal terminal, a second signal terminal, and a timing control unit connected across the first signal terminal and the second signal terminal; the time sequence control unit comprises a diode and a time delay circuit; the time sequence control method comprises the following steps:
step S1201: generating a first sudden change in a power supply of the integrated circuit; the first signal end responds to the first sudden change and descends at a first speed from the normal working level of the signal to be controlled; the second signal terminal is responsive to the first abrupt change to drop at a second rate from a normal operating level of the reference signal; the second speed is greater than the target speed;
step S1202: the delay circuit delays a first time length; the first duration is determined according to the power-off time of the signal to be controlled corresponding to the second speed;
step S1203: and when the second speed is higher than the first speed and the difference value between the current level of the signal to be controlled and the current level of the reference signal is greater than or equal to a preset level, the diode delays the first time to conduct the first signal end and the second signal end, so that the current level of the signal to be controlled is reduced at the third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal is the target time difference, so as to realize the time sequence control of the signal to be controlled.
The foregoing description of the various embodiments is intended to highlight various differences between the embodiments, and the same or similar parts may be referred to each other, and for brevity, will not be described again herein.
The methods disclosed in the method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.
Features disclosed in various product embodiments provided by the application can be combined arbitrarily to obtain new product embodiments without conflict.
The features disclosed in the method or system embodiments provided herein may be combined in any combination to arrive at new method or system embodiments without conflict.
While the present embodiments have been described with reference to the accompanying drawings, the present embodiments are not limited to the above-described embodiments, which are merely illustrative and not restrictive, and it will be apparent to those of ordinary skill in the art that many more modifications and variations can be made in the present embodiments without departing from the spirit of the disclosure and the scope of the appended claims.
Claims (10)
1. A timing control circuit, the circuit comprising: the timing control circuit comprises a first signal end, a second signal end and a timing control unit which is bridged between the first signal end and the second signal end; the first signal end is connected with a signal to be controlled on the integrated circuit; the second signal end is connected with a reference signal on the integrated circuit;
the level of the first signal terminal is used for responding to a first sudden change when a power supply source of the integrated circuit generates the first sudden change and descending at a first speed from the normal working level of the signal to be controlled;
the level of the second signal terminal is used for responding to the first sudden change and descending at a second speed from the normal working level of the reference signal under the condition that the power supply of the integrated circuit generates the first sudden change;
the time sequence control unit is used for conducting the first signal end and the second signal end under the condition that the second speed is higher than the first speed and the difference value between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to a preset level, so that the level of the current signal to be controlled is reduced at a third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal of the signal to be controlled is a target time difference so as to realize time sequence control of the signal to be controlled; the third speed is greater than the first speed.
2. The circuit of claim 1, wherein the second speed is a target speed corresponding to the target time difference; the timing control unit comprises a diode; the diode is connected in series between the first signal terminal and the second signal terminal;
the diode is used for conducting when the second speed is higher than the first speed and when the difference value between the current level of the signal to be controlled and the current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal end and the second signal end, the current level of the signal to be controlled is reduced at the third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal is the target time difference, so that the time sequence control of the signal to be controlled is realized.
3. The circuit of claim 2, wherein the second speed is greater than the target speed; the time sequence control unit also comprises a delay circuit; the delay circuit is connected in series between the diode and the first signal terminal or between the diode and the second signal terminal;
the delay circuit is used for delaying a first time length; the first duration is determined according to the power-off time of the signal to be controlled corresponding to the second speed;
the diode is further configured to be turned on after delaying the first time when the second speed is greater than the first speed and when a difference between a current level of the signal to be controlled and a current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal end and the second signal end, the current level of the signal to be controlled decreases at the third speed, and a difference between a power-off time of the signal to be controlled and a power-off time of the timing comparison signal is the target time difference, so as to implement timing control on the signal to be controlled.
4. The circuit of claim 3, wherein the accuracy of the first duration is a first accuracy; the delay circuit comprises at least one first delay circuit corresponding to the duration of the first precision;
the first delay circuit comprises a first resistor and a first capacitor; the first resistor is connected in series between the first signal end and the anode of the diode; the first capacitor is bridged between the first signal end and the common node and the grounding end of the diode;
the first delay circuit is used for delaying a second duration of the first precision based on the impedance value of the first resistor and the capacitive reactance value of the first capacitor; the second time length is determined according to the number of the first delay circuits and the first time length.
5. The circuit of claim 4, wherein the accuracy of the first duration is a second accuracy; the second precision is greater than the first precision; the delay circuit comprises at least one second delay circuit corresponding to the duration of the second precision; the second delay circuit comprises a second resistor, a second capacitor and a third capacitor; the second resistor is connected in series between the cathode of the diode and the second signal terminal; the second capacitor is bridged between the common node of the diode and the second resistor and the ground terminal; the third capacitor is in a cross-boundary between a common node of the second resistor and the second signal end and a ground end;
the second delay circuit is configured to delay a third duration of the second precision based on the impedance value of the second resistor, the capacitive reactance values of the second capacitor and the third capacitor; the third time length is determined according to the number of the second delay circuits and the first time length.
6. The circuit of claim 5, wherein the first time duration comprises a first sub-duration of the first precision and a second sub-duration of the second precision; the delay circuit comprises at least one first delay circuit and at least one second delay circuit;
at least one first delay circuit for delaying the first sub-duration;
and the at least one second delay circuit is used for delaying the second sub-duration.
7. The circuit of any of claims 1 to 6, wherein the signal to be controlled comprises at least one of: power supply, communication signal.
8. A method for timing control of an integrated circuit, the integrated circuit comprising a first signal terminal, a second signal terminal, and a timing control unit coupled across the first signal terminal and the second signal terminal, the method comprising:
a first sudden change of a power supply source of the integrated circuit; the first signal end responds to the first sudden change and descends at a first speed from the normal working level of the signal to be controlled; the second signal terminal is responsive to the first abrupt change to drop at a second rate from a normal operating level of the reference signal;
under the condition that the second speed is higher than the first speed and the difference value between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to a preset level, the timing control unit conducts the first signal end and the second signal end to enable the level of the current signal to be controlled to be reduced at a third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the timing comparison signal of the signal to be controlled is a target time difference so as to realize timing control on the signal to be controlled; the third speed is greater than the first speed.
9. The method of claim 8, wherein the second speed is a target speed corresponding to the target time difference; the time sequence control unit comprises a diode, and the time sequence control unit conducts the first signal end and the second signal end under the condition that the second speed is higher than the first speed and the difference value between the current level of the signal to be controlled and the current level of the reference signal is greater than or equal to a preset level, so that the current level of the signal to be controlled is reduced at a third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal of the signal to be controlled is a target time difference to realize time sequence control on the signal to be controlled; the method comprises the following steps:
and the diode is conducted when the second speed is higher than the first speed and when the difference value between the current level of the signal to be controlled and the current level of the reference signal is greater than or equal to a preset level, so that a loop is formed between the first signal end and the second signal end, the current level of the signal to be controlled is reduced at the third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal is used as a target time difference to realize time sequence control of the signal to be controlled.
10. The method of claim 9, wherein the second speed is greater than the target speed; when the second speed is higher than the first speed and the difference between the level of the current signal to be controlled and the level of the current reference signal is greater than or equal to a preset level, the timing control unit conducts the first signal end and the second signal end to enable the level of the current signal to be controlled to be reduced at the third speed, and the difference between the power-off time of the signal to be controlled and the power-off time of the timing comparison signal of the signal to be controlled is a target time difference to realize timing control of the signal to be controlled; the method comprises the following steps:
the delay circuit delays a first time length; the first duration is determined according to the power-off time of the signal to be controlled corresponding to the second speed;
and when the second speed is higher than the first speed and the difference value between the current level of the signal to be controlled and the current level of the reference signal is greater than or equal to a preset level, the diode delays the first time to conduct the first signal end and the second signal end, so that the current level of the signal to be controlled is reduced at the third speed, and the difference value between the power-off time of the signal to be controlled and the power-off time of the time sequence comparison signal is the target time difference to realize the time sequence control of the signal to be controlled.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110011652A (en) * | 2019-04-08 | 2019-07-12 | 北京承力电源有限公司 | A kind of Switching Power Supply at least second level starts sequential control circuit |
| CN112834822A (en) * | 2020-04-30 | 2021-05-25 | 神亚科技股份有限公司 | Detection circuit for timing error |
| CN113917440A (en) * | 2020-07-10 | 2022-01-11 | 广州印芯半导体技术有限公司 | Optical sensor and correction method thereof |
-
2022
- 2022-03-30 CN CN202210334294.6A patent/CN114840071A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110011652A (en) * | 2019-04-08 | 2019-07-12 | 北京承力电源有限公司 | A kind of Switching Power Supply at least second level starts sequential control circuit |
| CN112834822A (en) * | 2020-04-30 | 2021-05-25 | 神亚科技股份有限公司 | Detection circuit for timing error |
| CN113917440A (en) * | 2020-07-10 | 2022-01-11 | 广州印芯半导体技术有限公司 | Optical sensor and correction method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 马平;: "一种投影仪延时断电电路的设计与实现", 黑龙江科技信息, no. 33, 25 November 2014 (2014-11-25), pages 153 - 155 * |
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