CN114839907A - Multichannel analog isolation acquisition circuit and chip - Google Patents
Multichannel analog isolation acquisition circuit and chip Download PDFInfo
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- CN114839907A CN114839907A CN202210435392.9A CN202210435392A CN114839907A CN 114839907 A CN114839907 A CN 114839907A CN 202210435392 A CN202210435392 A CN 202210435392A CN 114839907 A CN114839907 A CN 114839907A
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- G05B19/00—Programme-control systems
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- H—ELECTRICITY
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Abstract
The invention discloses a multi-channel analog isolation acquisition circuit and a chip, wherein the circuit comprises a multi-channel isolation power supply, a multi-channel analog isolation conversion circuit and an FPGA system; the multi-channel isolation power supply is electrically connected with the multi-channel analog isolation conversion circuit in a one-to-one correspondence manner; the multi-channel analog isolation conversion circuit is connected with the FPGA system; the analog isolation conversion circuit of any channel comprises a signal conditioning circuit, a voltage/digital conversion circuit and a digital isolator ISO which are sequentially connected; the multi-channel analog isolation conversion circuit realizes the conversion from the acquired analog quantity to the digital quantity and the digital quantity isolation and outputs the isolated digital quantity to the FPGA system, and the FPGA system realizes a digital signal filter and an external SPI interface. The circuit is high in integration level, small in occupied area of devices, the universality and flexibility of the circuit are improved through the digital output interface, and requirements of tens of paths or even hundreds of paths of analog voltage signals for isolation and collection can be met in a small circuit area.
Description
Technical Field
The invention belongs to the field of microelectronics, and relates to a multi-channel analog isolation acquisition circuit and a chip.
Background
In an aerospace remote measuring system, a large number of analog voltage signals such as voltage, current and temperature need to be measured for monitoring the working state of each electrical node, and meanwhile, each electrical node needs to be measured in an isolation mode for avoiding the mutual influence between each signal and the system due to the common ground of a loop.
As shown in fig. 1, in the conventional analog signal isolation and acquisition method, a linear optocoupler or a digital optocoupler is used as a core device to implement isolation of an analog signal, and the digital optocoupler and the linear optocoupler are optical medium-based transmission devices, which inevitably has a series of problems of low conversion precision, large volume, low insulation voltage resistance, high power consumption, and the like. Usually, an analog switch is required to be added to gate an acquisition channel for realizing multi-path measurement, an operational amplifier follower is required to be introduced to avoid the impedance mismatching problem caused by the analog switch, and finally, measurement data converted by the analog-to-digital converter enters the FPGA through a digital interface of the converter to form a complete isolation measurement system. Meanwhile, each acquisition channel is required to be provided with an independent isolation power supply, the whole acquisition circuit has numerous devices, the design link is complex, the cost is high, and meanwhile, a large amount of printed board area is required to be occupied, so that the method is high in price, low in bandwidth, high in power consumption, low in precision and large in printed board area is required to be occupied.
With the development trend of miniaturization, light weight and intellectualization of new generation space equipment, the number of channels needing isolation measurement in a remote measurement system continuously rises, even reaches hundreds of channels, new requirements on measurement precision are continuously provided, and meanwhile, the area of a printed board is continuously reduced. The traditional measurement system is difficult to meet the increasing measurement requirements, so that the complicated isolation acquisition circuit is difficult to meet the actual requirements in terms of device cost, design difficulty and circuit board area, and the analog voltage isolation acquisition circuit of a miniaturized, high-integration, multi-channel and built-in multi-path isolation power supply is urgently needed to be developed.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a multi-channel analog isolation acquisition circuit and a chip, thereby meeting the requirements of realizing the non-distortion and high-precision isolation acquisition of multi-channel analog voltage signals under a smaller circuit area.
The invention is realized by the following technical scheme:
a multi-channel analog isolation acquisition circuit comprises a multi-channel isolation power supply, a multi-channel analog isolation conversion circuit and an FPGA system;
the current output ends of the multi-channel isolation power supply are electrically connected with the current input ends of the multi-channel analog isolation conversion circuit in a one-to-one correspondence manner; the multi-channel analog isolation conversion circuit is connected with the FPGA system in a data transmission way;
the multichannel isolation power supply comprises an input decoupling capacitor C1, an undervoltage protection circuit, a drive bootstrap circuit, a chopper circuit, a synchronous Buck controller U1, a planar transformer T1, a primary side feedback loop and a multichannel output end rectification filter loop;
one end of the input decoupling capacitor C1 is connected with the positive end of an input power supply VIN, and the other end of the input decoupling capacitor C1 is grounded; the undervoltage protection circuit is connected with the positive end of an input power supply VIN and the synchronous Buck controller U1; the driving bootstrap circuit is connected with the positive end of an input power supply VIN and the synchronous Buck controller U1; the chopper circuit is connected with the synchronous Buck controller U1 and the planar transformer T1; the primary side feedback loop is connected with the plane transformer T1 and the synchronous Buck controller U1; the multi-channel output end rectifying and filtering loop, the planar transformer T1 and the output V OUT Connecting and setting;
the analog isolation conversion circuit of any channel in the multi-channel analog isolation conversion circuit comprises a signal conditioning circuit, a voltage/digital conversion circuit and a digital isolator ISO which are sequentially connected.
Preferably, the undervoltage protection circuit comprises a resistor R1 and a resistor R2; the resistor R1 and the resistor R2 are connected in series to form a voltage division circuit; the free end of the resistor R1 is connected with the positive end of an input power supply VIN, the free end of the resistor R2 is connected with the virtual ground end GND of the synchronous Buck controller U1, and the voltage dividing ends of the resistor R1 and the resistor R2 are connected with the enabling end EN of the synchronous Buck controller U1.
Preferably, the driving bootstrap circuit comprises a schottky diode D1 and a capacitor C4; the anode of the Schottky diode D1 is connected with the positive end of an input power supply VIN; the cathode of the Schottky diode D1 is connected with a bootstrap capacitor pin BST of the synchronous Buck controller; one end of the capacitor C4 is connected with a bootstrap capacitor pin BST of the synchronous Buck controller, and the other end of the capacitor C4 is connected with a switch node SW of the synchronous Buck controller.
Preferably, the planar transformer T1 includes a first printed board, several layers of second printed boards, and a planar magnetic core; the first printed board is provided with a primary winding, and the plurality of layers of second printed boards are provided with secondary windings; the first printed board and the plurality of layers of second printed boards are stacked, and the planar magnetic core is inserted at two sides of the stacked first printed board and the plurality of layers of second printed boards; and the thickness of the stacked first printed board and the plurality of layers of second printed boards is consistent with the height of the planar magnetic core.
Preferably, the chopper circuit comprises an NMOS transistor Q1 and an NMOS transistor Q2; the grid electrode of the NMOS tube Q1 is connected with a high-voltage opening end HO of the synchronous Buck controller U1, the drain electrode of the NMOS tube Q1 is connected with the positive end of an input voltage VIN, and the source electrode of the NMOS tube Q1 is connected with the drain electrode of the NMOS tube Q2, the switch node SW of the synchronous Buck controller U1 and the primary winding; the gate of the NMOS transistor Q2 is connected to the low-voltage turn-on terminal LO of the synchronous Buck controller, and the source of the NMOS transistor Q2 is connected to the virtual ground terminal GND of the synchronous Buck controller U1.
Preferably, the primary feedback loop comprises a capacitor C2, a capacitor C3, a resistor R3 and a resistor R4; the resistor R3 and the resistor R4 are arranged in series to form a voltage division circuit; the free end of the resistor R3 is connected with the primary winding, and the free end of the resistor R4 is connected with a virtual ground end GND of a synchronous Buck controller U1; the voltage dividing ends of the resistor R3 and the resistor R4 are connected with the feedback end FB of the synchronous Buck controller; the capacitor C3 is connected in parallel with the resistor R3, one end of the C3 is connected with the voltage division ends of the resistor R3 and the resistor R4, and the other end of the C3 is grounded; one end of the capacitor C2 is connected with the primary winding, and the other end of the capacitor C2 is connected with a virtual ground end GND of the synchronous Buck controller U1.
Preferably, any one of the multi-channel output end rectifying and filtering loops comprises a schottky diode D3, a magnetic bead MB1, a capacitor C6 and a capacitor C7; the cathode of the Schottky diode D3 is connected with one end of the capacitor C6, and two ends of the secondary winding are respectively connected with the anode of the Schottky diode D3 and the other end of the capacitor C6; the magnetic bead MB1 is serially connected into an output V OUT The capacitor C7 and the output V OUT Are arranged in parallel.
Preferably, the signal conditioning circuit comprises an operational amplifier Op1 and an operational amplifier Op 2; the inverting input terminal of the operational amplifier Op1 is connected with the output terminal of the operational amplifier Op1, and the non-inverting input terminal of the operational amplifier Op1 is connected with an input signal; the inverting input terminal of the operational amplifier Op2 and the output terminal of the operational amplifier Op2 are both connected to a virtual ground, and the non-inverting input terminal of the operational amplifier Op2 is connected to the voltage dividing terminal of the voltage dividing circuit of the voltage reference VREF.
Preferably, the voltage/digital conversion circuit includes a summing node SUM1, a summing node SUM2, an integrator I1, an integrator I2, a hysteresis comparator CMP, a voltage reference VREF, and a flip-flop FILP; a positive input terminal of the summing node SUM1 is connected to the output terminal of the follower Op1, and a negative input terminal of the summing node SUM1 is connected to the result output terminal of the flip-flop FILP; the output of the summing node SUM1 is connected to the input of the integrator I1; the positive input of the summing node SUM2 is connected to the output of the integrator I1, the negative input of the summing node SUM2 is connected to the result output of the flip-flop FILP, and the output of the summing node SUM2 is connected to the input of the integrator I2; the input end of the hysteresis comparator CMP is connected with the output end of the integrator I2, and the output end of the hysteresis comparator CMP is connected with the input D end of the flip-flop FILP; the power supply end VCC of the trigger FILP is connected with a voltage reference VREF;
one lane of the digital isolator ISO isolates the clock signal CLK and accesses the CLK end of the flip-flop FILP, and the other lane isolates the DATA signal DATA of the flip-flop FILP.
A multi-channel analog isolation acquisition chip comprises a first layer circuit board, a second layer circuit board, a third layer circuit board and a bottom board which are sequentially stacked and fixedly arranged;
the first layer circuit board and the second layer circuit board both comprise the analog isolation conversion circuit;
the third layer circuit board comprises the multi-channel isolation power supply and the FPGA system;
the distance between the first layer of circuit board, the second layer of circuit board, the third layer of circuit board and the bottom board is 0.3-0.5 mm.
Compared with the prior art, the invention has the following beneficial technical effects:
a multi-channel analog isolation acquisition circuit comprises a multi-channel isolation power supply, a multi-channel analog isolation conversion circuit and an FPGA system. The multi-channel isolation power supply provides power required by devices for the multi-channel analog isolation conversion circuit, the multi-channel analog isolation conversion circuit realizes conversion from collected analog quantity to digital quantity and digital quantity isolation and outputs the isolated digital quantity to the FPGA system, and the FPGA system realizes a digital signal filter and an external SPI (serial peripheral interface). The input decoupling capacitor C1 in the multichannel isolation power supply can be used for the input voltage V IN And filtering is carried out to reduce the noise influence of the input voltage. The undervoltage protection circuit can effectively prevent the power supply system from working when the input voltage is too low, the bootstrap circuit is driven to provide a floating power supply to enable the NMOS tube to be conducted as required, the chopper circuit converts an input direct-current power supply into an alternating-current pulse power supply, and the synchronous Buck controller U1 completes loop compensation and grid synchronizationThe planar transformer T1 forms an input winding and a secondary winding to realize an energy conversion loop in a power conversion circuit, a primary side feedback loop maintains the effective excitation voltage of the primary end of the transformer T1 unchanged in the chopping process, and an output stable multi-channel output end rectifying and filtering loop is kept. The capacitive digital isolator is used for isolation, so that the isolation and conversion of analog signals without distortion and with high precision are realized; meanwhile, the multi-channel isolation power supply comprising the planar transformer can realize multi-channel isolation output only by single power supply input, is simple in design and is suitable for an isolation signal measuring system; meanwhile, the FPGA system is arranged in the circuit, digital extraction and filtering work of the modulation signals is completed in the circuit, various requirements of a user are met, the signals after extraction and filtering are sent serially through the SPI, and the circuit is high in universality and convenient to use. The circuit is high in integration level, the occupied area of devices is greatly reduced, meanwhile, the risk caused by the traditional complex design is eliminated, the universality and the flexibility of the circuit are improved through the digital output interface, and the requirement of isolating and collecting dozens of or even hundreds of analog voltage signals can be met in a smaller circuit area.
Further, the undervoltage protection circuit comprises a resistor R1 and a resistor R2, the voltage dividing ends of the resistor R1 and the resistor R2 are connected with the enable end EN of the synchronous Buck controller U1, if the input voltage is too low to reach the enable end opening level, the synchronous Buck controller stops working, and the power supply system can be effectively prevented from working when the input voltage is too low.
Further, the bootstrap circuit is driven to provide a floating power supply, and the schottky diode D1 charges the capacitor C4 when being turned on, so as to ensure that the voltage of the bootstrap capacitor pin BST end of the synchronous Buck controller is higher than that of the SW end, and thus the NMOS transistor Q1 is turned on.
Furthermore, the planar transformer adopts multilayer printed board winding as a transformer winding, and the number of layers of the printed boards is increased if the number of the windings is increased. The planar transformer adopts the flat magnetic core, directly pegs graft in printed board both sides, pile up the back printed board thickness with the highly uniform of planar magnetic core has reduced the power height effectively, does benefit to the integrated design.
Further, the chopper circuit includes an NMOS transistor Q1 and an NMOS transistor Q2, and the synchronous Buck controller U1 turns on the high-side power NMOS transistor Q1 at a fixed frequency, and when the primary winding current of the planar transformer T1 rises linearly, the device turns off the high-side NMOS transistor Q1 and turns on the low-side NMOS transistor Q2 when the peak current of the high-side NMOS transistor Q1 is sensed to rise above the internal voltage. When the NMOS transistor Q2 is turned on, the inductor current decreases. And closing the low-voltage side NMOS tube Q2 and opening the high-voltage side NMOS tube Q1 on the rising edge of the next period, thereby realizing the charging and discharging of the primary winding of the planar transformer.
Further, the primary side feedback loop comprises a capacitor C2, a capacitor C3, a resistor R3 and a resistor R4, the resistor R3 and the resistor R4 are used as voltage dividing resistors to feed back the voltage of the output end, the capacitor C3 introduces a pole into the transfer function of the feedback loop, and the capacitor C2 is used as output end capacitor filtering.
Furthermore, any one loop in the multi-channel output end rectifying and filtering loop comprises a Schottky diode D3, a magnetic bead MB1, a capacitor C6 and a capacitor C7, the Schottky diode D3 and the capacitor C6 rectify the output voltage into direct current, and the magnetic bead MB1 and the capacitor C7 are used for filtering the output power supply.
Further, the signal conditioning circuit comprises an operational amplifier Op1 and an operational amplifier Op2, wherein the operational amplifier Op1 and the inverting terminal of the operational amplifier Op2 are connected with the output end to form a follower, the operational amplifier Op1 follows the input signal, and the operational amplifier Op2 follows half of the voltage reference VREF to provide virtual ground VG.
The utility model provides a multichannel simulation keeps apart and gathers chip, adopts the design thinking that the printing board space piles up, when increasing substantially system integration and flexibility, can also reduce entire system's design complexity, reduces the design risk, reduces development cost, satisfies the miniaturized, light, intelligent development trend of new generation aerospace equipment.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a block diagram of an isolated voltage acquisition system in the prior art;
FIG. 2 is a block diagram of a multi-channel analog isolation acquisition circuit of the present invention;
FIG. 3 is a schematic diagram of the circuit connection of the isolated power supply of the present invention;
FIG. 4 is a schematic diagram of the connection of the analog-to-digital converter circuit of the present invention;
FIG. 5 is a schematic diagram of the planar transformer T1 according to the present invention;
FIG. 6 is a block diagram of an FPGA system of the present invention;
FIG. 7 is a serial output timing sequence of the dual DOUT lines of the interface SPI in the present invention;
FIG. 8 is a schematic diagram of single board function distribution and circuit integration of the multi-channel analog isolation acquisition chip of the present invention;
fig. 9 is a schematic diagram of a stacking structure of a multi-channel analog isolation acquisition chip according to the present invention.
The transformer comprises a first printed board 1, a first printed board 11, a primary winding 2, a second printed board 21, a secondary winding 3, a planar magnetic core 4, a printed board bottom layer 41, a winding fan-out loop 1-1, a first layer circuit board 1-2, a second layer circuit board 1-3, a third layer circuit board 1-4, a bottom board 1-5, a positioning pin 1-6 and a base plate DB board.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the present invention is used, the description is merely for convenience and simplicity, and the indication or suggestion that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, cannot be understood as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
Furthermore, the term "horizontal", if present, does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the embodiments of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The invention is described in further detail below with reference to the accompanying drawings:
the project aims at solving the isolation measurement problem of a plurality of groups of non-common ground analog voltage signals, and provides a multi-channel analog isolation acquisition circuit, which is internally provided with a multi-channel capacitive isolation analog quantity acquisition circuit, a multi-channel micropower isolation power supply and an FPGA system. The PoP process adopts the design idea of space stacking of printed boards, greatly improves the integration level and flexibility of the system, and simultaneously can reduce the design complexity of the whole system, reduce the design risk, reduce the development cost and meet the requirements of a new generation of space equipment. In the traditional analog signal isolation and acquisition system, aiming at different measurement input requirements of users, a targeted customized design is required, the design difficulty is increased, and the risk is promoted. By adopting a PoP technology, a capacitive isolation analog quantity acquisition circuit, an eight-path micropower isolation power supply and an FPGA system are integrated in a module. A user only needs one-way single-power input, and can receive eight-way serial isolated acquisition data through a module standard SPI interface. The design risk is greatly reduced, and the measurement accuracy, the design flexibility and the system testability are improved. The circuit is designed based on a PoP process, the integration level is high, the occupied area of a device is greatly reduced, meanwhile, the risk caused by the traditional complex design is avoided, the universality and the flexibility of the circuit are improved through a digital output interface, and the requirement of isolating and collecting dozens of paths or even hundreds of paths of analog voltage signals can be met in a smaller circuit area.
As shown in fig. 2, a multi-channel analog isolation acquisition circuit includes a multi-channel isolation power supply, i.e., a multi-channel micropower isolation power supply, a multi-channel analog isolation conversion circuit, and an FPGA system; the current output end of the multi-channel isolation power supply is electrically connected with the current input end of the multi-channel analog isolation conversion circuit in a one-to-one correspondence manner; the multi-channel analog isolation conversion circuit is connected with the FPGA system in a DATA transmission mode, and transmitted DATA comprise a clock signal CLK and a DATA signal DATA.
First, for an isolated power supply: the traditional isolation power supply is designed based on a fly-back topology and depends on feedback of a secondary photoelectric coupler, but the size of the photoelectric coupler is large, the thermal stability is not high, and the height of a vertical winding transformer used in cooperation with the photoelectric coupler becomes a main reason for restricting the integration level of a circuit. The winding transformer is usually wound manually, so that the cost is high, consistency among batches cannot be realized, a magnetic circuit is not closed tightly, leakage inductance is large, and electromagnetic interference is easy to generate. Is not favorable for miniaturization and light weight design. The primary side feedback isolation type buck-boost topology is changed into primary side capacitor voltage feedback, the voltage of a primary side output capacitor is kept stable and is used as the excitation voltage of a primary winding of a transformer, and a complex design scheme of output voltage feedback is abandoned. Under the condition of stable input voltage and continuous current, the output voltage of the secondary side is only related to the turn ratio and the load of the transformer, and the topology greatly reduces the complexity of the design.
As shown in fig. 3, the multichannel isolation power supply includes an input decoupling capacitor C1, an under-voltage protection circuit, a driving bootstrap circuit, a chopper circuit, a synchronous Buck controller U1, a planar transformer T1, a primary side feedback loop, and a multichannel output end rectification filter loop; one end of the input decoupling capacitor C1 is connected with the positive end of the input power VIN, and the other end is grounded; the synchronous Buck controller U1 is used for realizing functions of loop compensation, grid synchronous driving, overcurrent protection, over-temperature protection and the like; the undervoltage protection circuit is connected with the positive end of an input power supply VIN and the synchronous Buck controller U1, so that the power supply system is prevented from working when the input voltage is too low; the driving bootstrap circuit is connected with the positive end of an input power supply VIN and the synchronous Buck controller U1 to provide a floating power supply so that the NMOS tube Q1 can be conducted as required; the chopper circuit is connected with the synchronous Buck controller U1 and the planar transformer T1 and is used for converting an input direct-current power supply into an alternating-current pulse power supply; the primary side feedback loop is connected with the planar transformer T1 and the synchronous Buck controller U1; the multi-channel output end rectifying and filtering loop, the planar transformer T1 and the output V OUT And (4) connecting and setting. The input decoupling capacitor C1, the under-voltage protection circuit, the driving bootstrap circuit, the chopper circuit, the synchronous Buck controller U1 and the primary side feedback loop are all primary sides, the planar transformer T1 comprises a primary winding and a plurality of secondary windings, meanwhile, the number of the rectifying and filtering loops of the output end is also a plurality, and the plurality of the rectifying and filtering loops are connected with the plurality of the secondary windings in a one-to-one correspondence manner. More specifically:
(1) the input decoupling capacitor C1 is used for coupling the input voltage V IN Filtering is carried out, and the noise influence of the input voltage is reduced;
(2) the undervoltage protection circuit is used for preventing the power supply system from working when the input voltage is too low, and specifically comprises a resistor R1 and a resistor R2; the resistor R1 and the resistor R2 are connected in series to form a voltage division circuit; the free end of a resistor R1 is connected with the positive end of an input power supply VIN, the free end of a resistor R2 is connected with the virtual ground end GND of the synchronous Buck controller U1, and the voltage dividing ends of the resistor R1 and the resistor R2 are connected with the enabling end EN of the synchronous Buck controller U1.
(3) The driving bootstrap circuit is used for providing a floating power supply to enable the NMOS transistor Q1 to be conducted as required, and specifically comprises a schottky diode D1 and a capacitor C4; the anode of the schottky diode D1 is connected to the positive terminal of the input power VIN; the cathode of the Schottky diode D1 is connected with a bootstrap capacitor pin BST of the synchronous Buck controller; one end of the capacitor C4 is connected with a bootstrap capacitor pin BST of the synchronous Buck controller, and the other end is connected with a switch node SW of the synchronous Buck controller.
(4) As shown in fig. 5, the planar transformer T1 includes a first printed board 1, several layers of second printed boards 2, and a planar magnetic core 3; the first printed board 1 is provided with a primary winding 11, and the plurality of layers of second printed boards 2 are provided with secondary windings 21; the first printed board 1 and the plurality of layers of second printed boards 2 are stacked, the planar magnetic core 3 is inserted into two sides of the stacked first printed board 1 and the plurality of layers of second printed boards 2, the planar magnetic core on one side can be 1/2E-type planar magnetic core, the planar magnetic core on the other side is 1/2I-type planar magnetic core, and the thickness of the stacked printed boards is consistent with the height of the planar magnetic core. The planar transformer T1 further includes a printed board bottom layer 4, and a winding fan-out return wire 41 is disposed on the printed board bottom layer 4. More preferably, the number of second printed boards 2 is preferably eight layers, forming an eight-channel isolated power supply. The planar transformer T1 adopts multilayer printed board winding as the transformer winding, and only the number of layers of printed boards needs to be increased if the number of windings needs to be increased. The planar transformer adopts the flat magnetic core, directly pegs graft in printed board both sides, and printed board thickness and magnetic core height coincide mutually, pile up the back printed board thickness promptly and the highly uniform of planar magnetic core has reduced the power height effectively, does benefit to the design of integrating. The printed board coupling is tight, the leakage inductance is small, the complex process of manual winding of the vertical winding transformer is omitted, batch production is facilitated, and the planar transformer T1 is used for realizing an energy conversion loop in a power conversion circuit.
(5) The chopper circuit is used for converting an input direct-current power supply into an alternating-current pulse power supply and specifically comprises an NMOS (N-channel metal oxide semiconductor) tube Q1 and an NMOS tube Q2; the gate of the NMOS transistor Q1 is connected to the high-voltage on-terminal HO of the synchronous Buck controller U1, the drain of the NMOS transistor Q1 is connected to the positive terminal of the input voltage VIN, and the source of the NMOS transistor Q1 is connected to the drain of the NMOS transistor Q2, the switch node SW of the synchronous Buck controller U1, and the primary winding 11; the gate of the NMOS transistor Q2 is connected to the low-voltage turn-on terminal LO of the synchronous Buck controller, and the source of the NMOS transistor Q2 is connected to the virtual ground terminal GND of the synchronous Buck controller U1.
(6) The primary side feedback loop is used for maintaining the effective excitation voltage of the primary end of the planar transformer T1 unchanged in the chopping process, and specifically comprises a capacitor C2, a capacitor C3, a resistor R3 and a resistor R4; the resistor R3 and the resistor R4 are arranged in series to form a voltage division circuit; the free end of the resistor R3 is connected with the primary winding 11, and the free end of the resistor R4 is connected with a virtual ground end GND of a synchronous Buck controller U1; the voltage dividing ends of the resistor R3 and the resistor R4 are connected with the feedback end FB of the synchronous Buck controller; the capacitor C3 is connected in parallel with the resistor R3, one end of the C3 is connected with the voltage dividing end, and the other end of the C3 is grounded; one end of the capacitor C2 is connected to the primary winding 11, and the other end is connected to the virtual ground GND of the synchronous Buck controller U1.
(7) The multi-channel output end rectifying and filtering loop is used for keeping output stable, and any loop comprises a Schottky diode D3, a magnetic bead MB1, a capacitor C6 and a capacitor C7; the cathode of the schottky diode D3 is connected to one end of the capacitor C6, and two ends of the secondary winding 21 are respectively connected to the anode of the schottky diode D3 and the other end of the capacitor C6; the magnetic bead MB1 is serially connected into an output V OUT The capacitor C7 and the output V OUT Are arranged in parallel.
Secondly, in the isolation acquisition circuit, the traditional optical coupling measurement mode hardly realizes the accurate measurement of the analog signal due to the problems of linearity, temperature drift and the like. The digital signal only has high and low levels, namely the signal of '0' or '1', has strong anti-interference performance in the transmission process, and the digital signal is transmitted on an isolation channel in order to ensure the accuracy of isolation acquisition. Before isolation, a high-frequency digital signal is used as a carrier to modulate a low-frequency analog signal, the modulated digital signal comprises a high-frequency digital carrier signal and a low-frequency analog signal, and lossless isolation transmission can be realized through a digital isolator. And finally, the signals enter the FPGA, and the original analog signals can be recovered through the built low-pass filter which can filter the high-frequency digital carrier signals. Therefore, conversion of the analog signals and the digital signals is realized before isolation, the digital signals are transmitted in an isolation channel in a digital signal form, the phenomena of signal distortion and attenuation do not exist, the design difficulty of the system is simplified, the acquisition precision of the system is improved, and the flexibility and the reliability of the system are improved.
As shown in fig. 2, in the multi-channel capacitive analog-to-digital conversion circuit, each analog-to-digital conversion circuit of a single channel includes a signal conditioning circuit, a voltage-to-digital conversion circuit, and a digital isolator ISO connected in sequence, that is, the signal conditioning circuit is composed of two operational amplifiers, two summing nodes SUM1 and SUM2, two integrators I1 and I2 composed of the operational amplifiers, a hysteresis comparator CMP, a voltage reference VREF, a D flip-flop FILP, and a digital isolator ISO.
As shown in fig. 4, the signal conditioning circuit includes an operational amplifier Op1 and an operational amplifier Op 2; the two operational amplifiers are both designed to be in a following input mode, the following mode has the characteristic of high input impedance and low output impedance, the operational amplifier Op1 realizes the buffering of an analog input signal, the operational amplifier Op2 outputs a virtual ground signal VG, current can be output or absorbed to a certain degree, and the level of the virtual ground signal VG is kept unchanged. The inverting input terminal of the operational amplifier Op1 is connected with the output terminal of the operational amplifier Op1, and the non-inverting input terminal of the operational amplifier Op1 is connected with an input signal; the inverting input terminal of the operational amplifier Op2 and the output terminal of the operational amplifier Op2 are both connected to a virtual ground, and the non-inverting input terminal of the operational amplifier Op2 is connected to the voltage dividing terminal of the voltage dividing circuit of the voltage reference VREF.
The voltage/digital conversion circuit includes a summing node SUM1, a summing node SUM2, an integrator I1, an integrator I2, a hysteresis comparator CMP, a voltage reference VREF, and a flip-flop FILP; a positive input terminal of the summing node SUM1 is connected to the output terminal of the follower Op1, and a negative input terminal of the summing node SUM1 is connected to the result output terminal of the flip-flop FILP; the output of the summing node SUM1 is connected to the input of the integrator I1; the positive input of the summing node SUM2 is connected to the output of the integrator I1, the negative input of the summing node SUM2 is connected to the result output of the flip-flop FILP, and the output of the summing node SUM2 is connected to the input of the integrator I2; the input end of the hysteresis comparator CMP is connected with the output end of the integrator I2, and the output end of the hysteresis comparator CMP is connected with the input D end of the flip-flop FILP; the power supply end VCC of the trigger FILP is connected with a voltage reference VREF;
the summing node SUM1 subtracts the output signal Q of the trigger FILP from the unipolar positive voltage VOUT, that is, subtracts the output signal of the operational amplifier Op1 from the output signal of the trigger FILP, and the obtained result is continuously time-integrated by the integrator I1;
the SUM node SUM2 subtracts the output of the integrator I1 and the output signal Q of the flip-flop FILP, and the obtained result is continuously time-integrated by the integrator I2;
the hysteresis comparator CMP is used to compare the output signal of the integrator I2 with the output virtual ground signal VG of Op2, and outputs a digital quantity "1" when the output signal of the integrator I2 is higher than the virtual ground signal VG and a digital quantity "0" when the output signal of the integrator I2 is lower than the virtual ground signal VG. The comparator is internally provided with a certain hysteresis range so as to reduce the influence of circuit noise;
under the influence of an input clock CLK, the D flip-flop FILP latches the output signal of the hysteresis comparator CMP according to the clock cycle, outputs a digital signal '1' or '0' according to the clock cycle of CLK, has a corresponding analog voltage of '+ VREF' or '0', and is connected to the summing nodes SUM1 and SUM2 to become a system feedback signal;
the digital isolator ISO is a dual-channel capacitive digital isolator, wherein one channel isolates a clock signal CLK and accesses the CLK end of the flip-flop FILP, and the other channel isolates a DATA signal DATA of the flip-flop FILP.
And thirdly, the capacitive isolation analog acquisition circuit outputs high-speed low-bit data stream, and in order to obtain a high-precision output signal, a digital filter is required to filter a noise-shaped high-frequency carrier signal and an input signal outside a bandwidth, and the signal rate can be reduced to the Nyquist frequency. The high-order filter can be easily realized by adopting the digital filter, and the sampling signal after passing through the filter can be directly subjected to subsequent analysis processing in a digital system. And a universal digital interface such as an SPI (serial peripheral interface) is adopted as an output interface of the whole circuit, so that the reliability, the universality and the flexibility of the system are improved. The design of the digital filter and the SPI interface can be easily realized by using a small-package and small-resource FPGA. The FPGA system block diagram is shown in FIG. 6. The FPGA system comprises an FPGA unit, an SPI FLASH unit, a crystal oscillator unit and a digital power supply unit, and provides 1.2V and 3.3V of required numbers for the system. The SPI FLASH unit is connected with the FPGA unit; the crystal oscillator unit is connected with the FPGA unit; the digital power supply unit is connected with the FPGA unit, the SPI FLASH unit and the crystal oscillator unit; the FPGA unit is internally and sequentially connected with a digital filter, a memory FIFO and an interface SPI; the digital filter includes a first stage of decimation, a second stage of decimation, and a third stage of decimation. The first stage is a CIC cascade integral comb filter to realize 32 times of extraction; the second stage is an HBF half-band filter, so that 2-time extraction is realized; the third stage is an FIR filter, which realizes a decimation filter with 2 times reduction. The three-level structure can obviously reduce the operation amount and the memory space of the whole filter, simplify the design of the filter and reduce the finite word length effect. The reduction of the sampling frequency is mainly completed by a first-stage CIC filter, and compared with other filter structures, the CIC filter does not need a multiplier, only needs an adder and a subtracter, and greatly reduces the operation time and resources. The second-stage HBF filter is used for attenuating signal components and quantization noise components which are aliased in a baseband after passing through the first-stage CIC filter. The HBF filter is a special linear phase filter, the coefficient of which is nearly half of zero, and the operation amount is reduced by nearly half with other FIR filters with the same length. The signal frequency is reduced by 64 times through the first two stages of filters, 2 times of downsampling is needed for reducing the Nyquist frequency, and the FIR filter is used as the third stage, so that smaller passband ripple and larger stop band attenuation can be obtained.
The output signal is restored to the Nyquist frequency after passing through the digital decimation filter, the data after eight-channel down-sampling is cached in the FIFO, when the external main equipment accesses the circuit, the cached data can be sent through the SPI interface, and the timing diagram of the double-DOUT serial interface is shown in fig. 7. At the moment, the external FPGA is in a Slave mode, after CS (circuit switching) is pulled low, the DOUTA serially outputs CH1-CH4 sampling values in next 64 clock cycles, and meanwhile, the DOUTB serially outputs CH5-CH8 sampling values in 64 clock cycles.
The multi-channel analog isolation acquisition circuit designed by the invention can input and modulate analog signals into digital signals of '0' and '1', and is isolated by the capacitive digital isolator, so that the analog signals are isolated and converted without distortion and with high precision; meanwhile, the isolated buck-boost power supply topology with primary side feedback and the micropower isolated power supply of the planar transformer are integrated, multi-channel isolated output can be realized only by single power supply input, the design is simple, and the isolated buck-boost power supply topology is very suitable for an isolated signal measuring system; the built-in FPGA system completes the digital extraction and filtering of the modulated signal inside the circuit, and the user may also configure the oversampling ratio via OS 0:2 pin to meet various user's requirement. The signals after extraction and filtering are in serial transmission and strong universality through a double-DOUT line SPI interface, and the use is convenient. The integration is carried out by adopting a PoP process, the integration level of a printed board system is improved to the maximum extent, and the problems of low testability, poor repairability, high process cost and the like caused by adopting a bare chip are solved. Aerospace products based on the PoP technology are greatly verified, and the technology is mature and reliable. The method has the characteristics of miniaturization, high integration degree, high flexibility and the like, and can be widely applied to the fields of aerospace, industrial control and the like.
The invention also discloses a multi-channel analog isolation acquisition chip, which comprises a first layer circuit board 1-1, a second layer circuit board 1-2, a third layer circuit board 1-3 and a bottom board 1-4 which are sequentially stacked and fixedly arranged, as shown in figure 8; the first layer of circuit board 1-1 and the second layer of circuit board 1-2 both include the analog isolation conversion circuit of the present invention, if the size is limited, the circuit boards can be provided in plurality, including a plurality of channel analog isolation conversion circuits. In this embodiment, the first layer circuit board 1-1 and the second layer circuit board 1-2 are both provided with four analog isolation conversion circuits, which can respectively implement input conversion and isolation of four voltages. An eight-channel analog isolation conversion circuit is formed. The third layer of circuit board 1-3 comprises the multi-channel isolation power supply and the FPGA system, and digital signal filtering, an SPI interface and multi-channel isolation power supply output are realized; the bottom plates 1-4 are light plates, so that the bottom surface of the device is smooth and insulated. As shown in FIG. 9, a first layer of circuit board 1-1, a second layer of circuit board 1-2, a third layer of circuit board 1-3 and a bottom board 1-4 are arranged in a stacking mode, accurate positioning is achieved by adopting high-precision positioning holes and positioning pins 1-5, and height between boards is controlled within a safety interval of 0.3-0.5 mm by using customized backing board DB boards 1-6 with different thicknesses. The whole circuit adopts a DIP32 mode to lead out pins.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A multi-channel analog isolation acquisition circuit is characterized by comprising a multi-channel isolation power supply, a multi-channel analog isolation conversion circuit and an FPGA system;
the current output ends of the multi-channel isolation power supply are electrically connected with the current input ends of the multi-channel analog isolation conversion circuit in a one-to-one correspondence manner; the multi-channel analog isolation conversion circuit is connected with the FPGA system in a data transmission way;
the multichannel isolation power supply comprises an input decoupling capacitor C1, an undervoltage protection circuit, a drive bootstrap circuit, a chopper circuit, a synchronous Buck controller U1, a planar transformer T1, a primary side feedback loop and a multichannel output end rectification filter loop;
one end of the input decoupling capacitor C1 is connected with the positive end of an input power supply VIN, and the other end of the input decoupling capacitor C1 is grounded; the undervoltage protection circuit is connected with the positive terminal of an input power VIN and the synchronous Buck controller U1; the driving bootstrap circuit is connected with the positive end of an input power supply VIN and the synchronous Buck controller U1; the chopper circuit is connected with the synchronous Buck controller U1 and the planar transformer T1; the primary side feedback loop is connected with the planar transformer T1 and the synchronous Buck controller U1; the multi-channel output end rectifying and filtering loop, the planar transformer T1 and the output V OUT Connecting and setting;
the analog isolation conversion circuit of any channel in the multi-channel analog isolation conversion circuit comprises a signal conditioning circuit, a voltage/digital conversion circuit and a digital isolator ISO which are sequentially connected.
2. The multi-channel analog isolation acquisition circuit of claim 1, wherein the undervoltage protection circuit comprises a resistor R1 and a resistor R2; the resistor R1 and the resistor R2 are connected in series to form a voltage division circuit; the free end of the resistor R1 is connected with the positive end of an input power supply VIN, the free end of the resistor R2 is connected with the virtual ground end GND of the synchronous Buck controller U1, and the voltage dividing ends of the resistor R1 and the resistor R2 are connected with the enabling end EN of the synchronous Buck controller U1.
3. The multi-channel analog isolation acquisition circuit of claim 1, wherein the driving bootstrap circuit comprises a schottky diode D1 and a capacitor C4; the anode of the Schottky diode D1 is connected with the positive end of an input power supply VIN; the cathode of the Schottky diode D1 is connected with a bootstrap capacitor pin BST of the synchronous Buck controller; one end of the capacitor C4 is connected with a bootstrap capacitor pin BST of the synchronous Buck controller, and the other end of the capacitor C4 is connected with a switch node SW of the synchronous Buck controller.
4. A multichannel analog isolation acquisition circuit according to claim 1, characterized in that said planar transformer T1 comprises a first printed board (1), several layers of second printed boards (2) and a planar magnetic core (3); a primary winding (11) is arranged on the first printed board (1), and secondary windings (21) are arranged on the second printed boards (2); the first printed board (1) and the plurality of layers of second printed boards (2) are stacked, and the planar magnetic core (3) is inserted into two sides of the stacked first printed board (1) and the plurality of layers of second printed boards (2); the thicknesses of the first printed board (1) and the plurality of layers of second printed boards (2) after stacking are consistent with the height of the planar magnetic core (3).
5. The multi-channel analog isolation acquisition circuit of claim 4, wherein the chopper circuit comprises an NMOS transistor Q1 and an NMOS transistor Q2; the grid electrode of the NMOS tube Q1 is connected with a high-voltage opening end HO of the synchronous Buck controller U1, the drain electrode of the NMOS tube Q1 is connected with the positive end of an input voltage VIN, and the source electrode of the NMOS tube Q1 is connected with the drain electrode of the NMOS tube Q2, the switch node SW of the synchronous Buck controller U1 and the primary winding (11); the grid electrode of the NMOS tube Q2 is connected with the low-voltage starting end LO of the synchronous Buck controller, and the source electrode of the NMOS tube Q2 is connected with the virtual ground end GND of the synchronous Buck controller U1.
6. The multi-channel analog isolation acquisition circuit of claim 4, wherein the primary feedback loop comprises a capacitor C2, a capacitor C3, a resistor R3, and a resistor R4; the resistor R3 and the resistor R4 are arranged in series to form a voltage division circuit; the free end of the resistor R3 is connected with the primary winding (11), and the free end of the resistor R4 is connected with a virtual ground end GND of a synchronous Buck controller U1; the voltage dividing ends of the resistor R3 and the resistor R4 are connected with the feedback end FB of the synchronous Buck controller; the capacitor C3 is connected in parallel with the resistor R3, one end of the C3 is connected with the voltage division ends of the resistor R3 and the resistor R4, and the other end of the C3 is grounded; one end of the capacitor C2 is connected with the primary winding (11), and the other end is connected with a virtual ground end GND of the synchronous Buck controller U1.
7. The multi-channel analog isolation acquisition circuit of claim 4, wherein any one of the multi-channel output rectifying and filtering circuits comprises a Schottky diode D3, a magnetic bead MB1, a capacitor C6 and a capacitor C7; the cathode of the Schottky diode D3 is connected with one end of the capacitor C6, and two ends of the secondary winding (21) are respectively connected with the anode of the Schottky diode D3 and the other end of the capacitor C6; the magnetic bead MB1 is serially connected into an output V OUT The capacitor C7 and the output V OUT Are arranged in parallel.
8. The multi-channel analog isolation acquisition circuit of claim 1, wherein the signal conditioning circuit comprises an operational amplifier Op1 and an operational amplifier Op 2; the inverting input terminal of the operational amplifier Op1 is connected with the output terminal of the operational amplifier Op1, and the non-inverting input terminal of the operational amplifier Op1 is connected with an input signal; the inverting input terminal of the operational amplifier Op2 and the output terminal of the operational amplifier Op2 are both connected to a virtual ground, and the non-inverting input terminal of the operational amplifier Op2 is connected to the voltage dividing terminal of the voltage dividing circuit of the voltage reference VREF.
9. The multi-channel analog isolation acquisition circuit of claim 8, wherein the voltage/digital conversion circuit comprises a summing node SUM1, a summing node SUM2, an integrator I1, an integrator I2, a hysteresis comparator CMP, a voltage reference VREF, and a flip-flop FILP; a positive input terminal of the summing node SUM1 is connected to the output terminal of the follower Op1, and a negative input terminal of the summing node SUM1 is connected to the result output terminal of the flip-flop FILP; the output of the summing node SUM1 is connected to the input of the integrator I1; the positive input of the summing node SUM2 is connected to the output of the integrator I1, the negative input of the summing node SUM2 is connected to the result output of the flip-flop FILP, and the output of the summing node SUM2 is connected to the input of the integrator I2; the input end of the hysteresis comparator CMP is connected with the output end of the integrator I2, and the output end of the hysteresis comparator CMP is connected with the input D end of the flip-flop FILP; the power supply end VCC of the trigger FILP is connected with a voltage reference VREF;
one lane of the digital isolator ISO isolates the clock signal CLK and accesses the CLK end of the flip-flop FILP, and the other lane isolates the DATA signal DATA of the flip-flop FILP.
10. A multi-channel analog isolation acquisition chip is characterized by comprising a first layer circuit board (1-1), a second layer circuit board (1-2), a third layer circuit board (1-3) and a bottom board (1-4) which are sequentially stacked and fixedly arranged;
the first layer circuit board (1-1) and the second layer circuit board (1-2) both comprise the analog isolation conversion circuit as claimed in claim 1;
the third layer of circuit board (1-3) comprises a multi-channel isolation power supply and an FPGA system as described in claim 1;
the distance between the first layer of circuit board (1-1), the second layer of circuit board (1-2), the third layer of circuit board (1-3) and the bottom board (1-4) is 0.3-0.5 mm.
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