CN114839501A - Efficient test system and method for turn-off voltage of junction field effect transistor - Google Patents
Efficient test system and method for turn-off voltage of junction field effect transistor Download PDFInfo
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- CN114839501A CN114839501A CN202210777944.4A CN202210777944A CN114839501A CN 114839501 A CN114839501 A CN 114839501A CN 202210777944 A CN202210777944 A CN 202210777944A CN 114839501 A CN114839501 A CN 114839501A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The invention discloses a high-efficiency test system and a method for the turn-off voltage of a junction field effect transistor, which comprises a reverse addition operation circuit U1, a reverse amplification operation circuit U2, an integral operation circuit U3, a reverse amplification circuit U4, a Fei' an level offset current buffer operational amplifier circuit U5, a sampling resistor RX and three GND output ports.
Description
Technical Field
The invention relates to a system and a method for efficiently testing the turn-off voltage of a junction field effect transistor, belonging to the field of discrete device testing.
Background
Currently, the VGS-ID curve is drawn by a sequential scanning method in the industry to obtain the turn-off voltage (VGS (off)). This method requires multiple measurements, successively increasing the value of VGS until its off voltage value is obtained. The method has the disadvantages that repeated tests are needed for many times until an accurate closing voltage value is obtained, the operation is complicated, and the efficiency is low.
Disclosure of Invention
The purpose of the invention is as follows: in order to overcome the defects in the prior art, the invention provides the system and the method for efficiently testing the turn-off voltage of the junction field effect transistor.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:
the utility model provides a high-efficient test system of JFET turn-off voltage, includes inverse addition operational circuit U1, inverse amplification operational circuit U2, integral operation circuit U3, inverse amplification circuit U4, the flying ampere level offset current buffering operational amplifier circuit U5, sampling resistor RX, output port three GND, wherein:
the inverse addition operational circuit U1 includes a resistor three R3, a capacitor one C1, and a first operational amplifier, wherein the non-inverting input terminal of the first operational amplifier is grounded through a resistor one R1, and the inverting input terminal of the first operational amplifier is connected to the signal input port one VID through a resistor two R2. The resistor three R3 has one end connected to the inverting input terminal of the first operational amplifier and the other end connected to the output terminal of the first operational amplifier, and the capacitor one C1 has one end connected to the inverting input terminal of the first operational amplifier and the other end connected to the output terminal of the first operational amplifier.
The inverting amplification operational circuit U2 comprises a resistor five R5, a capacitor two C2 and a second operational amplifier, wherein the non-inverting input end of the second operational amplifier is grounded through a resistor six R6, one end of the resistor five R5 is connected to the inverting input end of the second operational amplifier, the other end of the resistor five R5 is connected to the output end of the second operational amplifier, one end of the capacitor two C2 is connected to the inverting input end of the second operational amplifier, the other end of the capacitor two C2 is connected to the output end of the second operational amplifier, and the output end of the second operational amplifier is connected with the inverting input end of the first operational amplifier through a resistor four R4.
The integral operational circuit U3 comprises a capacitor two C3 and a third operational amplifier, wherein the non-inverting input end of the third operational amplifier is grounded through a resistor ten R10, the inverting input end of the third operational amplifier is connected with the signal input port two VDS through a resistor fifteen R15, one end of a capacitor two C35 is connected to the inverting input end of the third operational amplifier, the other end of the capacitor two C35 is connected to the output end of the third operational amplifier, and the output end of the third operational amplifier is connected with the signal output port two VGS through a resistor sixteen R16.
The inverting amplifying circuit U4 includes a resistor twelve R12 and a fourth operational amplifier, one end of the resistor twelve R12 is connected to the inverting input terminal of the fourth operational amplifier, the other end of the resistor twelve R12 is connected to the output terminal of the fourth operational amplifier, the non-inverting input terminal of the fourth operational amplifier is grounded through a resistor thirteen R13, and the inverting input terminal of the fourth operational amplifier is connected to the output terminal of the third operational amplifier through a resistor eleven R11. And the output end of the fourth operational amplifier is connected with the second output port VG.
The Feian level offset current buffer operational amplifier circuit U5 comprises a resistor seventeen R17 and a Feian level input offset current buffer operational amplifier, wherein the non-inverting input end of the Feian level input offset current buffer operational amplifier is connected with an output port VD through a resistor fourteen R14, one end of the resistor seventeen R17 is connected to the inverting input end of the Feian level input offset current buffer operational amplifier, and the other end of the resistor seventeen R17 is connected to the output end of the Feian level input offset current buffer operational amplifier. The output end of the FeiAN level input offset current buffer operational amplifier is connected with the inverting input end of the second operational amplifier through a resistor seven R7, and the output end of the FeiAN level input offset current buffer operational amplifier is connected with the inverting input end of the third operational amplifier through a resistor eight R8.
The output port three GND is grounded, one end of the sampling resistor RX is connected with the output port one VD, and the other end of the sampling resistor RX is connected with the output end of the first operational amplifier.
A drain electrode of a device Q to be tested is connected with an output port I VD, a grid electrode of the device Q to be tested is connected with an output port II VG, and a source electrode of the device Q to be tested is connected with an output port III GND. The power supply input is provided through a signal input port VID, the power supply input reaches the drain electrode of the device Q to be tested through an inverse addition operation circuit U1 and a sampling resistor RX, the voltage of the drain electrode of the device Q to be tested is collected by a flying-amp-level offset current buffer operational amplifier circuit U5 and compensated to the input ends of an inverse amplification operation circuit U2 and an integral operation circuit U3 through an inverse amplification operation circuit U2, therefore, the voltage of the input port VID is loaded to two ends of the sampling resistor RX, the current value passing through the sampling resistor RX is calculated according to ohm's law, and the current flowing through the sampling resistor RX flows into the device Q to be tested completely. The signal input port two VDS provides the drain-source voltage needed by the tested device.
Preferably: when the circuit is powered on, the ID current is small and is in nA level, so that the output voltage of the output port I VD slowly rises, and the direction is opposite to the direction of the voltage provided by the signal input port II VDS. The output voltage of the integral operation circuit U3 rapidly rises under the action of the input voltage of the signal input port two VDS until the input voltage is fully biased. When the output voltage of the first output port VD is larger than the output voltage of the second VDS of the signal input port, the direction of the reverse input voltage of the integral operation circuit U3 is changed, so that the output voltage of the operational amplifier starts to be reduced, when the voltage is reduced to the value of the output voltage of the tested device Q and just conducts, the resistance value of a drain electrode and a source electrode channel of the tested device Q is reduced, so that the output voltage of the first output port VD is reduced, the output voltage of the first output port VD is finally equal to the output voltage of the second VDS of the signal input port, balance is achieved, the reverse input end of the integral operation circuit U3 is zero-input at the moment, the output end is kept unchanged, and the output voltage of the integral operation circuit U3 is the conducting voltage of the tested device Q at the moment, and the directions are opposite.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention adopts the ingenious combination design of four high-precision operational amplifiers and one flying-safety-level input offset current buffer operational amplifier, and realizes the rapid test of the turn-off voltage VGS (off) of the JFET.
2. The flying-ampere-level input offset current buffer operational amplifier is used as a follow-up acquisition operational amplifier of VD (voltage-division) voltage, and can accurately acquire the VD voltage while neglecting the current influence in the original circuit.
3. By using the input and output characteristics of the integral operational amplifier and based on the characteristic of circuit balance, VD voltage acquisition is skillfully used as compensation, and VGS (th) accurate measurement is realized.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of the present invention.
FIG. 2 is a circuit diagram of an embodiment of the present invention.
FIG. 3 is a flowchart of an embodiment of the present invention.
Fig. 4 is a Multisim simulation waveform diagram.
Detailed Description
The present invention is further illustrated by the following description in conjunction with the accompanying drawings and the specific embodiments, it is to be understood that these examples are given solely for the purpose of illustration and are not intended as a definition of the limits of the invention, since various equivalent modifications will occur to those skilled in the art upon reading the present invention and fall within the limits of the appended claims.
A high-efficiency test system for the turn-off voltage of a junction field effect transistor is disclosed, as shown in figure 1, the system provides two signal input ports VID and VDS to realize the provision of test conditions, three output ports VD, VG and GND are used for connecting a tested device, and one test port is used for converting and outputting a test value. VID provides the current slew value required by the device under test, and VDS provides the drain-source voltage required to measure VGS (off). As shown in fig. 2, the integrated circuit includes an inverse addition operation circuit U1, an inverse amplification operation circuit U2, an integration operation circuit U3, an inverse amplification circuit U4, a flying-ampere-level offset current buffer operational amplifier circuit U5, a sampling resistor RX, and an output port three GND, where:
the inverse addition operational circuit U1 includes a resistor three R3, a capacitor one C1, and a first operational amplifier, wherein the non-inverting input terminal of the first operational amplifier is grounded through a resistor one R1, and the inverting input terminal of the first operational amplifier is connected to the signal input port one VID through a resistor two R2. The resistor three R3 has one end connected to the inverting input terminal of the first operational amplifier and the other end connected to the output terminal of the first operational amplifier, and the capacitor one C1 has one end connected to the inverting input terminal of the first operational amplifier and the other end connected to the output terminal of the first operational amplifier.
The inverting amplification operational circuit U2 comprises a resistor five R5, a capacitor two C2 and a second operational amplifier, wherein the non-inverting input end of the second operational amplifier is grounded through a resistor six R6, one end of the resistor five R5 is connected to the inverting input end of the second operational amplifier, the other end of the resistor five R5 is connected to the output end of the second operational amplifier, one end of the capacitor two C2 is connected to the inverting input end of the second operational amplifier, the other end of the capacitor two C2 is connected to the output end of the second operational amplifier, and the output end of the second operational amplifier is connected with the inverting input end of the first operational amplifier through a resistor four R4.
The integral operational circuit U3 comprises a capacitor two C3 and a third operational amplifier, wherein the non-inverting input end of the third operational amplifier is grounded through a resistor ten R10, the inverting input end of the third operational amplifier is connected with the signal input port two VDS through a resistor fifteen R15, one end of a capacitor two C35 is connected to the inverting input end of the third operational amplifier, the other end of the capacitor two C35 is connected to the output end of the third operational amplifier, and the output end of the third operational amplifier is connected with the signal output port two VGS through a resistor sixteen R16.
The inverting amplifying circuit U4 includes a resistor twelve R12 and a fourth operational amplifier, one end of the resistor twelve R12 is connected to the inverting input terminal of the fourth operational amplifier, the other end of the resistor twelve R12 is connected to the output terminal of the fourth operational amplifier, the non-inverting input terminal of the fourth operational amplifier is grounded through a resistor thirteen R13, and the inverting input terminal of the fourth operational amplifier is connected to the output terminal of the third operational amplifier through a resistor eleven R11. And the output end of the fourth operational amplifier is connected with the second output port VG.
The Feian level offset current buffer operational amplifier circuit U5 comprises a resistor seventeen R17 and a Feian level input offset current buffer operational amplifier, wherein the non-inverting input end of the Feian level input offset current buffer operational amplifier is connected with an output port VD through a resistor fourteen R14, one end of the resistor seventeen R17 is connected to the inverting input end of the Feian level input offset current buffer operational amplifier, and the other end of the resistor seventeen R17 is connected to the output end of the Feian level input offset current buffer operational amplifier. The output end of the FeiAN level input offset current buffer operational amplifier is connected with the inverting input end of the second operational amplifier through a resistor seven R7, and the output end of the FeiAN level input offset current buffer operational amplifier is connected with the inverting input end of the third operational amplifier through a resistor eight R8. The voltage of a VD (voltage divider) at an output port is collected by the Fei-level offset current buffer operational amplifier circuit U5 and is supplied to the input ends of the inverse amplification operation circuit U2 and the integral operation circuit U3.
The output port three GND is grounded, one end of the sampling resistor RX is connected with the output port one VD, and the other end of the sampling resistor RX is connected with the output end of the first operational amplifier.
A drain electrode of a device Q to be tested is connected with an output port I VD, a grid electrode of the device Q to be tested is connected with an output port II VG, and a source electrode of the device Q to be tested is connected with an output port III GND. The power supply input is provided through a signal input port VID, the power supply input reaches the drain electrode of the device Q to be tested through an inverse addition operation circuit U1 and a sampling resistor RX, the voltage of the drain electrode of the device Q to be tested is collected by a FeiAmp level offset current buffer operational amplifier circuit U5 and compensated to the input port VID through an inverse amplification operation circuit U2, therefore, the input port VID is loaded to two ends of the sampling resistor RX, the current value passing through the sampling resistor RX is calculated according to ohm law, the voltage is collected only by the FeiAmp level offset current buffer operational amplifier circuit U5, the influence on the circuit current can be ignored, and therefore, the current flowing through the sampling resistor RX flows into the device Q to be tested completely. The signal input port two VDS provides the drain-source voltage needed by the tested device.
As shown in fig. 3, taking JFET-N as an example, when the circuit is powered on, since the ID current is small and is in the nA level, the output voltage of the output port one VD slowly rises in the direction opposite to the direction of the voltage supplied by the signal input port two VDs. The output voltage of the integral operation circuit U3 rises rapidly under the action of the input voltage of the signal input port two VDS until the voltage is fully biased (a voltage stabilizing diode protection operational amplifier is added in an actual circuit). When the output voltage of the first output port VD is larger than the output voltage of the second VDS of the signal input port, the direction of the reverse input voltage of the integral operation circuit U3 is changed, so that the output voltage of the operational amplifier starts to be reduced, when the voltage is reduced to the value of the output voltage of the tested device Q and just conducts, the resistance value of a drain electrode and a source electrode channel of the tested device Q is reduced, so that the output voltage of the first output port VD is reduced, the output voltage of the first output port VD is finally equal to the output voltage of the second VDS of the signal input port, balance is achieved, the reverse input end of the integral operation circuit U3 is zero-input at the moment, the output end is kept unchanged, and the output voltage of the integral operation circuit U3 is the conducting voltage of the tested device Q at the moment, and the directions are opposite.
As shown in fig. 4, the output waveforms of VD and U3 are Multisim simulations and substantially match the theoretical output.
The invention can realize the measurement of the VGS (off) value of the junction field effect transistor, and compared with the traditional scanning measurement mode, the invention improves the test efficiency and reduces the test cost.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (3)
1. The utility model provides a high-efficient test system of JFET turn-off voltage which characterized in that: the high-voltage integrated circuit comprises an inverse addition operation circuit U1, an inverse amplification operation circuit U2, an integral operation circuit U3, an inverse amplification circuit U4, a Fei' an level offset current buffer operational amplifier circuit U5, a sampling resistor RX and an output port three GND, wherein:
the reverse addition operational circuit U1 comprises a resistor three R3, a capacitor one C1 and a first operational amplifier, wherein the non-inverting input end of the first operational amplifier is grounded through a resistor one R1, and the inverting input end of the first operational amplifier is connected with a signal input port one VID through a resistor two R2; the third resistor R3 has one end connected to the inverting input end of the first operational amplifier and the other end connected to the output end of the first operational amplifier, and the first capacitor C1 has one end connected to the inverting input end of the first operational amplifier and the other end connected to the output end of the first operational amplifier;
the inverting amplification operational circuit U2 comprises a resistor five R5, a capacitor two C2 and a second operational amplifier, wherein the non-inverting input end of the second operational amplifier is grounded through a resistor six R6, one end of the resistor five R5 is connected to the inverting input end of the second operational amplifier, the other end of the resistor five R5 is connected to the output end of the second operational amplifier, one end of the capacitor two C2 is connected to the inverting input end of the second operational amplifier, the other end of the capacitor two C2 is connected to the output end of the second operational amplifier, and the output end of the second operational amplifier is connected with the inverting input end of the first operational amplifier through a resistor four R4;
the integral operational circuit U3 comprises a capacitor II C3 and a third operational amplifier, wherein the non-inverting input end of the third operational amplifier is grounded through a resistor decaR 10, the inverting input end of the third operational amplifier is connected with the signal input port II VDS through a resistor pentadR 15, one end of the capacitor II C35 is connected with the inverting input end of the third operational amplifier, the other end of the capacitor II C35 is connected with the output end of the third operational amplifier, and the output end of the third operational amplifier is connected with the signal output port II VGS through a resistor sixteen R16;
the inverting amplifying circuit U4 comprises a resistor twelve R12 and a fourth operational amplifier, wherein one end of the resistor twelve R12 is connected to the inverting input end of the fourth operational amplifier, the other end of the resistor twelve R12 is connected to the output end of the fourth operational amplifier, the non-inverting input end of the fourth operational amplifier is grounded through a resistor thirteen R13, and the inverting input end of the fourth operational amplifier is connected with the output end of the third operational amplifier through a resistor eleven R11; the output end of the fourth operational amplifier is connected with the second output port VG;
the Feampere-grade offset current buffer operational amplifier circuit U5 comprises a resistor seventeen R17 and a Feampere-grade input offset current buffer operational amplifier, wherein the non-inverting input end of the Feampere-grade input offset current buffer operational amplifier is connected with a VD (voltage drop) output port through a resistor fourteen R14, one end of a resistor seventeen R17 is connected to the inverting input end of the Feampere-grade input offset current buffer operational amplifier, and the other end of the resistor seventeen R17 is connected to the output end of the Feampere-grade input offset current buffer operational amplifier; the output end of the FeiAN level input offset current buffer operational amplifier is connected with the inverting input end of the second operational amplifier through a resistor seven R7, and the output end of the FeiAN level input offset current buffer operational amplifier is connected with the inverting input end of the third operational amplifier through a resistor eight R8;
the output port three GND is grounded, one end of the sampling resistor RX is connected with the output port one VD, and the other end of the sampling resistor RX is connected with the output end of the first operational amplifier.
2. A test method applied to the efficient test system of the junction field effect transistor turn-off voltage of the junction field effect transistor in the claim 1 is characterized in that: the drain of the device Q to be tested is connected with the first output port VD, the grid of the device Q to be tested is connected with the second output port VG, and the source of the device Q to be tested is connected with the third output port GND; the power supply input is provided through a signal input port VID, the power supply input reaches the drain electrode of the device Q to be tested through an inverse addition operation circuit U1 and a sampling resistor RX, the voltage of the drain electrode of the device Q to be tested is collected by a flying-ampere level offset current buffer operational amplifier circuit U5, and is compensated to the input ends of an inverse amplification operation circuit U2 and an integral operation circuit U3 through an inverse amplification operation circuit U2, so that the voltage of the input port VID is loaded to the two ends of the sampling resistor RX, the current value passing through the sampling resistor RX is calculated according to ohm's law, and the current flowing through the sampling resistor RX flows into the device Q to be tested; the signal input port two VDS provides the drain-source voltage needed by the tested device.
3. The test method of claim 2, wherein: when the circuit is electrified, because the ID current is small and is at the nA level, the output voltage of the output port I VD slowly climbs, and the direction is opposite to the voltage provided by the signal input port II VDS; the output voltage of the integral operation circuit U3 rapidly rises under the action of the input voltage of the second VDS of the signal input port until the input voltage is fully biased; when the output voltage of the first output port VD is larger than the output voltage of the second VDS of the signal input port, the direction of the reverse input voltage of the integral operation circuit U3 is changed, so that the output voltage of the operational amplifier starts to be reduced, when the voltage is reduced to the value of the output voltage of the tested device Q and just conducts, the resistance value of a drain electrode and a source electrode channel of the tested device Q is reduced, so that the output voltage of the first output port VD is reduced, the output voltage of the first output port VD is finally equal to the output voltage of the second VDS of the signal input port, balance is achieved, the reverse input end of the integral operation circuit U3 is zero-input at the moment, the output end is kept unchanged, and the output voltage of the integral operation circuit U3 is the conducting voltage of the tested device Q at the moment, and the directions are opposite.
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