CN114827088A - Address assignment system, method, electronic device, storage medium, and program product - Google Patents
Address assignment system, method, electronic device, storage medium, and program product Download PDFInfo
- Publication number
- CN114827088A CN114827088A CN202210294559.4A CN202210294559A CN114827088A CN 114827088 A CN114827088 A CN 114827088A CN 202210294559 A CN202210294559 A CN 202210294559A CN 114827088 A CN114827088 A CN 114827088A
- Authority
- CN
- China
- Prior art keywords
- inspection
- address
- slave
- machine
- inspection slave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000007689 inspection Methods 0.000 claims abstract description 250
- 238000004891 communication Methods 0.000 claims abstract description 62
- 230000005540 biological transmission Effects 0.000 claims abstract description 6
- 238000004590 computer program Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
- H04L12/40176—Flexible bus arrangements involving redundancy
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention relates to the technical field of battery management, and discloses an address allocation system, an address allocation method, electronic equipment, a storage medium and a program product, which can automatically allocate addresses in sequence. The system comprises an inspection host and a plurality of inspection slave machines, wherein the inspection host is provided with a first address output interface and a first address input interface; the inspection slave machine is provided with a second address input interface and a second address output interface; the first address output interface is electrically connected with the second address input interface of the first inspection slave, the first address input interface is electrically connected with the second address output interface of the last inspection slave, and the second address output interface of the previous inspection slave is electrically connected with the second address input interface of the next inspection slave. When the communication addresses of the inspection slave machines are distributed, the communication addresses of the inspection slave machines are set according to the physical sequence by combining the accumulated transmission of the pulse signal pulse number, so that the distribution efficiency, the accuracy and the reliability of the communication addresses are effectively improved.
Description
Technical Field
The present invention relates to the field of battery management technologies, and in particular, to an address assignment system, method, electronic device, storage medium, and program product.
Background
The storage battery is used as a reliable uninterrupted power supply, is widely applied to power operation power supplies and communication power supply systems, and ensures that the whole system can work reliably without interruption, so that in order to ensure the reliable work of the storage battery, the storage battery needs to be inspected in real time, and parameters such as voltage, internal resistance, temperature and the like of a single battery are detected, so that a fault battery can be found in advance, the potential fault hazard can be eliminated, and the reliability of the whole system can be improved. The general battery inspection system comprises an inspection host and a plurality of inspection slave machines, wherein the inspection host is in communication connection with each inspection slave machine, so that a unique sequential address needs to be distributed to each inspection slave machine and is in one-to-one correspondence with the battery sequence, and the normal communication between the host and the units and the accuracy of battery data are ensured.
Two common address allocation methods are currently used:
1. selecting and matching addresses by using a dial switch: each inspection slave is provided with a multi-bit dial switch, and addresses are sequentially distributed to each inspection slave by setting different states of the dial switches, so that the addresses of the inspection slaves are ensured to be in one-to-one correspondence with the physical sequence of the batteries. The method is simple and easy to implement, and has the defects that addresses need to be set manually, and the number of the routing inspection slave machines is usually hundreds, so that the workload is large and errors are easy to occur; moreover, the dial switch is in mechanical contact, so that poor contact is easy to occur after a long time, and communication faults are caused.
2. The solidified addresses are distributed to each inspection slave in advance in sequence, and the inspection slave and each battery are required to be installed in a one-to-one pairing mode in sequence during engineering installation, so that the workload is increased, and errors are easy to occur; when the inspection slave machine breaks down, the units with the same address need to be replaced, spare parts cannot be prepared in advance, timely replacement is difficult to achieve, and the difficulty of system maintenance is increased.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides an address allocation system which can automatically allocate addresses in sequence and improve the efficiency of address allocation.
The invention also provides an address allocation method applied to the address allocation system.
On one hand, the address distribution system comprises an inspection host and a plurality of inspection slave machines which are electrically connected in sequence, wherein the inspection host is provided with a first address output interface and a first address input interface; each inspection slave machine is provided with a second address output interface and a second address input interface; the first address output interface is electrically connected with the second address input interface of the first inspection slave, the first address input interface is electrically connected with the second address output interface of the last inspection slave, and the second address output interface of the previous inspection slave is electrically connected with the second address input interface of the next inspection slave.
According to some embodiments of the invention, the inspection master is further provided with a first communication interface, each inspection slave is provided with a second communication interface, and the first communication interface is electrically connected with each second communication interface.
According to some embodiments of the present invention, one of an RS485 bus, an RS-422 bus or a CAN bus is used for communication transmission between the first communication interface and the second communication interface.
Another aspect of the embodiments of the present invention provides an address allocation method, applied to the address allocation system described above, including:
determining the number of the inspection slave machines needing address allocation as a first numerical value, inputting the first numerical value to the inspection host machine, and sending 1 pulse signal to the first inspection slave machine by the inspection host machine;
updating the communication address of the inspection slave to be A according to the number A of the pulse signals received by the inspection slave, and sending A +1 pulse signals to the next inspection slave;
and determining the number of the pulse signals sent by the last routing inspection slave machine as B, and comparing B with the first numerical value to judge whether the address allocation is successful or wrong.
According to some embodiments of the present invention, the determining that the number of the pulse signals sent by the last patrol slave is B, comparing B with the first value, and determining that address allocation is complete or an error, includes:
and judging whether the B is equal to the first numerical value plus 1, if so, judging that the address allocation is successful, and if not, judging that the address allocation is failed.
According to some embodiments of the invention, upon determining an address allocation error, the following steps are performed:
electrically connecting the second address output interface of the inspection slave in the middle with the first address input interface;
and returning to the step that the number of the routing inspection slave machines which need to be allocated with addresses is determined to be a first numerical value, inputting the first numerical value to the routing inspection master machine, and sending 1 pulse signal to the first routing inspection slave machine by the routing inspection master machine.
According to some embodiments of the invention, upon determining an address allocation error, the following steps are performed:
electrically connecting the second address input interface of the inspection slave in the middle with the first address output interface;
and returning to the step that the number of the routing inspection slave machines which need to be allocated with addresses is determined to be a first numerical value, inputting the first numerical value to the routing inspection master machine, and sending 1 pulse signal to the first routing inspection slave machine by the routing inspection master machine.
Another aspect of the embodiments of the present invention provides an electronic device, including a processor and a memory;
the memory is used for storing programs;
the processor executes the program to implement the address assignment method as described above.
In another aspect of the embodiments of the present invention, the embodiments of the present invention further provide a computer-readable storage medium, where the storage medium stores a program, and the program is executed by a processor to implement the address allocation method described above.
Embodiments of the present invention also disclose a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The computer instructions may be read by a processor of a computer device from a computer-readable storage medium, and the computer instructions executed by the processor cause the computer device to perform the foregoing address assignment method.
The embodiment of the invention at least comprises the following beneficial effects: when the communication addresses of the inspection slave machines are distributed, the communication addresses of the inspection slave machines are set according to the physical sequence of the inspection slave machines by combining the accumulated transmission mode of the pulse signal pulse number, the cable connection operation and the address distribution process are simplified, and the distribution efficiency, the accuracy and the reliability of the communication addresses are effectively improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a diagram of an address assignment system according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating an address allocation method according to a first embodiment of the present invention;
FIG. 3 is a flowchart illustrating an address allocation method according to a second embodiment of the present invention;
fig. 4 is a flowchart illustrating an address allocation method according to a third embodiment of the present invention.
Reference numerals: the patrol master 100, the first address output interface 110, the first address input interface 120, the first communication interface 130, the patrol slave 200, the second address input interface 220, the second address output interface 210 and the second communication interface 230.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Before further detailed description of the embodiments of the present invention, terms and expressions mentioned in the embodiments of the present invention are explained, and the terms and expressions mentioned in the embodiments of the present invention are applicable to the following explanations:
aiming at the problem of low battery management address allocation efficiency in the related technology, the embodiment of the invention provides an address allocation system, an address allocation method, electronic equipment, a storage medium and a program product.
On one hand, referring to fig. 1, the address allocation system according to the embodiment of the present invention includes an inspection master 100 and a plurality of inspection slaves 200 electrically connected in sequence, wherein the inspection master 100 has a first address output interface 110 and a first address input interface 120; each patrol slave 200 has a second address output interface 210 and a second address input interface 220; the first address output interface 110 is electrically connected to the second address input interface 220 of the first patrol inspection slave 200, the first address input interface 120 is electrically connected to the second address output interface 210 of the last patrol inspection slave 200, and the second address output interface 210 of the previous patrol inspection slave 200 is electrically connected to the second address input interface 220 of the next patrol inspection slave 200.
In some embodiments of the present invention, the inspection master 100 further has a first communication interface 130, each inspection slave 200 has a second communication interface 230, and the first communication interface 130 is electrically connected to each second communication interface 230.
In some embodiments of the present invention, one of an RS485 bus, an RS-422 bus or a CAN bus is used for communication transmission between the first communication interface 130 and the second communication interface 230. And selecting a corresponding communication bus protocol according to the communication requirement.
As shown in fig. 1, the inspection master 100 has one inspection slave 200, the number of the inspection slave 200 is N, the first address output interface 110 is electrically connected to the second address input interface 220 of the first inspection slave 200, the first address input interface 120 is electrically connected to the second address output interface 210 of the last inspection slave 200, and the N inspection slaves 200 are electrically connected in sequence, that is, the second address output interface 210 of the previous inspection slave 200 is electrically connected to the second address input interface 220 of the next inspection slave 200, wherein the number of batteries is matched with the number of the inspection slaves 200.
Another aspect of the embodiments of the present invention provides a first address allocation method, applied to the foregoing address allocation system, including:
s100, determining the number of the inspection slave machines 200 needing to be allocated with addresses as a first numerical value, inputting the first numerical value into the inspection master machine 100, and sending 1 pulse signal to the first inspection slave machine 200 by the inspection master machine 100; with reference to the embodiment of fig. 1, it is determined that the current first value is N, the address allocation number N is input to the inspection master 100, and the inspection master 100 sends 1 pulse signal to the first inspection slave 200;
s200, updating the communication address of the inspection slave machine 200 to A according to the number A of the pulse signals received by the inspection slave machine 200, and sending A +1 pulse signals to the next inspection slave machine 200; that is, the first inspection slave device 200 receives 1 pulse signal, the communication address of the first inspection slave device 200 is updated to 1, and 2 pulse signals are sent to the second inspection slave device 200; when the second inspection slave machine 200 receives 2 pulse signals, the communication address of the second inspection slave machine 200 is updated to 2, and 3 pulse signals are sent to the third inspection slave machine 200; the inspection slave 200 sequentially executes the steps until the nth inspection slave 200 receives the N pulse signals, the communication address of the nth inspection slave 200 is updated to N, and N +1 pulse signals are sent to the inspection master 100;
s300, determining the number of the pulse signals sent by the last inspection slave machine 200 as B, and comparing B with a first numerical value to judge whether the address allocation is successful or wrong; in this embodiment, when the patrol inspection host 100 receives N +1 pulse signals, it determines that address allocation is successful.
Another aspect of the embodiments of the present invention provides a second address allocation method, which is applied to the foregoing address allocation system, and includes:
s100, determining the number of the inspection slave machines 200 needing to be allocated with addresses as a first numerical value, inputting the first numerical value into the inspection master machine 100, and sending 1 pulse signal to the first inspection slave machine 200 by the inspection master machine 100; with reference to the embodiment of fig. 1, it is determined that the current first value is N, the address allocation number N is input to the inspection master 100, and the inspection master 100 sends 1 pulse signal to the first inspection slave 200;
s200, updating the communication address of the inspection slave machine 200 to A according to the number A of the pulse signals received by the inspection slave machine 200, and sending A +1 pulse signals to the next inspection slave machine 200; that is, the first inspection slave device 200 receives 1 pulse signal, the communication address of the first inspection slave device 200 is updated to 1, and 2 pulse signals are sent to the second inspection slave device 200; when the second inspection slave machine 200 receives 2 pulse signals, the communication address of the second inspection slave machine 200 is updated to 2, and 3 pulse signals are sent to the third inspection slave machine 200; the inspection slave 200 sequentially executes the steps until the nth inspection slave 200 receives the N pulse signals, the communication address of the nth inspection slave 200 is updated to N, and N +1 pulse signals are sent to the inspection master 100;
s300, determining the number of the pulse signals sent by the last routing inspection slave machine 200 as B, comparing B with a first numerical value, and determining whether address allocation is completed or wrong, wherein the method comprises the following steps: and judging whether the B is equal to the first numerical value plus 1, if yes, judging that the address allocation is successful, and if not, judging that the address allocation is failed.
It should be noted that if the numbers do not match, it indicates that a sequential connection error occurs between the first inspection slave 200 and the nth inspection slave 200, if the number of pulse signals received by the inspection master 100 is N, it indicates that one inspection slave 200 is not connected to the serial circuit, if the number of pulse signals received by the inspection master 100 is N-1, it indicates that two inspection slaves 200 are not connected to the serial circuit, and so on, it may determine a fault condition.
Referring to FIG. 3, in some embodiments of the present invention, upon determining an address assignment error, the following steps are performed:
s400, electrically connecting the second address output interface 210 of the inspection slave 200 in the middle with the first address input interface 120;
and returning to the step of determining that the number of the routing inspection slave machines 200 needing to be allocated with the address is the first numerical value, inputting the first numerical value into the routing inspection master machine 100, and sending 1 pulse signal to the first routing inspection slave machine 200 by the routing inspection master machine 100 until the fault unit is determined.
Since N may be even or radix, performing step S400 may be performed in conjunction with the following two cases:
in the first case:
if N is an even number, for convenience of description, N is set to 8, after steps S100 to S300 are performed for the first time, if the determination fails, the fourth routing inspection second address output interface 210 is electrically connected to the first address input interface 120; executing the step S400, and returning to the step S100 again, that is, determining that the current first numerical value is 4, inputting the address allocation number of 4 to the inspection master 100, and sending 1 pulse signal to the first inspection slave 200 by the inspection master 100;
when the step S200 is executed, that is, the first inspection slave device 200 receives 1 pulse signal, the communication address of the first inspection slave device 200 is updated to 1, and 2 pulse signals are sent to the second inspection slave device 200; when the second inspection slave machine 200 receives 2 pulse signals, the communication address of the second inspection slave machine 200 is updated to 2, and 3 pulse signals are sent to the third inspection slave machine 200; the inspection slave 200 sequentially executes the steps until the fourth inspection slave 200 receives 4 pulse signals, the communication address of the fourth inspection slave 200 is updated to 4, and 5 pulse signals are sent to the inspection master 100;
step S300 is executed, if the inspection master machine 100 receives 5 pulse signals, the position of the fault point is between the fifth inspection slave machine 200 and the eighth inspection slave machine 200, the step S400 is continuously executed on the fifth inspection slave machine 200 to the eighth inspection slave machine 200, the fault point is continuously searched, and the step S400 is repeatedly executed until the fault point is eliminated; similarly, if the inspection master 100 does not receive the 5 pulse signals, it indicates that the position of the fault point is between the first to fourth inspection slave 200, the step S400 is continuously executed on the first to fourth inspection slave 200, the fault point is continuously searched, and the step S400 is repeatedly executed until the position of the fault point is eliminated.
In the second case:
if N is an odd number, for convenience of description, N is set to 9, after steps S100 to S300 are performed for the first time, if the determination fails, the fifth routing inspection second address output interface 210 is electrically connected to the first address input interface 120; executing the step S400, and returning to the step S100 again, that is, determining that the current first numerical value is 5, inputting the address allocation number of 5 to the inspection master 100, and sending 1 pulse signal to the first inspection slave 200 by the inspection master 100;
when the step S200 is executed, that is, the first inspection slave device 200 receives 1 pulse signal, the communication address of the first inspection slave device 200 is updated to 1, and 2 pulse signals are sent to the second inspection slave device 200; when the second inspection slave machine 200 receives the 2 pulse signals, the communication address of the second inspection slave machine 200 is updated to 2, and 3 pulse signals are sent to the third inspection slave machine 200; the inspection slave machine 200 sequentially executes the steps until the fifth inspection slave machine 200 receives 5 pulse signals, the communication address of the fifth inspection slave machine 200 is updated to 5, and 6 pulse signals are sent to the inspection master machine 100;
step S300 is executed, if the inspection master machine 100 receives the 6 pulse signals, the position of the fault point is between the sixth inspection slave machine 200 and the ninth inspection slave machine 200, step S400 is continuously executed on the sixth inspection slave machine 200 to the ninth inspection slave machine 200, the fault point is continuously searched, and step S400 is repeatedly executed until the position of the fault point is eliminated; similarly, if the inspection master 100 does not receive the 6 pulse signals, it indicates that the position of the fault point is between the first to fifth inspection slave 200, the step S400 is continuously executed on the first to fifth inspection slave 200, the fault point is continuously searched, and the step S400 is repeatedly executed until the position of the fault point is eliminated.
Referring to FIG. 4, in some embodiments of the present invention, upon determining an address assignment error, the following steps are performed:
s500, electrically connecting the second address input interface 220 of the inspection slave 200 in the middle with the first address output interface 110;
and returning to the step of determining that the number of the routing inspection slave machines 200 needing to be allocated with the address is the first numerical value, inputting the first numerical value into the routing inspection master machine 100, and sending 1 pulse signal to the first routing inspection slave machine 200 by the routing inspection master machine 100 until the fault unit is determined.
Since N may be even or radix, performing step S500 may be performed in conjunction with the following two cases:
in the first case:
if N is an even number, for convenience of description, N is set to 8, after the steps S100 to S300 are performed for the first time, if the determination fails, the fifth routing inspection second address input interface 220 is electrically connected to the first address output interface 110; executing the step S500, and returning to the step S100 again, that is, determining that the current first numerical value is 4, inputting the address allocation number of 4 to the inspection master 100, and sending 1 pulse signal to the first inspection slave 200 by the inspection master 100;
when the step S200 is executed, that is, the fifth inspection slave device 200 receives 1 pulse signal, the communication address of the fifth inspection slave device 200 is updated to 1, and 2 pulse signals are sent to the sixth inspection slave device 200; if the sixth inspection slave machine 200 receives 2 pulse signals, the communication address of the sixth inspection slave machine 200 is updated to 2, and 3 pulse signals are sent to the seventh inspection slave machine 200; the inspection slave 200 sequentially executes the steps until the eighth inspection slave 200 receives 4 pulse signals, the communication address of the eighth inspection slave 200 is updated to 4, and 5 pulse signals are sent to the inspection master 100;
step S300 is executed, if the inspection master machine 100 receives 5 pulse signals, the position of the fault point is between the first inspection slave machine 200 and the fourth inspection slave machine 200, step S500 is continuously executed on the first inspection slave machine 200 to the fourth inspection slave machine 200, the fault point is continuously searched, and step S500 is repeatedly executed until the fault point is eliminated; similarly, if the inspection master 100 does not receive 5 pulse signals, it indicates that the position of the fault point is between the fifth to eighth inspection slave 200, the step S500 is continuously executed on the fifth to eighth inspection slave 200, the fault point is continuously searched, and the step S400 is repeatedly executed until the fault point is eliminated.
In the second case:
if N is an odd number, for convenience of description, N is set to 9, after steps S100 to S300 are performed for the first time, if the determination fails, the fifth routing inspection second address input interface 220 is electrically connected to the first address output interface 110; executing the step S500, and returning to the step S100 again, that is, determining that the current first numerical value is 5, inputting the address allocation number of 5 to the inspection master 100, and sending 1 pulse signal to the fifth inspection slave 200 by the inspection master 100;
when the step S200 is executed, that is, the fifth inspection slave device 200 receives 1 pulse signal, the communication address of the fifth inspection slave device 200 is updated to 1, and 2 pulse signals are sent to the sixth inspection slave device 200; if the sixth inspection slave machine 200 receives 2 pulse signals, the communication address of the sixth inspection slave machine 200 is updated to 2, and 3 pulse signals are sent to the seventh inspection slave machine 200; the patrol slave 200 sequentially executes the steps until the ninth patrol slave 200 receives 5 pulse signals, the communication address of the ninth patrol slave 200 is updated to 5, and 6 pulse signals are sent to the patrol master 100;
step S300 is executed, if the inspection master machine 100 receives the 6 pulse signals, the position of the fault point is between the first inspection slave machine 200 and the fourth inspection slave machine 200, step S500 is continuously executed on the first inspection slave machine 200, the fault point is continuously searched, and step S500 is repeatedly executed until the fault point is eliminated; similarly, if the inspection master 100 does not receive the 6 pulse signals, it indicates that the position of the fault point is between the fifth to ninth inspection slave 200, the step S500 is continuously executed on the fifth to ninth inspection slave 200, the fault point is continuously searched, and the step S500 is repeatedly executed until the fault point is eliminated.
After the fault point position is eliminated, all the inspection slave machines 200 are connected in series again and then connected between the first address output interface 110 and the first address input interface 120 of the inspection master machine 100, and the step S100 to the step S300 are executed again, so that the address allocation of the N inspection slave machines 200 can be completed smoothly.
It should be noted that there is a fault condition in the embodiment of the present invention, that is, within a set time, if the inspection host 100 has not received the pulse signal all the time, it indicates that there is a poor contact at some point between the N inspection hosts 100, and it may also cooperate with step S400 or step S500, and by checking which combination the inspection host 100 cannot receive the pulse signal, it indicates that a fault point is between them, and by repeatedly cooperating with step S400 or step S500, the fault point may be eliminated, and after the elimination, the step S100 to step S300 are executed again, and address allocation may be completed smoothly.
Another aspect of the embodiments of the present invention provides an electronic device, including a processor and a memory; the memory is used for storing programs; the processor executing the program implements the address assignment method as described above.
In this embodiment, the processor executes the program mainly to execute step S100, step S200, and step S300, and step S400 and step S500 need to be completed in cooperation with manual operation.
The electronic device for performing the address allocation method according to the embodiment of the present invention may be a server, which may generate a relatively large difference due to different configurations or performances, and may include one or more Central Processing Units (CPUs) (e.g., one or more processors) and a memory, and one or more storage media (e.g., one or more mass storage devices) for storing applications or data. The memory and storage medium may be, among other things, transient or persistent storage. The program stored on the storage medium may include one or more modules (not shown), each of which may include a series of instruction operations for the server. Still further, the central processor may be configured to communicate with the storage medium to execute a series of instruction operations in the storage medium on the server.
The server may also include one or more power supplies, one or more wired or wireless network interfaces, one or more input-output interfaces, and/or one or more operating systems, such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, and the like.
A processor in the server may be used to perform the address assignment method.
Embodiments of the present invention further provide a computer-readable storage medium, where the computer-readable storage medium is configured to store a program code, and the program code is configured to execute the address allocation method in each of the foregoing embodiments.
In this embodiment, the program code execution program mainly executes step S100, step S200, step S300, and step S400 and step S500 need to be completed in a manual manner.
Embodiments of the present invention also provide a computer program product, which includes a computer program, and the computer program is stored in a computer readable storage medium. The processor of the computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the address assignment method that implements the above-described address assignment method.
In this embodiment, the computer device executes the program mainly to execute step S100, step S200, step S300, and step S400 and step S500 need to be completed in a manual manner.
The embodiment of the invention at least comprises the following beneficial effects: when the communication addresses of the inspection slave machines (200) are distributed, the communication addresses of the inspection slave machines (200) are set according to the physical sequence of the inspection slave machines (200) by combining the mode of accumulated transmission of the number of pulse signals, the operation of cable connection and the process of address distribution are simplified, and the distribution efficiency, accuracy and reliability of the communication addresses are effectively improved.
The terms "first," "second," "third," "fourth," and the like in the description of the invention and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It is to be understood that, in the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and address assignment," "a and c," "address assignment and c," or "a and b and c," wherein a, b, and c may be single or plural.
It should be understood that in the description of the embodiments of the present invention, a plurality (or a plurality) means two or more, more than, less than, more than, etc. are understood as excluding the number, and more than, less than, etc. are understood as including the number.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form, and the electrical connection mentioned in the present invention may be a wired connection or a wireless connection.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention, which is substantially or partly contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. An address allocation system, comprising:
the inspection host is provided with a first address output interface and a first address input interface;
the system comprises a plurality of inspection slave machines which are electrically connected in sequence, wherein each inspection slave machine is provided with a second address output interface and a second address input interface;
the first address output interface is electrically connected with the second address input interface of the first inspection slave, the first address input interface is electrically connected with the second address output interface of the last inspection slave, and the second address output interface of the previous inspection slave is electrically connected with the second address input interface of the next inspection slave.
2. The address assignment system according to claim 1, wherein: the inspection master machine is also provided with first communication interfaces, each inspection slave machine is provided with a second communication interface, and the first communication interfaces are electrically connected with the second communication interfaces.
3. The address assignment system according to claim 2, wherein: and one of an RS485 bus, an RS-422 bus or a CAN bus is adopted between the first communication interface and the second communication interface for communication transmission.
4. An address allocation method, characterized by: address assignment system as claimed in one of claims 1 to 3, comprising:
determining the number of the inspection slave machines needing address allocation as a first numerical value, inputting the first numerical value to the inspection host machine, and sending 1 pulse signal to the first inspection slave machine by the inspection host machine;
updating the communication address of the inspection slave to be A according to the number A of the pulse signals received by the inspection slave, and sending A +1 pulse signals to the next inspection slave;
and determining the number of the pulse signals sent by the last routing inspection slave machine as B, and comparing B with the first numerical value to judge whether the address allocation is successful or wrong.
5. The address allocation method according to claim 4, wherein: the determining that the number of the pulse signals sent by the last patrol slave machine is B, comparing B with the first numerical value, and determining that address allocation is completed or is wrong comprises the following steps:
and judging whether the B is equal to the first numerical value plus 1, if so, judging that the address allocation is successful, and if not, judging that the address allocation is failed.
6. The address allocation method according to claim 4 or 5, characterized in that: when the address allocation error is determined, the following steps are executed:
electrically connecting the second address output interface of the inspection slave in the middle with the first address input interface;
and returning to the step that the number of the routing inspection slave machines which need to be allocated with addresses is determined to be a first numerical value, inputting the first numerical value to the routing inspection master machine, and sending 1 pulse signal to the first routing inspection slave machine by the routing inspection master machine.
7. The address allocation method according to claim 4 or 5, characterized in that: when the address allocation error is determined, the following steps are executed:
electrically connecting the second address input interface of the inspection slave in the middle with the first address output interface;
and returning to the step that the number of the routing inspection slave machines which need to be allocated with addresses is determined to be a first numerical value, inputting the first numerical value to the routing inspection master machine, and sending 1 pulse signal to the first routing inspection slave machine by the routing inspection master machine.
8. An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the address allocation method of claim 4 or 5 when executing the computer program.
9. A computer-readable storage medium storing a program, wherein the program is characterized by implementing the address assignment method of claim 4 or 5 when executed by a processor.
10. A computer program product comprising a computer program, characterized in that the computer program realizes the address allocation method of claim 4 or 5 when executed by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210294559.4A CN114827088A (en) | 2022-03-24 | 2022-03-24 | Address assignment system, method, electronic device, storage medium, and program product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210294559.4A CN114827088A (en) | 2022-03-24 | 2022-03-24 | Address assignment system, method, electronic device, storage medium, and program product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114827088A true CN114827088A (en) | 2022-07-29 |
Family
ID=82530594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210294559.4A Pending CN114827088A (en) | 2022-03-24 | 2022-03-24 | Address assignment system, method, electronic device, storage medium, and program product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114827088A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115567488A (en) * | 2022-09-30 | 2023-01-03 | 上海京硅智能技术有限公司 | Communication address configuration method, electronic device and storage medium |
| CN115580596A (en) * | 2022-11-24 | 2023-01-06 | 合肥华思系统有限公司 | Automatic battery cluster address distribution system and method based on chain connection |
| CN117439973A (en) * | 2023-10-10 | 2024-01-23 | 深圳市佳合丰新能源科技有限公司 | Equipment address allocation method, battery energy storage system and related equipment |
| CN117439974A (en) * | 2023-10-10 | 2024-01-23 | 深圳市佳合丰新能源科技有限公司 | Equipment address allocation method, battery energy storage system and related equipment |
| CN117614939A (en) * | 2024-01-19 | 2024-02-27 | 杭州方千科技有限公司 | 485 communication address automatic allocation method for image light supplementing device |
| WO2024124779A1 (en) * | 2022-12-16 | 2024-06-20 | 上海艾为电子技术股份有限公司 | Address allocation method and system, chip, and electronic device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060195639A1 (en) * | 2004-12-03 | 2006-08-31 | Sheng-Hung Yang | System and method for dynamically allocating inter integrated circuits addresses to multiple slaves |
| CN106131240A (en) * | 2016-08-09 | 2016-11-16 | 郑州市茂辰电子科技有限公司 | A kind of CAN address distribution method based on daisy chaining and communication system |
| CN110417930A (en) * | 2019-06-19 | 2019-11-05 | 浙江天正电气股份有限公司 | A kind of auto-allocation method of serial device mailing address |
| CN111586205A (en) * | 2020-05-13 | 2020-08-25 | 贵州浙储系统科技有限公司 | Method and device for automatically allocating slave addresses in battery management system |
| CN113037889A (en) * | 2021-03-19 | 2021-06-25 | 天合光能股份有限公司 | Slave machine address allocation method for energy storage battery management system |
| CN113286015A (en) * | 2021-06-10 | 2021-08-20 | 北京华威创联科技有限公司 | Method for automatically allocating address |
| CN114157641A (en) * | 2021-11-30 | 2022-03-08 | 陕西中源智控科技有限公司 | Automatic control equipment address generating system and method based on pulse width communication |
-
2022
- 2022-03-24 CN CN202210294559.4A patent/CN114827088A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060195639A1 (en) * | 2004-12-03 | 2006-08-31 | Sheng-Hung Yang | System and method for dynamically allocating inter integrated circuits addresses to multiple slaves |
| CN106131240A (en) * | 2016-08-09 | 2016-11-16 | 郑州市茂辰电子科技有限公司 | A kind of CAN address distribution method based on daisy chaining and communication system |
| CN110417930A (en) * | 2019-06-19 | 2019-11-05 | 浙江天正电气股份有限公司 | A kind of auto-allocation method of serial device mailing address |
| CN111586205A (en) * | 2020-05-13 | 2020-08-25 | 贵州浙储系统科技有限公司 | Method and device for automatically allocating slave addresses in battery management system |
| CN113037889A (en) * | 2021-03-19 | 2021-06-25 | 天合光能股份有限公司 | Slave machine address allocation method for energy storage battery management system |
| CN113286015A (en) * | 2021-06-10 | 2021-08-20 | 北京华威创联科技有限公司 | Method for automatically allocating address |
| CN114157641A (en) * | 2021-11-30 | 2022-03-08 | 陕西中源智控科技有限公司 | Automatic control equipment address generating system and method based on pulse width communication |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115567488A (en) * | 2022-09-30 | 2023-01-03 | 上海京硅智能技术有限公司 | Communication address configuration method, electronic device and storage medium |
| CN115580596A (en) * | 2022-11-24 | 2023-01-06 | 合肥华思系统有限公司 | Automatic battery cluster address distribution system and method based on chain connection |
| CN115580596B (en) * | 2022-11-24 | 2023-03-10 | 合肥华思系统有限公司 | Automatic battery cluster address distribution system and method based on chain connection |
| WO2024124779A1 (en) * | 2022-12-16 | 2024-06-20 | 上海艾为电子技术股份有限公司 | Address allocation method and system, chip, and electronic device |
| CN117439973A (en) * | 2023-10-10 | 2024-01-23 | 深圳市佳合丰新能源科技有限公司 | Equipment address allocation method, battery energy storage system and related equipment |
| CN117439974A (en) * | 2023-10-10 | 2024-01-23 | 深圳市佳合丰新能源科技有限公司 | Equipment address allocation method, battery energy storage system and related equipment |
| CN117614939A (en) * | 2024-01-19 | 2024-02-27 | 杭州方千科技有限公司 | 485 communication address automatic allocation method for image light supplementing device |
| CN117614939B (en) * | 2024-01-19 | 2024-05-28 | 杭州方千科技有限公司 | 485 Communication address automatic allocation method for image light supplementing device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114827088A (en) | Address assignment system, method, electronic device, storage medium, and program product | |
| EP3410288B1 (en) | Online upgrade method, device and system | |
| JP3657027B2 (en) | Time management system and method for vehicle fault diagnosis apparatus | |
| CN109654666B (en) | Method, device and equipment for debugging unit | |
| JP2010061939A (en) | Multi-cell battery system and method for applying management number | |
| CN108923957B (en) | Distribution network terminal DTU fault elimination method and device and terminal equipment | |
| CN105183575A (en) | Processor fault diagnosis method, device and system | |
| CN111897697A (en) | Server hardware fault repairing method and device | |
| CN114758715B (en) | Method, device and equipment for lighting hard disk fault lamp and readable storage medium | |
| CN111338869A (en) | Configuration parameter management method, device, equipment and storage medium | |
| CN109031005B (en) | Distributed relay protection device testing method and relay protection tester | |
| CN114064435A (en) | Database test method, device, medium and electronic equipment | |
| CN117251401A (en) | Serial port information output control system, method and device | |
| CN111885158A (en) | Cluster task processing method and device, electronic equipment and storage medium | |
| CN109885420B (en) | PCIe link fault analysis method, BMC and storage medium | |
| CN111984287A (en) | Equipment upgrading method and system | |
| CN115933591A (en) | Controller diagnosis method, device, equipment and storage medium | |
| CN115480975A (en) | Wiring checking method and device | |
| CN113447880B (en) | Fault diagnosis method and device for electric energy meter and terminal equipment | |
| CN114429782A (en) | Solid state disk fault diagnosis method, device, equipment and medium | |
| CN112965791A (en) | Timing task detection method, device, equipment and storage medium | |
| CN104102575A (en) | On-line debugging method | |
| CN113271223B (en) | Unified communication management method for charging module and terminal equipment | |
| CN117538672B (en) | Test method and device for target capacitive screen and electronic equipment | |
| CN113190881B (en) | Method and device for determining machine number of charging module and terminal equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |