CN114826219A

CN114826219A - Clock buffer circuit applied to passive and passive voltage mixer

Info

Publication number: CN114826219A
Application number: CN202210748495.0A
Authority: CN
Inventors: 蒋明澔
Original assignee: Gaoche Technology Shanghai Co ltd; Fengjia Microelectronics Kunshan Co ltd
Current assignee: Gaoche Technology Shanghai Co ltd; Fengjia Microelectronics Kunshan Co ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2022-07-29
Anticipated expiration: 2042-06-29
Also published as: CN114826219B

Abstract

The invention belongs to a passive mixer in a wireless transceiver, and particularly relates to a clock buffer circuit applied to a passive voltage mixer, wherein a third capacitor C3 and a fifth capacitor C5, and a second capacitor C2 and a sixth capacitor C6 are used as a capacitor voltage divider to perform signal voltage division processing, and a first voltage bias VB1, a second voltage bias VB2, a third voltage bias VB3 and a fourth voltage bias VB4 are matched, so that a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4 are in a good working interval. The first transistor M1 and the second transistor M2 or the third transistor M3 and the fourth transistor M4 form a dual-gate, cascode form, so that the second transistor M2 protects the first transistor M1, and the third transistor M3 protects the fourth transistor M4. On the premise of reliability and safety, the swing amplitude of the clock is reasonably improved, so that the switching performance of the frequency mixer is further improved.

Description

Clock buffer circuit applied to passive and passive voltage mixer

Technical Field

The invention belongs to a passive mixer in a wireless transceiver, and particularly relates to a clock buffer circuit applied to a passive voltage mixer.

Background

The modern era is an era of high-speed development and an era of information explosion, and the ever-increasing data requirements of people are difficult to meet by means of the traditional transceiver, so that the broadband high-speed radio frequency transceiver is produced at the same time and is a necessary product of the development of the era. However, the indexes of broadband, high linearity, low noise and high speed are balanced for the hardware IC implementation, and it is difficult to improve the indexes comprehensively. Therefore, designers are seeking to improve these indexes and the development of integrated circuits is still being driven.

With the requirement of broadband, high speed and high power for transmitting information, these characteristics impose severe requirements on the traditional passive mixer, which is difficult to adapt to the requirement of high performance, and the performance of the mixer as a ring that cannot be lacked in the broadband high-speed radio frequency transceiver architecture greatly affects the indexes of the system. The traditional passive mixer is required by the reliability of the device, and the linear switching on or off of the switch cannot be ensured under the condition of large amplitude of baseband signals, so that the baseband influences each other or the nonlinearity of the switch resistor is introduced, thereby deteriorating the performance. The other active mixer is difficult to completely replace the position of the passive mixer due to high power consumption and poor noise. There is therefore a strong need for a passive mixer that provides better performance.

With the advance of the process, the size of the CMOS becomes smaller and smaller, and the withstand voltage becomes stricter and stricter. The prior art clock buffer generally adopts NMOS and PMOS inverters, but this means that the clock swing becomes smaller, which affects the linearity of the switch.

Disclosure of Invention

The invention aims to provide a clock buffer applied to a passive voltage mixer and a circuit thereof, which can improve clock swing or introduce a high-speed bootstrap circuit to solve the problem of switch nonlinearity.

In order to achieve the purpose, the invention provides the following technical scheme:

a circuit applied to a clock buffer of a passive voltage mixer, the clock buffer being of a dual gate cascode form, comprising:

the input ends of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are electrically connected to provide input signals;

the gate of the first transistor M1 is electrically connected to the first end of the first resistor R1 and the output end of the first capacitor C1, the source of the first transistor M1 is grounded, the first bias voltage VB1 is electrically connected to the second end of the first resistor R1, and the first transistor M1 is biased;

the gate of the second transistor M2 is electrically connected to the first end of the second resistor R2, the output end of the second capacitor C2 and the first end of the sixth capacitor C6, the source of the second transistor M2 is electrically connected to the drain of the first transistor M1, the second bias voltage VB2 is electrically connected to the second end of the second resistor R2, the second transistor M2 is biased, and the second end of the sixth capacitor C6 is grounded;

a gate of the third transistor M3 is electrically connected to the first end of the third resistor R3, the output end of the third capacitor C3 and the first end of the fifth capacitor C5, a drain of the third transistor M3 is electrically connected to a drain of the second transistor M2 as an output electrode, the third bias voltage VB3 is electrically connected to the second end of the third resistor R3, the third transistor M3 is biased, and the second end of the fifth capacitor C5 is grounded;

a gate of the fourth transistor M4 is electrically connected to the first end of the fourth resistor R4 and the output end of the fourth capacitor C4, a source of the fourth transistor M4 is connected to the power supply electrical VDD, a drain of the fourth transistor M4 is electrically connected to the source of the third transistor M3, and the fourth bias voltage VB4 is electrically connected to the second end of the fourth resistor R4, so as to bias the fourth transistor M4;

a passive voltage mixer comprises a clock buffer formed by the circuit of the clock buffer, a signal from a transmitter flows into a baseband input end of the passive mixer through a low-pass filter I and a low-pass filter Q, an input clock signal flows into a clock input end of the passive mixer through the clock buffer to carry out up-conversion operation, the frequency-converted signal enters a variable gain amplifier to carry out gain adjustment, and finally flows into a power amplifier to output a power signal, and a bias circuit of the passive voltage mixer consists of a variable current and current-voltage conversion module.

Compared with the prior art, the invention has the beneficial effects that:

1. on the premise of reliability and safety, the swing amplitude of the clock is reasonably improved, so that the switching performance is further improved.

2. The modification does not sacrifice extra power consumption, still keeps the advantages of low power consumption and low noise of the passive mixer, and only optimizes the defects of the passive mixer, namely large voltage swing and linear deterioration.

3. The invention relates to a passive voltage mixer in a wireless transceiver. The method has the advantages of low power consumption, high linearity, adaptability to the process requirement and low noise, so the method is widely applied.

4. In the current era of high-speed communication, various advanced protocols are gradually used to increase data transmission rates, such as 5G, 6G, and so on. These advanced communication protocols also place higher demands on the rf transceiver, such as linearity, noise, power consumption, etc. Therefore, the invention provides a novel high-linearity high-conversion-gain passive mixer for solving the problem of third harmonic degradation in the passive mixer, and mainly aims to improve a clock buffer into a dual-gate clock buffer so as to ensure the linearity of a switch under the condition of a large baseband signal.

Drawings

FIG. 1 is a circuit diagram of a dual-gate cascode (dual-gate cascode) form of clock buffer in accordance with the present invention;

FIG. 2 is a simplified block diagram of a passive voltage mixer with a clock buffer according to the present invention; the LPF is low-pass filtering, the MIXER is a passive MIXER, the LO BUFFER is a clock BUFFER, the PGA is a variable gain amplifier, and the PA is a power amplifier;

FIG. 3 is a graph showing the experimental results of the amplitude of the clock buffer according to the present invention.

Detailed Description

The following further describes embodiments of the present invention with reference to the drawings.

The invention adopts a clock buffer (namely a dual-gate common-gate clock) with a capacitive voltage division mode, can achieve high output swing amplitude and small upper and lower edge delay, is used as a high-speed clock amplifier, can well protect a transistor in a safe area, and prolongs the service life of the transistor.

The double-gate layout can improve the speed of the buffer, improve the driving capability of the rear stage, and the cascode can protect the switch in a safe area, thereby prolonging the service life of the device.

Fig. 1 is a circuit diagram of a clock buffer in the form of a dual-gate cascode.

The input terminals of the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are electrically connected to provide an input signal.

The gate of the first transistor M1 is electrically connected to the first terminal of the first resistor R1 and the output terminal of the first capacitor C1, the source of the first transistor M1 is grounded, and the first bias voltage VB1 is electrically connected to the second terminal of the first resistor R1 to bias the first transistor M1.

The gate of the second transistor M2 is electrically connected to the first end of the second resistor R2, the output end of the second capacitor C2 and the first end of the sixth capacitor C6, the source of the second transistor M2 is electrically connected to the drain of the first transistor M1, the second bias voltage VB2 is electrically connected to the second end of the second resistor R2, the second transistor M2 is biased, and the second end of the sixth capacitor C6 is grounded.

The gate of the third transistor M3 is electrically connected to the first end of the third resistor R3, the output end of the third capacitor C3, and the first end of the fifth capacitor C5, the drain of the third transistor M3 is electrically connected to the drain of the second transistor M2 as an output electrode, the third bias voltage VB3 is electrically connected to the second end of the third resistor R3, the third transistor M3 is biased, and the second end of the fifth capacitor C5 is grounded.

The gate of the fourth transistor M4 is electrically connected to the first end of the fourth resistor R4 and the output end of the fourth capacitor C4, the source of the fourth transistor M4 is connected to the power supply electrical VDD, the drain of the fourth transistor M4 is electrically connected to the source of the third transistor M3, and the fourth bias voltage VB4 is electrically connected to the second end of the fourth resistor R4 to bias the fourth transistor M4.

The third capacitor C3 and the fifth capacitor C5 function as a capacitive voltage divider, and the second capacitor C2 and the sixth capacitor C6 also function as a capacitive voltage divider.

In the circuit, the third capacitor C3 and the fifth capacitor C5, and the second capacitor C2 and the sixth capacitor C6 are used as a capacitive voltage divider to perform signal voltage division processing, and cooperate with the first voltage bias VB1, the second voltage bias VB2, the third voltage bias VB3 and the fourth voltage bias VB4, so that the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are in a good working interval.

The first transistor M1 and the second transistor M2 or the third transistor M3 and the fourth transistor M4 form a dual-gate.

The CASCODE (cascod) form has the second transistor M2 protecting the first transistor M1, and the third transistor M3 protecting the fourth transistor M4.

The Dual-gate cascode clock buffer is powered by a low dropout linear regulator, four bias voltages VB1, VB2, VB3 and VB4 are generated by a bias circuit, however, the bias circuit must overcome the changes of process and temperature, the input of the clock buffer is connected with a high-speed clock signal, and the output drives the gate stage of the passive mixer.

Fig. 2 is a simplified block diagram of a clock BUFFER applied to a passive voltage MIXER, where the transmitter is a zero-if transmitter, quadrature baseband signals are used, the signals flow into the baseband input terminal of MIXER via LPF _ I and LPF _ Q, and the LO clock signals flow into the clock input terminal of MIXER via the LO BUFFER clock BUFFER for up-conversion. The frequency-converted signal enters the PGA to adjust the gain, and finally flows into the PA to output a power signal. The MIXER is a passive MIXER, the LO _ BUFFER is a dual-gate BUFFER of the present application, and the bias circuits thereof are each composed of a variable current mirror and a current-voltage conversion module (not shown in the figure), so as to provide a suitable operating voltage, and ensure that the transistor operates in a suitable state, thereby overcoming the variation of PVT.

A source electrode of a passive voltage mixer for a transmitter is connected with an analog baseband part of a radio frequency transceiver, the bandwidth of a signal is usually within the bandwidth of 200MHz, and an up-conversion signal is output; the source of the passive mixer for the receiver is connected with a radio frequency signal, and a down-conversion signal is generated by the mixer to complete the function of the mixer, namely the frequency shifting function.

The working process of the invention is as follows:

firstly, an input square wave signal is at a high level of 1V and a low level of 0V, and simultaneously, a direct current voltage is reset through a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, and voltages of a first bias voltage VB1, a second bias voltage VB2, a third bias voltage VB3 and a fourth bias voltage VB4 are all composed of a variable current module and a current-voltage conversion module which are digitally controllable, so that the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all at proper voltages. Under the conditions that the low level of an output signal is 0V and the high level of the output signal is the full swing of power supply voltage (the range of the power supply voltage is 1.2V to 1.8V), the gate source voltage, the gate drain voltage and the source drain voltage of all transistors can not exceed 1V, and the service life of the transistors is prolonged. The third capacitor C3 and the fifth capacitor C5 form a signal divider to adjust the swing of the input signal at the gate of the third transistor M3. Similarly, the second capacitor C2 and the sixth capacitor C6 also form a signal divider to adjust the gate input signal swing of the second transistor M2. The gate input signal swing of the first transistor M1 and the fourth transistor M4 is 0 to 1V, as is the input signal. Since the gates of the first transistor M1 and the second transistor M2 both have signal swings, and similarly, the third transistor M3 and the fourth transistor M4 also have input signal swings, there is strong load driving capability, and it is suitable for implementing a high-speed circuit.

Experimental results of the amplitude of the clock buffer of the present invention are shown in fig. 3. The voltage swing of the traditional inverter is limited by the process of a 28nm transistor, only 1V voltage swing can be output, but a dual-gate cascode clock buffer can realize higher clock swing, as shown in FIG. 3, the output clock swing can be realized between 1.2V and 1.8V, and the adjustment of VDD voltage can be realized by using a low-dropout linear regulator or an external variable power supply.

Claims

1. A circuit for a clock buffer for a passive voltage mixer, comprising: the clock buffer is in a dual-gate cascode form, and includes:

2. A passive voltage mixer, characterized by: the clock buffer comprises the circuit of the clock buffer according to claim 1, wherein a signal from a transmitter flows into a baseband input end of the passive mixer through a low-pass filter _ I and a low-pass filter _ Q, an input clock signal flows into a clock input end of the passive mixer through the clock buffer to carry out up-conversion operation, the frequency-converted signal enters the variable gain amplifier to carry out gain adjustment, and finally flows into the power amplifier to output a power signal, and a bias circuit of the clock buffer comprises a variable current and current-voltage conversion module.