JP3350437B2 - High frequency switch device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an RF (Radio Radio)
Frequency) The present invention relates to a high-frequency switch device that switches an input / output path of an RF signal in a transmission or reception mode of a transceiver.

[0002]

2. Description of the Related Art Automobile / mobile phone / PHS (Per)
In the case of a high-frequency switch device in a system such as a personal handy phone system, a circuit configuration using on / off by a PIN diode has been mainly used in the past, but is not suitable for miniaturization, which is a requirement of recent devices. , A single pole dual through (SPDT) switch composed of an FET has become mainstream. Further, a switch circuit having one control terminal has been attracting attention in order to reduce the burden of system design. FIG. 3 shows a conventional one-terminal-type high-frequency switch device incorporating an inverter circuit 80. This high-frequency switch device is a single power supply operation SP having a positive power supply voltage.
It has a DT switch. In case of SPDT switch,
Since there are two transmission paths, two control signals inverted from each other are required. Therefore, an inverter circuit 80 is built in and 1
This realizes a control terminal type high frequency switch device. 3, an input / output terminal 2 for a high-frequency signal is connected to a signal input / output terminal 3 via an FET 11, and the signal input / output terminal 3 is connected to a power supply terminal 6 via an FET 13. Further, the signal input / output terminal 2 is connected to the signal input / output terminal 4 via the FET 12, and the signal input / output terminal 4 is connected to the FET 14
Is connected to the power supply terminal 6 via the. In the following, FET1
The FETs 1 and 12 are called through FETs, and the FETs 13 and 14 are called shunt FETs. The power supply terminal 6 is grounded via a decoupling capacitor 40. The above configuration is called a shunt type switch circuit.

A control terminal 70 is an input terminal of an inverter circuit 80, and a shunt FET via a gate resistor 35.
Through-gate via gate 14 and gate resistor 32
11 gates. The output terminal 7 of the inverter circuit 80 is connected to the shunt F via the gate resistor 34.
Through gate F of ET13 and through resistor F via gate resistor 33
Each is connected to the gate of ET12. The power terminal 6
Is connected to the input / output terminal 2 via the resistor 31. Resistance 3
1 to 35 are high resistances of several KΩ.

The inverter circuit 80 includes a driver FET 81
And a load FET 82. In the above high-frequency switch device, FETs 11 to 14 and 82 are depletion type FETs, and FET 81 is an enhancement type F
ET.

Assuming a switch for switching an antenna of a digital cordless telephone between a transmitting state and a receiving state, for example, a signal input / output terminal 2 is an antenna signal terminal, a signal input / output terminal 3 is a terminal of a power transmission path on a transmission side, and a signal input / output. Terminal 4
Is the terminal of the small signal transmission path on the receiving side. Power supply voltage 3V
For example, when the control signal voltage is 3 V in the SPDT switch that operates with a single power supply, the transmission-side FET 11 is turned on and the reception-side FET 12 is turned off, and the transmission mode is set. When the control signal voltage is 0V, the transmission side FET
11 is OFF, the FET 12 on the receiving side is ON, and the transmission mode is set. As described above, the inverter circuit 8
The high-frequency switch device incorporating 0 can be controlled by one terminal.

[0006]

However, there has been a problem that the above-described inverter circuit 80 cannot secure a sufficient high level and low level. “High level” here
The “low level” indicates that the output voltage (the voltage of the terminal 7) when the input signal applied to the control terminal 70 is “0” in the output voltage of the inverter circuit 80 is “high level”, and the input signal is “1”. Is defined as "low level".

FIG. 4 shows the input / output characteristics of the inverter circuit 80. When the input voltage becomes higher than the Schottky voltage, a current flows and the low level rises due to the source resistance of the FET 81. The output voltage when the input is 3V is 0.8V. The low-level floating has a problem in that a linear output cannot be obtained when a large signal is input, resulting in distortion.

To explain this problem, consider a case where a signal is input from the terminal 3 on the transmitting side and output to the antenna terminal 2 via the through FET 11 in the ON state. FIG.
5 shows a relationship between the gate-source voltage (Vgs) of the through FET 12 in the off state and the current. Power supply voltage 3V
When 3V is applied to the gate terminal of the FET 11 and 0V is applied to the gate terminal of the FET 12, the gate-source voltage Vgs of the FET 12 is in the state of -3V. When an AC signal is input from the transmission side, the gate-source voltage Vgs has an amplitude corresponding to the input power, and when a large signal is input, the threshold voltage Vt of the FET 12 as shown by the broken line in FIG.
h, and the through FET 12 that was in the off state exceeds AC
May be turned on. The low-level floating shifts the Vgs between the gate and the source of the through FET 12 in the off state to a state shifted to the + side by the floating voltage. When turned on, current starts to flow to the receiving side, the waveform of the signal is distorted, and noise radio waves such as second harmonic spurious and third harmonic spurious other than the fundamental wave are generated.
The system may fail.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to realize a low-distortion high-frequency switch device incorporating an inverter circuit with as few malfunctions as possible.

[0010]

In order to solve the above-mentioned problems, a high-frequency switch device according to the present invention comprises a first FET for turning on and off a transmission path on a reception side, and an on and off switch for a transmission path on a transmission side. S having a second FET and at least one control signal input terminal to which a control signal is input
A PDT switch circuit, an inverter including an FET, and a high-level and low-level transition region of the inverter provided downstream of the inverter,
A push-pull circuit comprising an FET; and a gate provided before the inverter so that a maximum value of a gate voltage applied to a gate of the FET of the inverter and the push-pull circuit does not exceed a Schottky voltage. A level shifter for voltage, a source follower circuit including an FET, an input terminal connected to the source follower circuit, and an inverter circuit unit having an output terminal connected to the push-pull circuit; It is characterized by being.

The control signal input terminal of the SPDT switch circuit is connected to the input terminal of the inverter circuit and the gate of the first FET, and the output terminal of the inverter circuit is connected to the first terminal. Is preferably connected to the gate of the FET.

It is preferable that each of the input terminal and the output terminal of the inverter circuit is grounded via a decoupling capacitor.

[0013]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the high-frequency switch device according to the present invention. The high-frequency switch device 1 according to the present embodiment is used for an antenna switch of a digital cordless telephone, and includes a switch circuit unit 10 and an inverter circuit unit 50.

The switch circuit section 10 is an SPDT switch circuit, and includes a transmission-side through FET (not shown), a reception-side through FET (not shown), and an antenna signal terminal An.
t, terminal Tx of the power transmission path on the transmission side, terminal Rx of the small signal transmission path on the reception side, ON of the transmission side through FET,
A control terminal Vc _- Tx for controlling OFF, a control terminal Vc _- Rx for controlling ON and OFF of the receiving side through FET, a power supply terminal Vdd _- sw, and GN
It has a D terminal GND _- sw.

The inverter circuit section 50 includes a source follower circuit 52, an inverter 54, and a push-pull circuit 56.
And decoupling capacitors 62 and 64.

The source follower circuit 52 includes cascaded depletion type MOS transistors 52a and 52a.
b, 52c and 52d. Transistor 52a
Is the power supply terminal Vdd _- I of the inverter circuit unit 50
It has a configuration in which it is connected to NV, its gate is connected to the control input terminal IN, and its drain is connected to the source and gate of the transistor 52b. Transistor 52c
Has a configuration in which both the gate and the source are connected to the drain of the transistor 52b, and the drain is connected to the source of the transistor 52d. In addition, transistor 5
2d has a configuration in which the gate and the drain are connected to the ground terminal GND _- INV of the inverter circuit unit 50 and to one terminal of the decoupling capacitor 62. Note that the other terminal of the decoupling capacitor 62 is connected to the control input terminal IN.

On the other hand, the inverter 54 includes a depletion type MOS transistor 54a and an enhancement type MO transistor.
And an S transistor 54b. Transistor 5
4a is a power source terminal Vdd of the inverter circuit unit 50.
_- is connected to INV, gate and drain are configured to be connected to the drain of the transistor 54b.
The transistor 54b has a configuration in which the gate is connected to the source of the transistor 52d and the source is connected to the ground terminal GND _- INV of the inverter circuit unit 50.

The push-pull circuit 56 includes enhancement-type MOS transistors 56a, connected in series.
56b. The transistor 56a has a drain connected to the power supply terminal Vdd _- INV of the inverter circuit unit 50, a gate connected to the gate and drain of the transistor 54a, a source connected to the drain of the transistor 56b, and a decoupling capacitor 64.
Is connected to one of the terminals. The transistor 56b has a gate connected to the source of the transistor 52d, and a source connected to the ground terminal G of the inverter circuit unit 50.
It is configured to be connected to ND _- INV and to the other terminal of the decoupling capacitor 64. The one terminal of the decoupling capacitor 64 is connected to the control terminal Vc _- Tx. Further, the control input terminal IN is connected to the control terminal Vc _- Rx.

In the high-frequency switch device according to the present embodiment thus configured, the source follower circuit 52 includes the FET 54b of the inverter 54, the push-pull circuit 56
The level is shifted so that the maximum value of the voltage input to the FET 56b does not exceed the Schottky voltage. For this reason, in the present embodiment, the shift amount is determined by the two FETs 52b and 52c. However, it goes without saying that the number varies depending on the power supply voltage. FIG. 2 shows input / output characteristics of the inverter 54 according to the present embodiment. Since the Schottky voltage is not exceeded, the low level of the inverter 54 is set to 0.
05V. The push-pull circuit 56 includes an inverter 54
Has the function of reducing the transition region between the high level and the low level. Therefore, there is an effect that the margin for the fluctuation of the signal voltage is increased. Further, the decoupling capacitance 6 is connected to the input terminal IN and the output terminal 110 of the inverter circuit unit 50.
Since 2 and 64 are added, the fluctuation of the signal line can be suppressed.

The input terminal IN of the inverter circuit unit 50 is directly connected to the ON and O of the receiving side through FET of the switch circuit unit 10.
Connected to the terminal Vc _- Rx for controlling the FF, the output terminal 110 of the inverter circuit section is a transmission-side through FET.
Is connected to a terminal Vc _- Tx for controlling ON and OFF of the terminal. Generally, it is difficult to set the low level of the inverter to 0 V because of the floating due to the source resistance of the FET. Since the distortion is more problematic in the case of the transmission mode, it is necessary to reliably supply a "0" signal to the control terminal Vc _- Rx for controlling the receiving side.

Therefore, in the present embodiment, the control input terminal IN is connected so as to supply a control signal to the control terminal Vc _- Rx for directly controlling the receiving side.

In this embodiment, the ground power supply GND of the switch circuit section 10 and the inverter circuit section 50 is provided.
And the drive power supply Vdd are provided separately, so that malfunction and performance degradation due to coupling of signals via the ground power supply GND and the drive power supply Vdd can be prevented.

A high-frequency switch device in which an SPDT switch circuit obtained by removing the inverter circuit 80 from the conventional high-frequency switch device shown in FIG. 3 is used as the switch circuit section 10 of the high-frequency switch device of the present embodiment, and FIG. The performance of the conventional high-frequency switch device shown in FIG. When the power supply voltage Vdd is 3 V and the transmission mode, the spurious is -50 in the conventional high-frequency switch device.
The maximum value of the output power satisfying dBc or less was 21 dBm, whereas the maximum value of the output power was 26 dBm in the high-frequency switch device of the present embodiment. For this reason, 5d compared to the conventional case
Bm is improved, and it becomes possible to have a sufficient margin in consideration of the practical aspect with respect to the standard (21 dBm or more) in RCR STD-28 of PHS.

As described above, according to the present embodiment, the inverter 54 is connected to the source follower circuit 5 in the preceding stage.
2. Since the push-pull circuit 56 is provided at the subsequent stage, both the high level and the low level are sufficiently secured.
Therefore, the linear characteristic of the switch is not degraded by the inverter 54. Further, since the control input terminal IN is directly connected to the control terminal Vc _- Rx for directly controlling the receiving side, it is possible to reliably supply the "0" signal, so that distortion in the transmission mode can be suppressed. Further, since the input / output terminals are grounded via the decoupling capacitors 62 and 64, there is no malfunction due to signal fluctuation.

In order to explain the good performance of the high-frequency switch device according to the present embodiment, the case where the conventional shunt type switch circuit shown in FIG. 3 is used as the switch circuit section 10 has been described. It is not limited to. For example, the same effect can be obtained by using a resonance circuit type switch circuit in which inductors are connected in parallel to the through FETs 11 and 12 of the conventional shunt type switch circuit shown in FIG. Also, the case where the switch circuit unit 10 includes the power supply terminal and the GND terminal has been described, but it is needless to say that the same effect can be obtained even in the case where the switch circuit unit 10 does not include either or both terminals.

[0026]

As described above, according to the present invention, it is possible to obtain a high-frequency switch device with resistance distortion, which incorporates an inverter circuit with as few malfunctions as possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a high-frequency switch device according to the present invention.

FIG. 2 is a graph showing input / output characteristics of the inverter circuit according to the embodiment shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional high-frequency switch device.

FIG. 4 is a graph showing input / output characteristics of an inverter circuit used in a conventional high-frequency switch device.

FIG. 5 is an explanatory diagram for explaining a problem of a conventional high-frequency switch device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High frequency switch device 10 Switch circuit part 50 Inverter circuit part 52 Source follower circuit 54 Inverter 56 Push-pull circuit 62 Decoupling capacitor 64 Decoupling capacitor 110 Output terminal IN Control input terminal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-37334 (JP, A) JP-A-2-166829 (JP, A) JP-A-59-231920 (JP, A) JP-A 64-64 71219 (JP, A) JP-A-8-330930 (JP, A) JP-A-5-199094 (JP, A) JP-A-6-29811 (JP, A) JP-A-8-70245 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 17/00 H04B 1/44

Claims (3)

(57) [Claims] 1. A first method for turning on / off a transmission path on a receiving side.
And the second for turning on and off the transmission path on the transmission side
And an SPDT switch circuit having at least one control signal input terminal to which a control signal is input, an inverter including an FET, and a high level and a low level of the inverter provided at a subsequent stage of the inverter. And a push-pull circuit composed of an FET for reducing the transition region of the inverter and an FE of the inverter and the push-pull circuit provided before the inverter.
A source follower circuit comprising an FET, which level-shifts the gate voltage so that the maximum value of the gate voltage applied to the gate of T does not exceed the Schottky voltage;
A high-frequency switch device comprising: an inverter circuit unit having an input terminal connected to the source follower circuit and an output terminal connected to the push-pull circuit. 2. The control signal input terminal of the SPDT switch circuit is connected to the input terminal of the inverter circuit unit and the gate of the first FET, and the output terminal of the inverter circuit unit is connected to the second terminal. 2. The high-frequency switch device according to claim 1, wherein the high-frequency switch device is connected to a gate of the FET. 3. The high-frequency switch device according to claim 1, wherein the input terminal and the output terminal of the inverter circuit unit are each grounded via a decoupling capacitor.