CN114825296A - Field-effect tube array and multi-module heterogeneous chip - Google Patents
Field-effect tube array and multi-module heterogeneous chip Download PDFInfo
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- CN114825296A CN114825296A CN202210413896.0A CN202210413896A CN114825296A CN 114825296 A CN114825296 A CN 114825296A CN 202210413896 A CN202210413896 A CN 202210413896A CN 114825296 A CN114825296 A CN 114825296A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/026—Current limitation using PTC resistors, i.e. resistors with a large positive temperature coefficient
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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Abstract
The invention discloses a field effect transistor array and a multi-module heterogeneous chip, and relates to the technical field of chips. The field effect tube array comprises a plurality of field effect tubes which are connected in parallel, source electrodes of the field effect tubes are connected with a power supply, drain electrodes of the field effect tubes are connected with a load, the on-resistance of the field effect tubes has a positive temperature coefficient effect, and the grid electrode of each field effect tube is electrically connected with the control regulation port. According to the field effect transistor array and the multi-module heterogeneous chip provided by the embodiment of the invention, by utilizing the positive temperature coefficient effect of the on-resistance of the field effect transistor, when the power of a certain area is higher and the temperature is increased, the on-resistance of the field effect transistor in the area is increased, the passing current is reduced, and the passing current of the field effect transistor distributed in the area with lower temperature is increased, so that the temperature is increased, and the effects of dynamic power adjustment and temperature balance are achieved. Meanwhile, the grid voltage of the field effect transistor array is changed by controlling the adjusting port, and the current flowing through the field effect transistor array can be controlled.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a field effect transistor array and a multi-module heterogeneous chip.
Background
With the rapid development of integrated circuits in recent years, the trend of chips towards high integration, small size and high speed is breaking through, but the heat dissipation problem of chips is also gradually highlighted, especially for multi-module heterogeneous chips. The multi-module heterogeneous chip is a multifunctional and complex functional chip which is realized by a plurality of modules through heterogeneous 3D technology, and due to different power consumptions of different modules, the chip is easily heated unevenly, unexpected thermal stress and other problems are generated, and the electrical property, the working frequency, the mechanical strength, the reliability and the like of the chip are influenced. The heat flux density of some high-power chips and microsystems is up to 130W/cm 2 The need for thermal balancing techniques has increased to a very high level.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a field effect transistor array and a multi-module heterogeneous chip, which can solve the problem that the interior of the chip is heated unevenly.
In one aspect, a fet array according to an embodiment of the present invention includes: the field-effect transistors are connected in parallel, the source electrodes of the field-effect transistors are connected with a power supply, the drain electrodes of the field-effect transistors are connected with a load, and the on-resistance of the field-effect transistors has a positive temperature coefficient effect; and the control and regulation port is electrically connected with the grid electrode of each field effect transistor respectively.
According to some embodiments of the invention, the control and regulation port is electrically connected to a control and regulation module inside the multi-module heterogeneous chip.
On the other hand, the multi-module heterogeneous chip comprises a heterogeneous module layer, a heterogeneous power supply layer and a control layer which are electrically connected in sequence; wherein: a plurality of integrated modules are arranged on the heterogeneous module layer; the heterogeneous power supply layer is provided with a plurality of field effect tube arrays, and the power supply provided by the heterogeneous power supply layer supplies power to the integrated module through the field effect tube arrays; and the control layer is provided with a control and regulation module which is electrically connected with the control and regulation port of each field effect transistor array respectively.
According to some embodiments of the invention, the heterogeneous module layer, the heterogeneous power layer and the control layer are stacked.
According to some embodiments of the invention, the heterogeneous module layer is electrically connected to the heterogeneous power layer through a through silicon via, and the heterogeneous power layer is electrically connected to the control layer through a through silicon via.
According to some embodiments of the invention, a plurality of the integrated modules are disposed on the heterogeneous module layer by a three-dimensional heterogeneous integration technique.
According to some embodiments of the present invention, a digital-to-analog converter is disposed inside the control and regulation module, and the digital-to-analog converter has a plurality of channels corresponding to the control and regulation ports of the plurality of fet arrays one to one.
According to some embodiments of the invention, the control and regulation module is electrically connected to external pins of the multi-module heterogeneous chip.
According to some embodiments of the invention, the integrated module is a MCU or MMIC or MEMS.
According to some embodiments of the invention, the field effect transistor is a Planar FET or a FinFET or a GAAFET.
The field effect transistor array and the multi-module heterogeneous chip provided by the embodiment of the invention at least have the following beneficial effects: the field effect transistor array is uniformly distributed in a distributed mode in a heterogeneous power supply layer by utilizing the positive temperature coefficient effect of the on-resistance of the field effect transistor, when the power of a certain area is high and the temperature is increased, the on-resistance of the field effect transistor in the area is increased, the passing current is reduced, the passing current of the field effect transistor distributed in the area with the lower temperature is increased, the temperature is increased, and the effect of dynamic power adjustment and temperature balance is achieved. Meanwhile, the grid voltage of the field effect tube array is changed by controlling the adjusting module and the adjusting port, and the current flowing through the field effect tube array can be controlled, so that the programmable control of the power is realized.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic structural diagram of an FET array according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a multi-module heterogeneous chip according to an embodiment of the present invention;
reference numerals:
the field effect transistor array 100, the field effect transistor 110, the load 111, the control regulation port 120, the heterogeneous module layer 200, the heterogeneous power supply layer 300, the control layer 400, the control regulation module 410, and the through silicon via 500.
Detailed Description
Reference will now be made in detail to the present embodiments of the present invention, preferred embodiments of which are illustrated in the accompanying drawings, wherein the drawings are provided for the purpose of visually supplementing the description in the specification and so forth, and which are not intended to limit the scope of the invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
On the one hand, as shown in fig. 1 and fig. 2, the fet array according to the embodiment of the present invention includes a plurality of fets 110 connected in parallel, sources of the plurality of fets 110 are connected to a power supply, drains of the plurality of fets 110 are connected to a load 111, an on-resistance of the fets 110 has a positive temperature coefficient effect, and a gate of each fet 110 is electrically connected to the control and regulation port 120.
As shown in fig. 1, the fet array 100 includes a plurality of fets 110 connected in parallel, all the fets 110 have their sources connected to a power supply Vdd, all the fets 110 have their drains connected to a load 111, and all the fets 110 have their gates electrically connected to a control and regulation port 120. Since the on-resistance of the fet 110 has a positive temperature coefficient effect, the on-resistance of the fet 110 increases as the temperature increases; for the fet array 100 having a plurality of fets 110 connected in parallel, the fet 110 with a high temperature has a large on-resistance and a large current, and the fet 110 with a low temperature has a small on-resistance and a large current, so that dynamic power adjustment can be achieved to achieve thermal balance. Meanwhile, since the gate of the fet 110 is connected to the control adjustment port 120, the current capacity of the fet array 100 can be adjusted by adjusting the output voltage of the control adjustment port 120, thereby adjusting the supply power.
On the other hand, as shown in fig. 1 and fig. 2, the multi-module heterogeneous chip according to the embodiment of the present invention includes a heterogeneous module layer 200, a heterogeneous power layer 300, and a control layer 400, which are electrically connected in sequence; wherein: a plurality of integrated modules are arranged on the heterogeneous module layer 200; the heterogeneous power supply layer 300 is provided with a plurality of field effect transistor arrays 100 as described above, the plurality of field effect transistor arrays 100 are connected in parallel, and the power supply provided by the heterogeneous power supply layer 300 supplies power to the integrated module through the field effect transistor arrays 100; the control layer 400 is provided with a control and regulation module 410, and the control and regulation module 410 is electrically connected to the control and regulation port 120 of each fet array 100.
Specifically, as shown in fig. 2, in some embodiments, the heterogeneous module layer 200, the heterogeneous power layer 300, and the control layer 400 are stacked. Furthermore, the heterogeneous module layer 200, the heterogeneous power supply layer 300, and the control layer 400 may be connected Through a Through Silicon Via (TSV) 500.
As shown in fig. 2, a plurality of Integrated modules with different structures and functions, such as an MCU (Micro controller Unit), an MMIC (Monolithic Microwave Integrated Circuit), an MEMS (Micro-Electro-Mechanical System), or other ICs, are disposed on the heterogeneous module layer 200, and are not limited herein. A plurality of integrated modules are packaged in a chip through a three-dimensional heterogeneous integration technology.
The heterogeneous power layer 300 is a power supply module in the multi-module heterogeneous chip, and is used for supplying power to the integrated modules on the heterogeneous module layer 200. In the heterogeneous power layer 300, a plurality of fet arrays 100 are disposed in parallel, as shown in fig. 1, the plurality of fet arrays 100 have a common source and common drain characteristic, that is, the sources of all fets 110 in all fet arrays 100 are connected to the power Vdd, and the drains of all fets 110 in all fet arrays 100 are connected to the load of the heterogeneous module layer 200, so as to supply power to the integrated module. The power supply current is dynamically distributed by the field effect transistor array 100 of the heterogeneous power layer 300 and then supplies power to each integrated module; by distributively arranging the parallel field effect transistor arrays 100 on the heterogeneous power supply layer 300, the power supply current can be effectively and uniformly distributed in the chip, and the heat balance inside the chip is realized. By using the positive temperature coefficient effect of the on-resistance of the fet 110, when the power of a certain region is high and the temperature rises, the on-resistance of the fet 100 in the region increases, the current passing through the fet decreases, and the current passing through the fet 100 distributed in the region with a lower temperature increases, so that the temperature rises, thereby achieving the effect of dynamic power adjustment and thermal balance. In order to better realize the power adjustment and heat balance functions of the fet arrays 100, a plurality of fet arrays 100 are uniformly distributed in the heterogeneous power layer 300 without affecting the power supply performance. The FET 110 may be a Planar FET, FinFET, GAAFET, or other FET having a positive temperature coefficient effect on its on-resistance. In addition, each control and regulation port 120 is connected to a control and regulation module 410 on the control layer 400, and the output voltage of each control and regulation port 120 is adjusted by the control and regulation module 410, so that the current flowing through the fet array 100 can be controlled, and programmable control of power can be realized.
In some embodiments, a multi-channel digital-to-analog converter is disposed inside the control and regulation module 410, and the number of channels of the digital-to-analog converter matches the number of control and regulation ports 120, and the two are in one-to-one correspondence. By varying the output voltage of each channel of the digital-to-analog converter, the output voltage of each control regulation port 120 can be adjusted, thereby varying the current capacity of each fet array 100.
In some embodiments, the control and regulation module 410 is electrically connected to external pins of the multi-module heterogeneous chip. The control and regulation module 410 is programmed by an external pin through a communication protocol (such as SPI, IIC, etc.), so as to change the output voltage of each channel of the digital-to-analog converter, thereby implementing programmable control of the power supply.
According to the multi-module heterogeneous chip of the embodiment of the invention, the plurality of field effect transistor arrays 100 are uniformly distributed in the heterogeneous power layer 300 in a distributed manner by using the positive temperature coefficient effect of the on-resistance of the field effect transistors 110, when the power of a certain region is larger and the temperature is increased, the on-resistance of the field effect transistors 110 in the region is increased, the passing current is reduced, and the passing current of the field effect transistors 110 distributed in the region with lower temperature is increased, so that the temperature is increased, and the effects of dynamic power adjustment and temperature balance are achieved. Meanwhile, the gate voltage of the fet array 100 is changed by controlling the adjusting module 400 and the adjusting port, and the magnitude of the current flowing through the fet array 100 can be controlled, so as to implement programmable control of power.
In the description herein, references to the description of "one embodiment," "a further embodiment," "some specific embodiments," or "some examples," etc., mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. An array of field effect transistors, comprising:
the field-effect transistors are connected in parallel, the source electrodes of the field-effect transistors are connected with a power supply, the drain electrodes of the field-effect transistors are connected with a load, and the on-resistance of the field-effect transistors has a positive temperature coefficient effect;
and the control and regulation port is electrically connected with the grid electrode of each field effect transistor respectively.
2. The fet array of claim 1, wherein the control and regulation port is electrically connected to a control and regulation module within a multi-module heterogeneous chip.
3. A multi-module heterogeneous chip is characterized by comprising a heterogeneous module layer, a heterogeneous power supply layer and a control layer which are electrically connected in sequence; wherein:
a plurality of integrated modules are arranged on the heterogeneous module layer;
the heterogeneous power supply layer is provided with a plurality of field effect tube arrays according to claim 1 or 2, and power supplied by the heterogeneous power supply layer supplies power to the integrated module through the field effect tube arrays;
and the control layer is provided with a control and regulation module which is electrically connected with the control and regulation port of each field effect transistor array respectively.
4. The multi-module heterogeneous chip of claim 3, wherein the heterogeneous module layer, the heterogeneous power layer and the control layer are stacked.
5. The multi-module heterogeneous chip according to claim 4, wherein the heterogeneous module layer is electrically connected to the heterogeneous power layer through a through silicon via, and the heterogeneous power layer is electrically connected to the control layer through a through silicon via.
6. The multi-module heterogeneous chip according to claim 3, wherein a plurality of the integrated modules are disposed on the heterogeneous module layer by a three-dimensional heterogeneous integration technique.
7. The multi-module heterogeneous chip according to claim 3, wherein a digital-to-analog converter is disposed inside the control and regulation module, and the digital-to-analog converter has a plurality of channels corresponding to the control and regulation ports of the plurality of field effect transistor arrays one to one.
8. The multi-module heterogeneous chip according to claim 7, wherein the control and regulation module is electrically connected to external pins of the multi-module heterogeneous chip.
9. The multi-module heterogeneous chip according to claim 3, wherein the integrated module is an MCU or MMIC or MEMS.
10. The multi-module heterogeneous chip according to claim 3, wherein the FET is a Planar FET or a FinFET or a GAAFET.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210413896.0A CN114825296A (en) | 2022-04-19 | 2022-04-19 | Field-effect tube array and multi-module heterogeneous chip |
| PCT/CN2022/142871 WO2023202147A1 (en) | 2022-04-19 | 2022-12-28 | Field-effect transistor array and multi-module heterogeneous chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210413896.0A CN114825296A (en) | 2022-04-19 | 2022-04-19 | Field-effect tube array and multi-module heterogeneous chip |
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| CN114825296A true CN114825296A (en) | 2022-07-29 |
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| CN202210413896.0A Pending CN114825296A (en) | 2022-04-19 | 2022-04-19 | Field-effect tube array and multi-module heterogeneous chip |
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| WO (1) | WO2023202147A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023202147A1 (en) * | 2022-04-19 | 2023-10-26 | 珠海欧比特宇航科技股份有限公司 | Field-effect transistor array and multi-module heterogeneous chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010283973A (en) * | 2009-06-04 | 2010-12-16 | Denso Corp | Driving device for power-switching element |
| CN105550432A (en) * | 2015-12-11 | 2016-05-04 | 格科微电子（上海）有限公司 | Three-dimensional integrated circuit chip and power network layout method thereof |
| WO2017221292A1 (en) * | 2016-06-20 | 2017-12-28 | 三菱電機株式会社 | Parallel drive circuit |
| CN210007689U (en) * | 2019-05-29 | 2020-01-31 | 湖州顺为能源科技有限公司 | Hot plug circuit based on field effect transistor |
| CN113507201A (en) * | 2021-06-03 | 2021-10-15 | 北京自动化控制设备研究所 | Parallel SiC-MoS drive circuit of servo system |
| CN114825296A (en) * | 2022-04-19 | 2022-07-29 | 珠海欧比特宇航科技股份有限公司 | Field-effect tube array and multi-module heterogeneous chip |
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- 2022-04-19 CN CN202210413896.0A patent/CN114825296A/en active Pending
- 2022-12-28 WO PCT/CN2022/142871 patent/WO2023202147A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023202147A1 (en) * | 2022-04-19 | 2023-10-26 | 珠海欧比特宇航科技股份有限公司 | Field-effect transistor array and multi-module heterogeneous chip |
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