CN114824086A - Transistor and preparation method thereof - Google Patents

Transistor and preparation method thereof Download PDF

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Publication number
CN114824086A
CN114824086A CN202210447049.6A CN202210447049A CN114824086A CN 114824086 A CN114824086 A CN 114824086A CN 202210447049 A CN202210447049 A CN 202210447049A CN 114824086 A CN114824086 A CN 114824086A
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CN
China
Prior art keywords
channel region
electrode
semiconductor channel
substrate layer
transistor
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CN202210447049.6A
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Chinese (zh)
Inventor
林艳霞
曹宇
张志勇
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Beijing Yuanxin Carbon Based Integrated Circuit Research Institute
Peking University
Beijing Hua Tan Yuan Xin Electronics Technology Co Ltd
Original Assignee
Beijing Yuanxin Carbon Based Integrated Circuit Research Institute
Peking University
Beijing Hua Tan Yuan Xin Electronics Technology Co Ltd
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Application filed by Beijing Yuanxin Carbon Based Integrated Circuit Research Institute, Peking University, Beijing Hua Tan Yuan Xin Electronics Technology Co Ltd filed Critical Beijing Yuanxin Carbon Based Integrated Circuit Research Institute
Priority to CN202210447049.6A priority Critical patent/CN114824086A/en
Publication of CN114824086A publication Critical patent/CN114824086A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning

Abstract

The present disclosure provides a transistor, comprising: a substrate layer; the semiconductor channel region is formed above the substrate layer; the semiconductor device comprises a first electrode and a second electrode, wherein the first electrode and the second electrode are formed in a semiconductor channel region and are separated by a preset distance; the gate dielectric layer is at least formed on the opposite surfaces of the first electrode and the second electrode; the gate electrode is arranged between the first electrode and the second electrode, and gate dielectric layers are arranged between the gate electrode and the first electrode and between the gate electrode and the second electrode; the substrate layer is provided with a concave part, the concave part is provided with a bottom surface, a preset distance is reserved between the lower surface of the semiconductor channel region and the bottom surface of the concave part, or part of the semiconductor channel region is in contact with the bottom surface of the concave part. The present disclosure also provides a method of fabricating a transistor.

Description

Transistor and preparation method thereof
Technical Field
The present disclosure relates to a transistor and a method of fabricating the same.
Background
In the preparation process of the carbon nanotube transistor, due to the adoption of various chemical processes, impurity residues exist between the carbon nanotube and the substrate, and the impurities are difficult to remove by conventional means such as annealing, chemical cleaning and the like, so that the performance of the transistor is adversely affected.
In particular, high-purity and high-density semiconductor carbon nanotube arrays required by practical application of integrated circuits at present are prepared by separating high-purity semiconductor carbon nanotube solutions based on a polymer wrapping method and forming high-density arrays on substrates treated by a chemical process by a self-assembly method. Due to the polymer wrapped on the surface of the carbon nano tube and the modifier on the substrate, key parameters of the transistor such as on-state current, transconductance and threshold voltage are adversely affected.
Therefore, it is desirable to design a transistor structure and a method for fabricating the same to solve the above-mentioned problems.
Disclosure of Invention
In order to solve one of the above technical problems, the present disclosure provides a transistor and a method for fabricating the same.
According to an aspect of the present disclosure, there is provided a transistor including:
a substrate layer;
a semiconductor channel region formed above the substrate layer;
the first electrode and the second electrode are formed in the semiconductor channel region, and a preset distance is reserved between the first electrode and the second electrode;
the gate dielectric layer is formed on at least part of the upper surface of the semiconductor channel region; and
the gate electrode is arranged between the first electrode and the second electrode, and gate dielectric layers are arranged between the gate electrode and the first electrode and between the gate electrode and the second electrode;
wherein the substrate layer is formed with a recess having a bottom surface, a preset distance is provided between a lower surface of the semiconductor channel region and the bottom surface of the recess, or a portion of the semiconductor channel region is in contact with the bottom surface of the recess.
According to the transistor of at least one embodiment of the present disclosure, a lower surface of the semiconductor channel region is planar or substantially planar so that the semiconductor channel region has a predetermined distance from a bottom surface of the recess.
According to the transistor of at least one embodiment of the present disclosure, a portion of the lower surface of the semiconductor channel region is protruded downward such that the portion of the semiconductor channel region is located within the recess.
According to a transistor of at least one embodiment of the present disclosure, the recess portion is formed in a region between the first electrode and the second electrode.
According to a transistor of at least one embodiment of the present disclosure, the recess portion extends at least beyond one end portion of the semiconductor channel region in a length direction of the first and second electrodes.
According to the transistor of at least one embodiment of the present disclosure, the gate dielectric layer covers the surfaces of the first electrode and the second electrode which are opposite to each other and the semiconductor channel region between the first electrode and the second electrode.
According to the transistor of at least one embodiment of the present disclosure, after the semiconductor channel region is disposed on the substrate layer, the substrate material under the semiconductor channel region is etched to a certain depth by an etching process so as to form the recess.
According to the transistor of at least one embodiment of the present disclosure, when a substrate material below a semiconductor channel region is etched through an etching process, the semiconductor channel region is at least partially separated from the substrate layer, and the recess is formed at the separation of the semiconductor channel region and the substrate layer.
In a transistor according to at least one embodiment of the present disclosure, the semiconductor channel region is deformed so that a portion of the semiconductor channel region enters the recess.
According to a transistor of at least one embodiment of the present disclosure, a material forming the semiconductor channel region includes a semiconductor metal oxide, a two-dimensional transition metal sulfide, graphene, a carbon nanotube, an organic semiconductor, black phosphorus, or molybdenum disulfide.
According to another aspect of the present disclosure, there is provided a method of manufacturing a transistor, including:
preparing a substrate layer and cleaning the substrate layer;
preparing a semiconductor channel region on the substrate layer;
preparing a first electrode and a second electrode on the semiconductor channel region;
etching the substrate layer below the semiconductor channel region to a certain depth so as to form a concave part on the substrate layer;
preparing a gate dielectric layer on the first electrode, the second electrode and the semiconductor channel region;
and preparing a gate electrode on the gate dielectric layer.
According to another aspect of the present disclosure, there is provided a method of manufacturing a transistor, including:
preparing a substrate layer and cleaning the substrate layer;
preparing a semiconductor channel region on the substrate layer;
etching the substrate layer below the semiconductor channel region to a certain depth so as to form a concave part on the substrate layer;
preparing a first electrode and a second electrode on the semiconductor channel region;
preparing a gate dielectric layer on the first electrode, the second electrode and the semiconductor channel region;
and preparing a gate electrode on the gate dielectric layer.
A method of fabricating a transistor according to at least one embodiment of the present disclosure includes:
after the substrate layer is formed with the recess, the semiconductor channel region above the recess is subjected to solvent cleaning and/or annealing.
According to the manufacturing method of the transistor of at least one embodiment of the present disclosure, the material forming the semiconductor channel region includes a semiconductor metal oxide, a two-dimensional transition metal sulfide, graphene, a carbon nanotube, an organic semiconductor, black phosphorus, or molybdenum disulfide.
According to another aspect of the present disclosure, there is provided a transistor prepared by the above-described method of preparing a transistor.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.
Fig. 1 is a schematic structural diagram of a transistor according to one embodiment of the present disclosure.
Fig. 2A and 2B are schematic structural views of a substrate layer according to one embodiment of the present disclosure.
Fig. 3A and 3B are schematic structural views of a semiconductor channel region according to an embodiment of the present disclosure.
Fig. 4A and 4B are schematic structural views of source-drain electrodes according to an embodiment of the present disclosure.
Fig. 5A and 5B are schematic structural views of a recess according to an embodiment of the present disclosure.
Fig. 6A and 6B are schematic structural views of a gate dielectric layer according to an embodiment of the present disclosure.
Fig. 7A and 7B are schematic structural views of a gate electrode according to one embodiment of the present disclosure.
Fig. 8 is an electron micrograph of a transistor according to one embodiment of the present disclosure.
Fig. 9 is a performance curve of a transistor according to one embodiment of the present disclosure.
Fig. 10 is a flow chart of a method of fabricating a transistor according to one embodiment of the present disclosure.
Fig. 11 is a flow chart of a method of fabricating a transistor according to another embodiment of the present disclosure.
Fig. 12 is a flow chart of a method of fabricating a transistor according to another embodiment of the present disclosure.
Fig. 13 is a flow chart of a method of fabricating a transistor according to another embodiment of the present disclosure.
The reference numbers in the figures are in particular:
100 transistor
110 substrate layer
111 concave part
120 semiconductor channel region
130 first electrode
140 second electrode
150 gate dielectric layer
160 a gate electrode.
Detailed Description
The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.
The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.
When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.
For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "sidewall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a transistor according to one embodiment of the present disclosure.
As shown in fig. 1, a transistor 100 of the present disclosure includes a substrate layer 110, a semiconductor channel region 120, a first electrode 130, a second electrode 140, a gate dielectric layer 150, a gate electrode 160, and the like, where the substrate layer 110 is preferably a silicon wafer covered with silicon dioxide, and of course, the substrate layer 110 may also be made of glass, quartz, ITO, or flexible PI, PET, or the like.
A semiconductor channel region 120 is formed above the substrate layer 110. Useful materials for the semiconductor channel region 120 in the present disclosure may include: semiconductor metal oxides, two-dimensional transition metal sulfides, graphene, carbon nanotubes, organic semiconductors, black phosphorus, molybdenum disulfide, and other two-dimensional semiconductor materials, and preferably carbon nanotubes, such as a network or ordered high purity carbon nanotube film can be deposited. That is, the transistor and the manufacturing method provided by the present disclosure are not only suitable for carbon nanotubes, but also can be widely applied to other low dimensional materials. As a rule, contamination may occur in the case of catalysts contained in CVD growth, in the case of dispersed purification using some polymers, and may affect the performance of the transistor, as long as it is not a directly grown bulk material, including transfer during the process of obtaining a semiconductor material.
The first electrode 130 and the second electrode 140 are formed in the semiconductor channel region, so that the first electrode 130 and the second electrode 140 are formed as a source electrode and a drain electrode of the transistor 100. In the present disclosure, the first electrode 130 and the second electrode 140 are spaced apart by a predetermined distance.
Preferably, the semiconductor channel region 120 includes a first direction (X direction) and a second direction (Y direction), and taking the semiconductor channel region 120 as a thin film formed by carbon nanotubes as an example, the first direction may be a longitudinal direction of the semiconductor channel region 120, that is, a row direction of the thin film of carbon nanotubes, and the second direction may be a direction perpendicular to the first direction.
In the first direction, the first electrode 130 and the second electrode 140 are located at a position between both end portions of the semiconductor channel region 120.
On the other hand, the length direction of the first electrode 130 and the second electrode 140 is the second direction, and preferably, the first electrode 130 and the second electrode 140 may be disposed in parallel or substantially in parallel. The two ends of the first electrode 130 and the second electrode 140 in the length direction extend beyond the semiconductor channel region 120, and at least partial surfaces of the first electrode 130 and the second electrode 140 are in contact with the upper surface of the substrate layer 110, so that the first electrode 130 and the second electrode 140 can play a role in fixing the semiconductor channel region 120, and when the substrate layer 110 is formed with the recess 111, the semiconductor channel region 120 can be prevented from being peeled off from the surface of the substrate layer 110 under an etching process.
Preferably, both ends of the first electrode 130 and the second electrode 140 extend beyond the semiconductor channel region 120 along the second direction, so that the semiconductor channel region 120 can be more firmly fixed to the substrate layer 110 by the first electrode 130 and the second electrode 140.
In the present disclosure, the first electrode 130 and the second electrode 140 may be formed of any suitable material or combination of materials. Examples of materials that may be used for the first electrode 130 and the second electrode 140 include, but are not limited to: metals, conductive or semiconductive metal oxides, conductive or semiconductive polymers, doped semiconductors, graphene, and two-dimensional (2D) semiconductors, among others. As a preferred example, the material of the first electrode 130 and the second electrode 140 may be one or more of metal materials such as Ti (titanium), Pd (palladium), or Au (gold).
Since the first electrode 130 and the second electrode 140 are disposed in parallel or substantially in parallel and the first electrode 130 and the second electrode 140 extend to a certain height, the first electrode 130 and the second electrode 140 have opposite surfaces, and the gate dielectric layer 150 is formed on at least the opposite surfaces of the first electrode 130 and the second electrode 140.
Preferably, the gate dielectric layer 150 is formed on at least a portion of the upper surface of the semiconductor channel region 120, and in one embodiment, the gate dielectric layer 150 covers the surfaces of the first electrode 130 and the second electrode 140 opposite to each other and the semiconductor channel region 120 between the first electrode 130 and the second electrode 140, so that the gate dielectric layer 150 forms a receiving space, and the gate electrode 160 is disposed in the receiving space.
In another embodiment, considering that the gate dielectric layer 150 is obtained by ALD growth, the gate dielectric layer 150 can also be grown on the lower surface of the semiconductor channel region 120, even on the inner surface of the recess of the substrate layer 110, and formed in a gate-all-around structure. However, those skilled in the art will appreciate that the gate dielectric layer 150 existing under the semiconductor channel region cannot be gated due to the inability to apply a voltage, and only the gate dielectric layer 150 above the semiconductor channel region can be gated.
In the present disclosure, examples of materials for forming the gate dielectric layer 150 include, but are not limited to: SiO 2 2 、HfO 2 、ZrO 2 、Ta 2 O 5 、Y 2 O 3 、Nb 2 O 5 、Al 2 O 3 、TiO 2 、CeO 2 、In 2 O 3 、RuO2、MgO、SrO、B 2 O 3 、SnO 2 、PbO、PbO 2 、Pb 3 O 4 、V 2 O 3 、La 2 O 3 、Pr 2 O 3 、Sb 2 O 3 、Sb 2 O 5 CaO, etc.
The gate electrode 160 is disposed between the first electrode 130 and the second electrode 140, and a gate dielectric layer 150 is disposed between the gate electrode 160 and the first electrode 130, and between the gate electrode 160 and the second electrode 140, that is, the gate electrode 160 and the first electrode 130 cannot be directly connected in an electrically conductive manner, and correspondingly, the gate electrode 160 and the second electrode 140 cannot be directly connected in an electrically conductive manner. In one implementation, the gate electrode 160 may be made of a metal material such as Ti, Al, Sc, Ni, Pd, Au, Pt, or a stacked structure of metal materials.
In the present disclosure, the substrate layer 110 is formed with a recess 111, the recess 111 has a bottom surface, a preset distance is provided between a lower surface of the semiconductor channel region 120 and the bottom surface of the recess 111, or a portion of the semiconductor channel region 120 is in contact with the bottom surface of the recess 111.
On one hand, the lower surface of the semiconductor channel region 120 is planar or substantially planar, so that the semiconductor channel region 120 has a predetermined distance from the bottom surface of the recess, that is, the semiconductor channel region 120 is not deformed or is deformed by a small amount after the recess 111 is formed in the substrate layer 110. On the other hand, when the deformation of the semiconductor channel region 120 is large, a portion of the lower surface of the semiconductor channel region 120 protrudes downward so that the portion of the semiconductor channel region 120 is located within the recess 111. More preferably, the semiconductor channel region 120 is deformed such that a portion of the semiconductor channel region 120 enters the recess 111.
Further, when at least a portion of the semiconductor channel region 120 is located in the recess 111, the semiconductor channel region 120 and the bottom surface of the recess 111 may also be spaced apart.
In the present disclosure, the recess 111 is formed in a region between the first electrode 130 and the second electrode 140, and more preferably, the recess 111 extends at least beyond one end of the semiconductor channel region 120 in a length direction of the first electrode 130 and the second electrode 140, that is, the recess 111 extends at least beyond one end of the semiconductor channel region 120 in the second direction.
More preferably, after the semiconductor channel region 120 is disposed on the substrate layer 110, the substrate material under the semiconductor channel region 120 is etched by an etching process to a certain depth so as to form the recess 111. Furthermore, when the substrate material under the semiconductor channel region 120 is etched by an etching process, the semiconductor channel region 120 is at least partially separated from the substrate layer 110, and the recess 111 is formed at the separation of the semiconductor channel region 120 from the substrate layer 110.
Fig. 10 is a flow chart of a method of fabricating a transistor according to one embodiment of the present disclosure.
According to another aspect of the present disclosure, as shown in fig. 10, a method for manufacturing a transistor 100 is provided, and in the present disclosure, the method for manufacturing a transistor 100 may manufacture the transistor 100 described above, which includes:
substrate layer 110 is prepared and substrate layer 110 is cleaned, resulting in substrate layer 110 as shown in fig. 2A and 2B, where fig. 2A is a side view of substrate layer 110 and fig. 2B is a top view of substrate layer 110.
Preparing a semiconductor channel region 120 on the substrate layer 110; specifically, when the semiconductor channel region is prepared, a layer of semiconductor material is laid on the substrate layer 110, for example, a carbon nanotube film or a two-dimensional semiconductor material, or a carbon nanotube, a nanowire or a two-dimensional transition metal sulfide is laid; photolithography and etching are then used to pattern the active region of the layer of semiconductor material, thereby forming the semiconductor channel region 120. The semiconductor channel region 120 obtained by this step is shown in fig. 3A and 3B, where fig. 3A is a side view of the substrate layer 110 and the semiconductor channel region 120, and fig. 3B is a top view of the substrate layer 110 and the semiconductor channel region 120.
Preparing a first electrode 130 and a second electrode 140 on the semiconductor channel region 120; specifically, the first electrode 130 and the second electrode 140 may be formed by thin film growth, photolithography, and etching, and thus the first electrode 130 and the second electrode 140 may be formed as source-drain electrodes. The source-drain electrodes obtained through this step are shown in fig. 4A and 4B, where fig. 4A is a side view of the source-drain electrodes, and fig. 4B is a top view of the source-drain electrodes.
For example, when the transistor is a MOS transistor, the first electrode 130 may serve as a source of the MOS transistor, and the second electrode 140 may serve as a drain of the MOS transistor. As another implementation form, the first electrode 130 may also serve as a drain of a MOS transistor, and the second electrode 140 serves as a source of the MOS transistor. The region between the first electrode 130 and the second electrode 140 is the channel length of the MOS transistor.
In the present disclosure, after the source-drain electrodes are formed again, a recess is formed on the substrate layer 110. Specifically, the substrate layer 110 underlying the semiconductor channel region 120 may be etched to a certain depth through a photolithography and wet etching process so as to form the recess 111 in the substrate layer 110. Furthermore, forming the recess 111 after forming the first electrode 130 and the second electrode 140 can prevent the semiconductor channel region 120 from being peeled off from the surface of the substrate layer 110 by a wet etching process. Through this process, the semiconductor material of the semiconductor channel region 120 may be in a floating state or may fall on the exposed new substrate surface (the bottom surface of the recess) due to deformation.
Fig. 12 is a flow chart of a method of fabricating a transistor according to another embodiment of the present disclosure.
As shown in fig. 12, the semiconductor channel region 120 above the recess 111 is processed, and specifically, the semiconductor channel region 120 above the recess 111 of the substrate layer 110 is solvent-cleaned and/or annealed by annealing and/or solvent-cleaning to further remove impurities on the surface of the semiconductor channel region 120.
The recessed portion 111 obtained in this step is shown in fig. 5A and 5B, where fig. 5A is a side view of the recessed portion 111 and fig. 5B is a plan view of the recessed portion 111.
Preparing a gate dielectric layer 150 on the first electrode 130, the second electrode 140 and the semiconductor channel region 120; specifically, the gate dielectric layer 150 may be prepared by photolithography, atomic layer deposition or other methods, and the gate dielectric layer 150 may be HfO 2 ，Y 2 O 3 Or other insulating layer, and etching to form the gate dielectric region.
The gate dielectric layer 150 obtained by this step is shown in fig. 6A and 6B, where fig. 6A is a side view of the gate dielectric layer 150 and fig. 6B is a top view of the gate dielectric layer 150.
And preparing a gate electrode 160 on the gate dielectric layer 150. Specifically, the gate electrode 160 may be formed by using thin film growth, photolithography, and etching, and the gate electrode 160 obtained by this step is shown in fig. 7A and 7B, where fig. 7A is a side view of the gate electrode 160 and fig. 7B is a top view of the gate electrode.
Fig. 11 is a flow chart of a method of fabricating a transistor according to another embodiment of the present disclosure.
As another implementation form, as shown in fig. 11, before the first electrode and the second electrode are prepared on the semiconductor channel region, the substrate layer below the semiconductor channel region is etched to a certain depth so as to form a recess in the substrate layer.
Fig. 13 is a flow chart of a method of fabricating a transistor according to another embodiment of the present disclosure.
Further, as shown in fig. 13, after the recess 111 is formed, the recess 111 may be subjected to annealing, solvent cleaning, or the like.
According to another aspect of the present disclosure, a transistor 100 is provided, the transistor 100 being prepared by the above-mentioned method for preparing the transistor 100.
As shown in fig. 8 and 9, fig. 8(a) is a photo of the surface of the silicon dioxide substrate layer after etching; FIG. 8(b) is a Scanning Electron Microscope (SEM) photograph of the transistor after silicon dioxide on the surface of the substrate layer is etched; fig. 8(c) a transistor projection electron microscope (TEM) photograph of the substrate layer after the silicon dioxide layer surface is etched.
FIG. 9(a) a transfer characteristic curve of a carbon nanotube transistor before and after etching of a surface of a substrate layer; (b) counting results of the on-state current of the carbon nanotube transistor before and after the surface of the substrate layer is etched; (c) counting the on-state current (the over-grid voltage is-1V) of the carbon nanotube transistor before and after the surface of the substrate layer is etched; (d) counting results of threshold voltages of the carbon nanotube transistor before and after the surface of the substrate layer is etched; (e) the hysteresis statistical result of the carbon nanotube transistor before and after the surface of the substrate layer is etched; (f) counting results of the on-off ratio of the carbon nanotube transistor before and after the surface of the substrate layer is etched; (g) counting results of subthreshold slope swing of the carbon nanotube transistor before and after the etching of the surface of the substrate layer; (h) and (5) conducting cross conduction statistical results of the carbon nano tube transistor before and after the surface of the substrate layer is etched.
As shown in fig. 8 and 9, in the transistor and the method for manufacturing the same of the present disclosure, impurities on the contact surface between the semiconductor channel region 120 and the substrate layer 110 can be reduced, and thus the electrical performance of the transistor is improved, compared to the prior art, the transistor of the present disclosure has an on-state current increased by 35%, a hysteresis decreased by 59%, an on-off ratio increased by 6%, a subthreshold slope swing decreased by 11%, and a transconductance increased by 33%.
In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims (10)

1. A transistor, comprising:
a substrate layer;
a semiconductor channel region formed above the substrate layer;
the first electrode and the second electrode are formed in the semiconductor channel region, and a preset distance is reserved between the first electrode and the second electrode;
the gate dielectric layer is formed on at least part of the upper surface of the semiconductor channel region; and
the gate electrode is arranged between the first electrode and the second electrode, and gate dielectric layers are arranged between the gate electrode and the first electrode and between the gate electrode and the second electrode;
wherein the substrate layer is formed with a recess having a bottom surface, a preset distance is provided between a lower surface of the semiconductor channel region and the bottom surface of the recess, or a portion of the semiconductor channel region is in contact with the bottom surface of the recess.
2. The transistor of claim 1, wherein a lower surface of the semiconductor channel region is planar or substantially planar such that the semiconductor channel region is a predetermined distance from a bottom surface of the recess.
3. The transistor of claim 1, wherein a portion of a lower surface of the semiconductor channel region is downwardly convex such that the portion of the semiconductor channel region is located within the recess.
4. The transistor of claim 1, wherein the recess is formed in a region between the first and second electrodes.
5. The transistor of claim 1, wherein the recess extends beyond at least one end of the semiconductor channel region along a length of the first and second electrodes.
6. The transistor of any of claims 1-5, wherein said gate dielectric layer covers opposing surfaces of said first and second electrodes and a semiconductor channel region between said first and second electrodes;
optionally, after the semiconductor channel region is arranged on the substrate layer, etching the substrate material below the semiconductor channel region by an etching process to a certain depth so as to form the recess;
optionally, when a substrate material below the semiconductor channel region is etched through an etching process, the semiconductor channel region is at least partially separated from the substrate layer, and the recess is formed at the separation of the semiconductor channel region and the substrate layer;
optionally, the semiconductor channel region is deformed so that a portion of the semiconductor channel region enters the recess;
optionally, the material forming the semiconductor channel region comprises a semiconductor metal oxide, a two-dimensional transition metal sulfide, graphene, a carbon nanotube, a carbon nanowire, a semiconductor nanowire, an organic semiconductor, black phosphorus, or molybdenum disulfide.
7. A method for manufacturing a transistor, comprising:
preparing a substrate layer and cleaning the substrate layer;
preparing a semiconductor channel region on the substrate layer;
preparing a first electrode and a second electrode on the semiconductor channel region;
etching the substrate layer below the semiconductor channel region to a certain depth so as to form a concave part on the substrate layer;
preparing a gate dielectric layer on the first electrode, the second electrode and the semiconductor channel region;
and preparing a gate electrode on the gate dielectric layer.
8. A method for manufacturing a transistor, comprising:
preparing a substrate layer and cleaning the substrate layer;
preparing a semiconductor channel region on the substrate layer;
etching the substrate layer below the semiconductor channel region to a certain depth so as to form a concave part on the substrate layer;
preparing a first electrode and a second electrode on the semiconductor channel region;
preparing a gate dielectric layer on the first electrode, the second electrode and the semiconductor channel region;
and preparing a gate electrode on the gate dielectric layer.
9. The method for manufacturing a transistor according to claim 7 or 8, comprising:
after a sunken part is formed on the substrate layer, carrying out solvent cleaning and/or annealing on a semiconductor channel region above the sunken part;
optionally, the material forming the semiconductor channel region comprises a semiconductor metal oxide, a two-dimensional transition metal sulfide, graphene, a carbon nanotube, an organic semiconductor, black phosphorus or molybdenum disulfide.
10. A transistor produced by the method for producing a transistor according to any one of claims 11 to 14.
CN202210447049.6A 2022-04-26 2022-04-26 Transistor and preparation method thereof Pending CN114824086A (en)

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