CN114822616A - Sensitive amplifier, memory and working method of memory - Google Patents
Sensitive amplifier, memory and working method of memory Download PDFInfo
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- CN114822616A CN114822616A CN202110065296.5A CN202110065296A CN114822616A CN 114822616 A CN114822616 A CN 114822616A CN 202110065296 A CN202110065296 A CN 202110065296A CN 114822616 A CN114822616 A CN 114822616A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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Abstract
A sense amplifier, comprising: a first transistor, a gate of which is connected to a first bit line of the memory cell; a gate of the second transistor is connected with a second bit line of the memory cell, and a source of the second transistor is connected with a source of the first transistor; a third transistor, wherein the grid electrode of the third transistor is connected with the second bit line of the storage unit, the source electrode of the third transistor is connected with the source electrode of the second transistor, and the threshold voltages of the first transistor, the second transistor and the third transistor are different; the mirror image unit comprises a mirrored end, a first mirror image end and a second mirror image end, wherein the mirrored end is connected with the drain electrode of the first transistor, the first mirror image end is connected with the drain electrode of the second transistor, and the second mirror image end is connected with the drain electrode of the third transistor; and the detection unit is connected with the first mirror image end of the mirror image unit and the second mirror image end of the mirror image unit. The sense amplifier circuit improves the overall read-write speed of the memory.
Description
Technical Field
The invention relates to the technical field of semiconductor memories, in particular to a sense amplifier, a memory and a working method of the memory.
Background
With the popularization of electronic devices such as mobile phones, tablet computers, and personal computers, semiconductor memory technology has also been rapidly developed. Memories such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) have been widely used in various electronic devices due to their advantages of high density, low power consumption, low price, and the like.
A Sense Amplifier (SA) is an important component of a semiconductor memory, and is mainly used for amplifying a small signal on a bit line to perform a read or write operation.
As technology advances, semiconductor memories are decreasing in size, and in this case, the output of the sense amplifier is affected by the mismatch of transistors in the sense amplifier, thereby affecting the performance of the memory.
Disclosure of Invention
The invention aims to provide a sense amplifier, a memory and a working method of the memory so as to improve the performance of the memory.
In order to solve the above technical problem, a technical solution of the present invention provides a sense amplifier, including: a first transistor, a gate of which is connected to a first bit line of a memory cell; a second transistor, a gate of which is connected to a second bit line of the memory cell, and a source of which is connected to a source of the first transistor; a third transistor, a gate of the third transistor being connected to the second bit line of the memory cell, a source of the third transistor being connected to a source of the second transistor, a source of the first transistor, a source of the second transistor, and a source of the third transistor being coupled to a ground voltage node, threshold voltages of the first transistor, the second transistor, and the third transistor being different; the mirror image unit comprises a mirrored end, a first mirror image end and a second mirror image end, wherein the mirrored end is connected with the drain electrode of the first transistor, the first mirror image end is connected with the drain electrode of the second transistor, and the second mirror image end is connected with the drain electrode of the third transistor; and the first mirror image end of the mirror image unit is connected with the detection unit, and the second mirror image end of the mirror image unit is connected with the detection unit.
Optionally, the mirrored end of the mirroring unit includes: and a source of the fourth transistor is connected to the power supply voltage node, a drain of the fourth transistor is connected to the drain of the first transistor, and a gate of the fourth transistor is connected to the drain of the first transistor.
Optionally, the first mirroring end of the mirroring unit includes: a fifth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the second transistor, and a gate of which is connected to a gate of the fourth transistor; the detection unit is connected with the drain electrode of the fifth transistor.
Optionally, the second mirroring end of the mirroring unit includes: a sixth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the third transistor, and a gate of which is connected to a gate of the fourth transistor and a gate of the fifth transistor; the detection unit is connected with the drain electrode of the sixth transistor.
Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; the sixth transistor is a P-type transistor.
Optionally, the mirror cell further includes a voltage input node, and the voltage input node is connected to a power supply voltage node.
Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
Optionally, the method further includes: a first inverter and a second inverter; the first inverter is connected with the first mirror image end of the mirror image unit and the detection unit; and the second inverter is connected with the second mirror image end of the mirror image unit and the detection unit.
Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; the third transistor is an N-type transistor.
Optionally, the method further includes: and a seventh transistor having a drain connected to the second bit line of the memory cell and a gate of the third transistor, a source connected to the ground voltage node, and a gate connected to the gate of the third transistor.
Optionally, the seventh transistor is an N-type transistor.
Optionally, the method further includes: and a drain of the eighth transistor is connected to the second bit line of the memory cell and a gate of the second transistor, a source of the eighth transistor is connected to the ground voltage node, and a gate of the eighth transistor is connected to the gate of the second transistor.
Optionally, the eighth transistor is an N-type transistor.
Optionally, the method further includes: and a ninth transistor, a drain of which is connected to the first bit line of the memory cell and a gate of the first transistor, a source of which is connected to the ground voltage node, and a gate of which is connected to the gate of the first transistor.
Optionally, the ninth transistor is an N-type transistor.
Optionally, the method further includes: and a tenth transistor having a drain connected to the source of the first transistor, the source of the second transistor, and the source of the third transistor, and a source connected to a ground voltage node.
Optionally, the tenth transistor is an N-type transistor.
Correspondingly, the technical scheme of the invention also provides a memory, which comprises: a number of memory cells including a first bit line and a second bit line; a sense amplifier connected to the memory cell, the sense amplifier comprising: a first transistor, a gate of which is connected to a first bit line of a memory cell; a second transistor, a gate of which is connected to a second bit line of the memory cell, and a source of which is connected to a source of the first transistor; a third transistor, a gate of the third transistor being connected to the second bit line of the memory cell, a source of the third transistor being connected to a source of the second transistor, a source of the first transistor, a source of the second transistor, and a source of the third transistor being coupled to a ground voltage node, threshold voltages of the first transistor, the second transistor, and the third transistor being different; the mirror image unit comprises a mirrored end, a first mirror image end and a second mirror image end, wherein the mirrored end is connected with the drain electrode of the first transistor, the first mirror image end is connected with the drain electrode of the second transistor, and the second mirror image end is connected with the drain electrode of the third transistor; the first mirror image end of the mirror image unit is connected with the detection unit, and the second mirror image end of the mirror image unit is connected with the detection unit; and a reading unit connected with the sensitive amplifier.
Optionally, the mirrored end of the mirroring unit includes: and a source of the fourth transistor is connected to the power supply voltage node, a drain of the fourth transistor is connected to the drain of the first transistor, and a gate of the fourth transistor is connected to the drain of the first transistor.
Optionally, the first mirroring end of the mirroring unit includes: a fifth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the second transistor, and a gate of which is connected to a gate of the fourth transistor; the detection unit is connected with the drain electrode of the fifth transistor.
Optionally, the second mirroring end of the mirroring unit includes: a sixth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the third transistor, and a gate of which is connected to a gate of the fourth transistor and a gate of the fifth transistor; the detection unit is connected with the drain electrode of the sixth transistor.
Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; the sixth transistor is a P-type transistor.
Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
Optionally, the sense amplifier further includes: a first inverter and a second inverter; the first inverter is connected with the first mirror image end of the mirror image unit and the detection unit; and the second inverter is connected with the second mirror image end of the mirror image unit and the detection unit.
Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; the third transistor is an N-type transistor.
Correspondingly, the technical scheme of the invention also provides a working method of the memory, which comprises the following steps: providing a memory, the memory comprising: a number of memory cells including a first bit line and a second bit line; a sense amplifier connected to the memory cell, the sense amplifier comprising: a first transistor, a gate of which is connected to a first bit line of a memory cell; a second transistor, a gate of which is connected to a second bit line of the memory cell, and a source of which is connected to a source of the first transistor; a third transistor, a gate of the third transistor being connected to the second bit line of the memory cell, a source of the third transistor being connected to a source of the second transistor, a source of the first transistor, a source of the second transistor, and a source of the third transistor being coupled to a ground voltage node, threshold voltages of the first transistor, the second transistor, and the third transistor being different; the mirror image unit comprises a mirrored end, a first mirror image end and a second mirror image end, wherein the mirrored end is connected with the drain electrode of the first transistor, the first mirror image end is connected with the drain electrode of the second transistor, and the second mirror image end is connected with the drain electrode of the third transistor; the first mirror image end of the mirror image unit is connected with the detection unit, and the second mirror image end of the mirror image unit is connected with the detection unit; a reading unit connected with the sensitive amplifier; comparing the current magnitude of the mirror image end and the first mirror image end and outputting a first signal; comparing the current magnitude of the mirror image end and the current magnitude of the second mirror image end and outputting a second signal; the detection unit compares and judges the first signal and the second signal to obtain a comparison result; and the reading unit acquires a reading cycle corresponding to the comparison result to read the memory.
Optionally, the method for reading the memory by the reading unit acquiring the corresponding read cycle includes: if the first signal is the same as the second signal, reading the memory by adopting a first reading period; and if the first signal is different from the second signal, reading the memory by adopting a second reading period.
Optionally, the first read cycle is smaller than the second read cycle.
Optionally, the mirrored end of the mirroring unit includes: and a source of the fourth transistor is connected to the power supply voltage node, a drain of the fourth transistor is connected to the drain of the first transistor, and a gate of the fourth transistor is connected to the drain of the first transistor.
Optionally, the first mirroring end of the mirroring unit includes: a fifth transistor, a source of which is connected to the power supply voltage node, a drain of which is connected to a drain of the second transistor, and a gate of which is connected to a gate of the fourth transistor; the detection unit is connected with the drain electrode of the fifth transistor.
Optionally, the second mirroring end of the mirroring unit includes: a sixth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the third transistor, and a gate of which is connected to a gate of the fourth transistor and a gate of the fifth transistor; the detection unit is connected with the drain electrode of the sixth transistor.
Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; the sixth transistor is a P-type transistor.
Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
Optionally, the sense amplifier further includes: a first inverter and a second inverter; the first inverter is connected with the first mirror image end of the mirror image unit and the detection unit; and the second inverter is connected with the second mirror image end of the mirror image unit and the detection unit.
Optionally, the method for comparing the current magnitudes of the mirror terminal and the first mirror terminal includes: if the current of the mirror image end is larger than the current of the first mirror image end, the first signal is '0'; if the current of the mirror image end is smaller than the current of the first mirror image end, the first signal is 1.
Optionally, the method for comparing the current magnitudes of the mirror terminal and the second mirror terminal includes: if the current of the mirror image end is larger than the current of the second mirror image end, the second signal is '0'; if the current of the mirror image end is smaller than the current of the second mirror image end, the second signal is '1'.
Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; the third transistor is an N-type transistor.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the sense amplifier in the technical scheme of the invention, the threshold voltages of the first transistor, the second transistor and the third transistor are different, and the first transistor, the second transistor and the third transistor are respectively connected with the mirrored end, the first mirrored end and the second mirrored end of the mirroring unit. The threshold voltages of the first transistor, the second transistor and the third transistor are different, so that the currents of the first transistor, the second transistor and the third transistor are different, the detection unit can detect and compare signals output by the first mirror image end of the mirror image unit and the second mirror image end of the mirror image unit, and the strength state of the storage unit connected with the sensitive amplifier is judged according to the correctness of the comparison result, so that different reading periods are adopted to read the storage units with different strength states, the integral reading and writing speed of the memory is improved, and the performance of the memory is improved.
Further, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor. The current flowing through the first transistor is the same as the current of the mirrored end of the mirror unit, after the current of the mirrored end of the mirror unit is mirrored to the first mirrored end of the mirror unit and the second mirrored end of the mirror unit, the current of the first mirrored end of the mirror unit is leveled with the current flowing through the second transistor, and the current of the second mirrored end of the mirror unit is leveled with the current flowing through the third transistor, so that the detection unit can judge the strong and weak states of the storage unit connected with the sense amplifier by judging whether the change states of the signal of the first mirrored end of the mirror unit and the signal of the second mirrored end of the mirror unit are consistent or not. If the signal of the first mirror image end of the mirror image unit is the same as the signal of the second mirror image end of the mirror image unit, the storage unit connected with the sensitive amplifier is a unit with stronger driving; and if the signal of the first mirror image end of the mirror image unit is different from the signal of the second mirror image end of the mirror image unit, the storage unit connected with the sensitive amplifier is a unit with weaker drive.
Drawings
FIG. 1 is a circuit diagram of a voltage-mode sense amplifier in one embodiment;
FIG. 2 is a circuit schematic of a sense amplifier in an embodiment of the invention;
FIG. 3 is a circuit schematic of a sense amplifier in another embodiment of the invention;
FIG. 4 is a flow chart of a method for operating a memory according to an embodiment of the present invention.
Detailed Description
As described in the background, existing memory performance has yet to be improved.
Specifically, taking SRAM (dynamic random access memory) as an example, the performance of SRAM depends on the read operation. The driving capability of the memory cells in the memory array is inconsistent, and in order to ensure the correctness of the read operation of the SRAM, when the word line is turned off (the sense amplifier is turned on), the bit line swing of all the memory cells in the memory array is ensured to exceed the offset voltage of the sense amplifier, so the read delay of the memory array depends on the memory cell which is driven the weakest in the memory array. The driving capability of the memory cell is weak, so the read delay of the memory cell is relatively large.
In the whole read operation path, the word line driving circuit and the output driving module correspond to a common logic circuit, and the time delay can be reduced by adopting a low-threshold device, increasing the size of a transistor and the like; for the delay of the memory array, the magnitude of the delay is determined by the driving capability of the memory cell, and compared with the logic circuit, the driving capability of the SRAM memory cell is relatively weak, so that the discharge delay is relatively large.
When the power supply voltage is reduced to a near threshold value region, the statistical distribution of the discharge delay of the bit lines of the memory cells has an obvious tailing phenomenon due to local process fluctuation, the discharge delay of most of the memory cells is distributed within 15ns, only a few weakly-driven memory cells are distributed between 15ns and 30ns, the weakly-driven memory cells enable the design margin to be further increased along with the reduction of the power supply voltage, the performance of the memory array is sharply reduced due to the excessively pessimistic design margin, and therefore the overall performance of the SRAM is sharply reduced.
Fig. 1 is a circuit of a voltage-type sense amplifier, which is adapted to analyze the effect of transistor mismatch caused by local process fluctuation on the output of the sense amplifier.
Referring to fig. 1, the sense amplifier includes: a first transistor M1; a second transistor M2, the drain of the second transistor M2 is connected with the gate of the first transistor M1, and the drain of the first transistor M1 is connected with the gate of the second transistor M2; a third transistor M3 and a fourth transistor M4, a source of the third transistor M3 is connected to a source of the fourth transistor M4, a drain of the third transistor M3 is connected to a drain of the fourth transistor M4, a source of the third transistor M3 and a source of the fourth transistor M4 are connected to the power supply voltage node VDD, a drain of the third transistor M3 and a drain of the fourth transistor M4 are connected to a drain of the first transistor M1, and a gate of the fourth transistor M4 is connected to a gate of the first transistor M1; a fifth transistor M5 and a sixth transistor M6, wherein the source of the fifth transistor M5 is connected to the source of the sixth transistor M6, the drain of the fifth transistor M5 is connected to the drain of the sixth transistor M6, the source of the fifth transistor M5 and the source of the sixth transistor M6 are connected to the power supply voltage node VDD, the drain of the fifth transistor M5 and the drain of the sixth transistor M6 are connected to the drain of the second transistor M2, and the gate of the sixth transistor M6 is connected to the gate of the second transistor M2; a seventh transistor M7, wherein the drain of the seventh transistor M7 is connected to the source of the first transistor M1, and the gate of the seventh transistor M7 is connected to the first bit line IN of the memory cell; an eighth transistor M8, a drain of the eighth transistor M8 is connected to the source of the second transistor M2, a gate of the eighth transistor M8 is connected to the second bit line INB of the memory cell, and a source of the eighth transistor M8 is connected to the source of the seventh transistor M7; a ninth transistor M9, wherein a drain of the ninth transistor M9 is connected to a source of the eighth transistor M8 and a source of the seventh transistor M7, a source of the ninth transistor M9 is connected to the ground voltage node, a gate of the third transistor M3 is connected to a gate of the ninth transistor M9, and a gate of the sixth transistor M6 is connected to a gate of the ninth transistor M9.
In the sense amplifier, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are P-type transistors; the first transistor M1, the second transistor M2, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are N-type transistors.
IN the sense amplifier, when the driving force of the memory cell is weak due to local process fluctuation, a voltage difference Vinput between the seventh transistor M7 connected to the first bit line IN and the eighth transistor M8 connected to the second bit line INB is small, and the Vinput may be smaller than the offset voltage Voffset of the sense amplifier, which may cause an error IN the output result of the sense amplifier, thereby affecting the performance of the memory.
In order to solve the above problems, an embodiment of the present invention provides a sense amplifier, a memory, and a method for operating a memory, in which threshold voltages of a first transistor, a second transistor, and a third transistor in the sense amplifier are different, and the first transistor, the second transistor, and the third transistor are respectively connected to a mirrored end, a first mirrored end, and a second mirrored end of a mirroring unit. The threshold voltages of the first transistor, the second transistor and the third transistor are different, so that the currents of the first transistor, the second transistor and the third transistor are different, the detection unit can detect and compare signals output by the first mirror image end of the mirror image unit and the second mirror image end of the mirror image unit, and the strength state of the storage unit connected with the sensitive amplifier is judged according to the correctness of the comparison result, so that different reading periods are adopted to read the storage units with different strength states, the integral reading and writing speed of the memory is improved, and the performance of the memory is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
FIG. 2 is a circuit diagram of a sense amplifier according to an embodiment of the present invention.
Referring to fig. 2, the sense amplifier includes: a first transistor M1, the gate of the first transistor M1 is connected with the first bit line BL of the memory cell;
a second transistor M2, the gate of the second transistor M2 being connected to the second bit line BLB of the memory cell, the source of the second transistor M2 being connected to the source of the first transistor M1;
a third transistor M3, wherein the gate of the third transistor M3 is connected to the second bit line BLB of the memory cell, the source of the third transistor M3 is connected to the source of the second transistor M2, the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3 are coupled to the ground voltage node, and the threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different;
a mirror cell including a mirrored terminal connected to the drain of the first transistor M1, a first mirror terminal connected to the drain of the second transistor M2, and a second mirror terminal connected to the drain of the third transistor M3;
and the first mirror image end of the mirror image unit is connected with the detection unit T, and the second mirror image end of the mirror image unit is connected with the detection unit T.
In this embodiment, the mirrored end of the mirroring unit includes: a fourth transistor M4, a source of the fourth transistor M4 is connected to the power supply voltage node VDD, a drain of the fourth transistor M4 is connected to the drain of the first transistor M1, and a gate of the fourth transistor M4 is connected to the drain of the first transistor M1.
In this embodiment, the first mirroring end of the mirroring unit includes: a fifth transistor M5, a source of the fifth transistor M5 being connected to the power supply voltage node VDD, a drain of the fifth transistor M5 being connected to the drain of the second transistor M2, a gate of the fifth transistor M5 being connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.
In this embodiment, the second mirroring end of the mirroring unit includes: a sixth transistor M6, a source of the sixth transistor M6 being connected to the power supply voltage node VDD, a drain of the sixth transistor M6 being connected to the drain of the third transistor M3, a gate of the sixth transistor M6 being connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.
In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; the sixth transistor M6 is a P-type transistor.
The threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the currents of the first transistor M1, the second transistor M2 and the third transistor M3 are different, the detection unit T can detect and compare signals output by the first mirror image end of the mirror image unit and the second mirror image end of the mirror image unit, and the strength state of the storage unit connected with the sense amplifier is judged according to the correctness of the comparison result, so that different reading cycles are subsequently adopted to read the storage units with different strength states, the overall reading and writing speed of the memory is increased, and the performance of the memory is improved.
In the present embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.
Therefore, the current flowing through the first transistor M1 is the same as the current at the mirrored end of the mirror unit, after the current at the mirrored end of the mirror unit is mirrored to the first mirrored end of the mirror unit and the second mirrored end of the mirror unit, the current at the first mirrored end of the mirror unit is leveled with the current flowing through the second transistor M2, and the current at the second mirrored end of the mirror unit is leveled with the current flowing through the third transistor M3, so that the detection unit can judge the strong and weak states of the memory cell connected with the sense amplifier by judging whether the change states of the signal at the first mirrored end of the mirror unit and the signal at the second mirrored end of the mirror unit are the same or not. If the signal of the first mirror image end of the mirror image unit is the same as the signal of the second mirror image end of the mirror image unit, the storage unit connected with the sensitive amplifier is a unit with stronger driving; and if the signal of the first mirror image end of the mirror image unit is different from the signal of the second mirror image end of the mirror image unit, the storage unit connected with the sensitive amplifier is a unit with weaker drive.
In this embodiment, the mirror unit further includes a voltage input node (not labeled), and the voltage input node is connected to a power supply voltage node VDD.
In this embodiment, the method further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected with a first mirror terminal of the mirror unit and the detection unit T; the second inverter B2 is connected to the second mirror terminal of the mirror cell and the sensing cell T.
The first inverter B1 is configured to shape the current signal output by the first mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, which is a first signal, for the detection unit T to recognize and determine. The first signal is a comparison result of the current magnitude of the mirror image terminal and the first mirror image terminal.
The second inverter B2 is configured to shape the current signal output by the second mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, which is a second signal and is convenient for the detection unit T to recognize and determine. The second signal is a comparison result of the current magnitude of the mirror image terminal and the second mirror image terminal.
The first signal is 0 or 1; the second signal is 0 or 1.
In other embodiments, the circuit can also not include the first inverter and the second inverter.
In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; the third transistor M3 is an N-type transistor.
In this embodiment, the method further includes: a seventh transistor M7, a drain of the seventh transistor M7 is connected to the second bit line BLB of the memory cell and a gate of the third transistor M3, a source of the seventh transistor M7 is connected to the ground voltage node, and a gate of the seventh transistor M7 is connected to a gate of the third transistor M3.
The seventh transistor M7 functions as a mirror current, and the current flowing through the seventh transistor M7 mirrors to the third transistor M3.
In other embodiments, the circuit can also not include the seventh transistor M7.
In this embodiment, the seventh transistor M7 is an N-type transistor.
In this embodiment, the method further includes: and an eighth transistor M8, a drain of the eighth transistor M8 is connected to the second bit line BLB of the memory cell and a gate of the second transistor M2, a source of the eighth transistor M8 is connected to the ground voltage node, and a gate of the eighth transistor M8 is connected to a gate of the second transistor M2.
The eighth transistor M8 functions as a mirror current, and the current flowing through the eighth transistor M8 is mirrored to the second transistor M2.
In other embodiments, the circuit can also not include the eighth transistor M8.
In this embodiment, the eighth transistor M8 is an N-type transistor.
In this embodiment, the method further includes: a ninth transistor M9, a drain of the ninth transistor M9 is connected to the first bit line BL of the memory cell and to the gate of the first transistor M1, a source of the ninth transistor M9 is connected to the ground voltage node, and a gate of the ninth transistor M9 is connected to the gate of the first transistor M1.
The ninth transistor M9 functions as a mirror current, and the current flowing through the ninth transistor M9 is mirrored to the first transistor M1.
In other embodiments, the circuit can also not include the ninth transistor M9.
In this embodiment, the ninth transistor M9 is an N-type transistor.
In this embodiment, the method further includes: and a tenth transistor M10, a drain of the tenth transistor M10 being connected to the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3, and a source of the tenth transistor M10 being connected to the ground voltage node.
In this embodiment, the tenth transistor M10 is an N-type transistor.
The tenth transistor M10 serves as a switch for turning on the sense amplifier circuit.
FIG. 3 is a circuit diagram of a sense amplifier according to another embodiment of the invention.
Referring to fig. 3, the sense amplifier includes: a first transistor M1, the gate of the first transistor M1 is connected with the first bit line BL of the memory cell;
a second transistor M2, the gate of the second transistor M2 being connected to the second bit line BLB of the memory cell, the source of the second transistor M2 being connected to the source of the first transistor M1;
a third transistor M3, wherein the gate of the third transistor M3 is connected to the second bit line BLB of the memory cell, the source of the third transistor M3 is connected to the source of the second transistor M2, the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3 are coupled to the ground voltage node, and the threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different;
a mirror cell including a mirrored terminal connected to the drain of the first transistor M1, a first mirror terminal connected to the drain of the second transistor M2, and a second mirror terminal connected to the drain of the third transistor M3;
and the first mirror image end of the mirror image unit is connected with the detection unit T, and the second mirror image end of the mirror image unit is connected with the detection unit T.
In this embodiment, the mirrored end of the mirroring unit includes: a fourth transistor M4, a source of the fourth transistor M4 is connected to the power supply voltage node VDD, a drain of the fourth transistor M4 is connected to the drain of the first transistor M1, and a gate of the fourth transistor M4 is connected to the drain of the first transistor M1.
In this embodiment, the first mirror end of the mirror unit includes: a fifth transistor M5, a source of the fifth transistor M5 being connected to the power supply voltage node VDD, a drain of the fifth transistor M5 being connected to the drain of the second transistor M2, a gate of the fifth transistor M5 being connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.
In this embodiment, the second mirror end of the mirror unit includes: a sixth transistor M6, a source of the sixth transistor M6 being connected to the power supply voltage node VDD, a drain of the sixth transistor M6 being connected to the drain of the third transistor M3, a gate of the sixth transistor M6 being connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.
In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; the sixth transistor M6 is a P-type transistor.
The threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the currents of the first transistor M1, the second transistor M2 and the third transistor M3 are different, the detection unit T can detect and compare signals output by the first mirror image end of the mirror image unit and the second mirror image end of the mirror image unit, and judge the strong and weak states of the storage unit connected with the sense amplifier according to the correctness of the comparison result, so that different reading cycles are subsequently adopted to read the storage units with different strong and weak states, the overall reading and writing speed of the memory is increased, and the performance of the memory is improved.
In the present embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.
Therefore, the current flowing through the first transistor M1 is the same as the current at the mirrored end of the mirror unit, after the current at the mirrored end of the mirror unit is mirrored to the first mirrored end of the mirror unit and the second mirrored end of the mirror unit, the current at the first mirrored end of the mirror unit is leveled with the current flowing through the second transistor M2, and the current at the second mirrored end of the mirror unit is leveled with the current flowing through the third transistor M3, so that the detection unit can judge the strong and weak states of the memory cell connected with the sense amplifier by judging whether the change states of the signal at the first mirrored end of the mirror unit and the signal at the second mirrored end of the mirror unit are the same or not. If the signal of the first mirror image end of the mirror image unit is the same as the signal of the second mirror image end of the mirror image unit, the storage unit connected with the sensitive amplifier is a unit with stronger driving; and if the signal of the first mirror image end of the mirror image unit is different from the signal of the second mirror image end of the mirror image unit, the storage unit connected with the sensitive amplifier is a unit with weaker drive.
In this embodiment, the mirror cell further includes a voltage input node (not labeled), which is connected to a power supply voltage node VDD.
In this embodiment, the method further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected with a first mirror terminal of the mirror unit and the detection unit T; the second inverter B2 is connected to the second mirror terminal of the mirror cell and the sensing cell T.
The first inverter B1 is configured to shape the current signal output by the first mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, which is a first signal, for the detection unit T to recognize and determine. The first signal is a comparison result of the current magnitude of the mirror image terminal and the first mirror image terminal.
The second inverter B2 is configured to shape the current signal output by the second mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, which is a second signal and is convenient for the detection unit T to recognize and determine. The second signal is a comparison result of the current magnitude of the mirror image terminal and the second mirror image terminal.
The first signal is 0 or 1; the second signal is 0 or 1.
In other embodiments, the circuit can also not include the first inverter and the second inverter.
In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; the third transistor M3 is an N-type transistor.
In this embodiment, the method further includes: and a tenth transistor M10, a drain of the tenth transistor M10 being connected to the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3, and a source of the tenth transistor M10 being connected to the ground voltage node.
In this embodiment, the tenth transistor M10 is an N-type transistor.
The tenth transistor M10 serves as a switch for turning on the sense amplifier circuit.
FIG. 4 is a flow chart of a method for operating a memory according to an embodiment of the present invention.
Referring to fig. 4, the working method of the memory includes:
s100: a memory is provided.
The memory includes: a number of memory cells including a first bit line and a second bit line; a sense amplifier connected to the memory cell; and a reading unit connected with the sensitive amplifier.
S101: and comparing the current magnitude of the mirror image end with that of the first mirror image end and outputting a first signal, and comparing the current magnitude of the mirror image end with that of the second mirror image end and outputting a second signal.
S102: and comparing and judging the first signal of the first mirror image end and the second signal of the second mirror image end to obtain a comparison result.
S103: and the reading unit acquires a reading cycle corresponding to the comparison result to read the memory.
Referring to fig. 2, the circuit of the sense amplifier includes: a first transistor M1, the gate of the first transistor M1 is connected with the first bit line BL of the memory cell; a second transistor M2, the gate of the second transistor M2 being connected to the second bit line BLB of the memory cell, the source of the second transistor M2 being connected to the source of the first transistor M1; a third transistor M3, wherein the gate of the third transistor M3 is connected to the second bit line BLB of the memory cell, the source of the third transistor M3 is connected to the source of the second transistor M2, the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3 are coupled to the ground voltage node, and the threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different; a mirror cell including a mirrored terminal connected to the drain of the first transistor M1, a first mirror terminal connected to the drain of the second transistor M2, and a second mirror terminal connected to the drain of the third transistor M3; and the first mirror image end of the mirror image unit is connected with the detection unit T, and the second mirror image end of the mirror image unit is connected with the detection unit T.
In this embodiment, the method for reading the memory by the reading unit acquiring the corresponding read cycle includes: if the first signal is the same as the second signal, reading the memory by adopting a first reading period; and if the first signal is different from the second signal, reading the memory by adopting a second reading period.
In this embodiment, the first read cycle is less than the second read cycle.
If the first signal is the same as the second signal, the storage unit connected with the sensitive amplifier is a unit with stronger driving, and the storage unit with stronger driving is read by adopting a shorter first reading period; and if the first signal is different from the second signal, the memory cell connected with the sensitive amplifier is a weak-driving cell, and the weak-driving memory cell is read by adopting a longer second reading period. Different reading cycles are adopted to read the memory cells with different strengths and weaknesses in the memory array, so that the overall reading and writing speed of the memory is improved, and the performance of the memory is improved.
In this embodiment, the second read cycle may be multiple.
In this embodiment, the mirrored end of the mirroring unit includes: a fourth transistor M4, a source of the fourth transistor M4 is connected to the power supply voltage node VDD, a drain of the fourth transistor M4 is connected to the drain of the first transistor M1, and a gate of the fourth transistor M4 is connected to the drain of the first transistor M1.
In this embodiment, the first mirror end of the mirror unit includes: a fifth transistor M5, a source of the fifth transistor M5 being connected to the power supply voltage node VDD, a drain of the fifth transistor M5 being connected to the drain of the second transistor M2, a gate of the fifth transistor M5 being connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.
In this embodiment, the second mirroring end of the mirroring unit includes: a sixth transistor M6, a source of the sixth transistor M6 being connected to the power supply voltage node VDD, a drain of the sixth transistor M6 being connected to the drain of the third transistor M3, a gate of the sixth transistor M6 being connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.
In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; the sixth transistor M6 is a P-type transistor.
The threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the currents of the first transistor M1, the second transistor M2 and the third transistor M3 are different, the detection unit T can detect and compare signals output by the first mirror image end of the mirror image unit and the second mirror image end of the mirror image unit, and judge the strong and weak states of the storage unit connected with the sense amplifier according to the correctness of the comparison result, so that different reading cycles are subsequently adopted to read the storage units with different strong and weak states, the overall reading and writing speed of the memory is increased, and the performance of the memory is improved.
In the present embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.
Therefore, the current flowing through the first transistor M1 is the same as the current at the mirrored end of the mirror unit, after the current at the mirrored end of the mirror unit is mirrored to the first mirrored end of the mirror unit and the second mirrored end of the mirror unit, the current at the first mirrored end of the mirror unit is leveled with the current flowing through the second transistor M2, and the current at the second mirrored end of the mirror unit is leveled with the current flowing through the third transistor M3, so that the detection unit can judge the strong and weak states of the memory cell connected with the sense amplifier by judging whether the change states of the signal at the first mirrored end of the mirror unit and the signal at the second mirrored end of the mirror unit are the same or not. If the signal of the first mirror image end of the mirror image unit is the same as the signal of the second mirror image end of the mirror image unit, the storage unit connected with the sensitive amplifier is a unit with stronger driving; and if the signal of the first mirror image end of the mirror image unit is different from the signal of the second mirror image end of the mirror image unit, the storage unit connected with the sensitive amplifier is a unit with weaker drive.
In this embodiment, the sense amplifier further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected with a first mirror terminal of the mirror unit and the detection unit T; the second inverter B2 is connected to the second mirror terminal of the mirror cell and the sensing cell T.
The first inverter B1 is configured to shape the current signal output by the first mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, which is a first signal, for the detection unit T to recognize and determine. The first signal is a comparison result of the current magnitude of the mirror image terminal and the first mirror image terminal. The second inverter B2 is configured to shape the current signal output by the second mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, which is a second signal and is convenient for the detection unit T to recognize and determine. The second signal is a comparison result of the current magnitude of the mirror image terminal and the second mirror image terminal.
The first signal is 0 or 1; the second signal is 0 or 1.
The method for comparing the current magnitude of the mirror terminal and the current magnitude of the first mirror terminal comprises the following steps: if the current of the mirror image terminal is larger than the current of the first mirror image terminal, the first signal is 0; if the current of the mirror image end is smaller than the current of the first mirror image end, the first signal is 1.
The method for comparing the current magnitude of the mirror terminal and the current magnitude of the second mirror terminal comprises the following steps: if the current of the mirror image end is larger than the current of the second mirror image end, the second signal is '0'; if the current of the mirror image end is smaller than the current of the second mirror image end, the second signal is '1'.
In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; the third transistor M3 is an N-type transistor.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (37)
1. A sense amplifier, comprising:
a first transistor, a gate of which is connected to a first bit line of the memory cell;
a second transistor, a gate of which is connected to a second bit line of the memory cell, and a source of which is connected to a source of the first transistor;
a third transistor, a gate of the third transistor being connected to the second bit line of the memory cell, a source of the third transistor being connected to a source of the second transistor, a source of the first transistor, a source of the second transistor, and a source of the third transistor being coupled to a ground voltage node, threshold voltages of the first, second, and third transistors being different;
the mirror image unit comprises a mirrored end, a first mirror image end and a second mirror image end, wherein the mirrored end is connected with the drain electrode of the first transistor, the first mirror image end is connected with the drain electrode of the second transistor, and the second mirror image end is connected with the drain electrode of the third transistor;
and the first mirror image end of the mirror image unit is connected with the detection unit, and the second mirror image end of the mirror image unit is connected with the detection unit.
2. The sense amplifier of claim 1 wherein the mirrored end of the mirror cell comprises: and a source of the fourth transistor is connected to the power supply voltage node, a drain of the fourth transistor is connected to the drain of the first transistor, and a gate of the fourth transistor is connected to the drain of the first transistor.
3. The sense amplifier of claim 2 wherein the mirror cell first mirror terminal comprises: a fifth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the second transistor, and a gate of which is connected to a gate of the fourth transistor; the detection unit is connected with the drain electrode of the fifth transistor.
4. The sense amplifier of claim 3 wherein the mirror cell second mirror terminal comprises: a sixth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the third transistor, and a gate of which is connected to a gate of the fourth transistor and a gate of the fifth transistor; the detection unit is connected with the drain electrode of the sixth transistor.
5. The sense amplifier of claim 4 wherein the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; the sixth transistor is a P-type transistor.
6. The sense amplifier of claim 1 wherein the mirroring unit further comprises a voltage input node connected to a supply voltage node.
7. The sense amplifier of claim 1, wherein a threshold voltage of the first transistor is greater than a threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
8. The sense amplifier of claim 1, further comprising: a first inverter and a second inverter; the first inverter is connected with the first mirror image end of the mirror image unit and the detection unit; and the second inverter is connected with the second mirror image end of the mirror image unit and the detection unit.
9. The sense amplifier of claim 1 wherein the first transistor is an N-type transistor; the second transistor is an N-type transistor; the third transistor is an N-type transistor.
10. The sense amplifier of claim 1, further comprising: and a seventh transistor having a drain connected to the second bit line of the memory cell and a gate of the third transistor, a source connected to the ground voltage node, and a gate connected to the gate of the third transistor.
11. The sense amplifier of claim 10 wherein the seventh transistor is an N-type transistor.
12. The sense amplifier of claim 1, further comprising: and a drain of the eighth transistor is connected to the second bit line of the memory cell and a gate of the second transistor, a source of the eighth transistor is connected to the ground voltage node, and a gate of the eighth transistor is connected to the gate of the second transistor.
13. The sense amplifier of claim 12 wherein the eighth transistor is an N-type transistor.
14. The sense amplifier of claim 1, further comprising: and a ninth transistor, a drain of which is connected to the first bit line of the memory cell and a gate of the first transistor, a source of which is connected to the ground voltage node, and a gate of which is connected to the gate of the first transistor.
15. The sense amplifier of claim 14 wherein the ninth transistor is an N-type transistor.
16. The sense amplifier of claim 1, further comprising: and a tenth transistor having a drain connected to the source of the first transistor, the source of the second transistor, and the source of the third transistor, and a source connected to a ground voltage node.
17. The sense amplifier of claim 16 wherein the tenth transistor is an N-type transistor.
18. A memory, comprising:
a number of memory cells including a first bit line and a second bit line;
a sense amplifier connected to the memory cell, the sense amplifier comprising:
a first transistor, a gate of which is connected to a first bit line of a memory cell; a second transistor, a gate of which is connected to a second bit line of the memory cell, and a source of which is connected to a source of the first transistor; a third transistor, a gate of the third transistor being connected to the second bit line of the memory cell, a source of the third transistor being connected to a source of the second transistor, a source of the first transistor, a source of the second transistor, and a source of the third transistor being coupled to a ground voltage node, threshold voltages of the first transistor, the second transistor, and the third transistor being different; the mirror image unit comprises a mirrored end, a first mirror image end and a second mirror image end, wherein the mirrored end is connected with the drain electrode of the first transistor, the first mirror image end is connected with the drain electrode of the second transistor, and the second mirror image end is connected with the drain electrode of the third transistor; the first mirror image end of the mirror image unit is connected with the detection unit, and the second mirror image end of the mirror image unit is connected with the detection unit;
and a reading unit connected with the sensitive amplifier.
19. The memory of claim 18, wherein the mirrored unit mirrored end comprises: and a source of the fourth transistor is connected to the power supply voltage node, a drain of the fourth transistor is connected to the drain of the first transistor, and a gate of the fourth transistor is connected to the drain of the first transistor.
20. The memory of claim 19, wherein the mirroring unit first mirroring terminal comprises: a fifth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the second transistor, and a gate of which is connected to a gate of the fourth transistor; the detection unit is connected with the drain electrode of the fifth transistor.
21. The memory of claim 20, wherein the mirroring unit second mirroring terminal comprises: a sixth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the third transistor, and a gate of which is connected to a gate of the fourth transistor and a gate of the fifth transistor; the detection unit is connected with the drain electrode of the sixth transistor.
22. The memory of claim 21, wherein the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; the sixth transistor is a P-type transistor.
23. The memory of claim 18, wherein a threshold voltage of the first transistor is greater than a threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
24. The memory of claim 18, wherein the sense amplifier further comprises: a first inverter and a second inverter; the first inverter is connected with the first mirror image end of the mirror image unit and the detection unit; and the second inverter is connected with the second mirror image end of the mirror image unit and the detection unit.
25. The memory of claim 18, wherein the first transistor is an N-type transistor; the second transistor is an N-type transistor; the third transistor is an N-type transistor.
26. A method of operating a memory, comprising:
providing a memory, the memory comprising:
a number of memory cells including a first bit line and a second bit line;
a sense amplifier connected to the memory cell, the sense amplifier comprising: a first transistor, a gate of which is connected to a first bit line of a memory cell; a second transistor, a gate of which is connected to a second bit line of the memory cell, and a source of which is connected to a source of the first transistor; a third transistor, a gate of the third transistor being connected to the second bit line of the memory cell, a source of the third transistor being connected to a source of the second transistor, a source of the first transistor, a source of the second transistor, and a source of the third transistor being coupled to a ground voltage node, threshold voltages of the first, second, and third transistors being different; the mirror image unit comprises a mirrored end, a first mirror image end and a second mirror image end, wherein the mirrored end is connected with the drain electrode of the first transistor, the first mirror image end is connected with the drain electrode of the second transistor, and the second mirror image end is connected with the drain electrode of the third transistor; the first mirror image end of the mirror image unit is connected with the detection unit, and the second mirror image end of the mirror image unit is connected with the detection unit;
a reading unit connected with the sensitive amplifier;
comparing the current magnitude of the mirror image end with that of the first mirror image end and outputting a first signal, and comparing the current magnitude of the mirror image end with that of the second mirror image end and outputting a second signal;
the detection unit compares and judges the first signal and the second signal to obtain a comparison result;
and the reading unit acquires a reading cycle corresponding to the comparison result to read the memory.
27. The method for operating a memory according to claim 26, wherein the method for reading the memory by the reading unit acquiring the corresponding read cycle comprises: if the first signal is the same as the second signal, reading the memory by adopting a first reading period; and if the first signal is different from the second signal, reading the memory by adopting a second reading period.
28. The method of operating a memory of claim 27 wherein the first read cycle is less than the second read cycle.
29. The method of memory operation of claim 26, wherein the mirrored unit mirrored end comprises: and a source of the fourth transistor is connected to the power supply voltage node, a drain of the fourth transistor is connected to the drain of the first transistor, and a gate of the fourth transistor is connected to the drain of the first transistor.
30. The method of claim 29, wherein the mirroring unit first mirroring terminal comprises: a fifth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the second transistor, and a gate of which is connected to a gate of the fourth transistor; the detection unit is connected with the drain electrode of the fifth transistor.
31. The method of claim 30, wherein the mirroring unit second mirroring terminal comprises: a sixth transistor, a source of which is connected to a power supply voltage node, a drain of which is connected to a drain of the third transistor, and a gate of which is connected to a gate of the fourth transistor and a gate of the fifth transistor; the detection unit is connected with the drain electrode of the sixth transistor.
32. The method according to claim 31, wherein the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; the sixth transistor is a P-type transistor.
33. The method of operating a memory as claimed in claim 26, wherein the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
34. The method of operating a memory of claim 26, wherein the sense amplifier further comprises: a first inverter and a second inverter; the first inverter is connected with the first mirror image end of the mirror image unit and the detection unit; and the second inverter is connected with the second mirror image end of the mirror image unit and the detection unit.
35. The method of operating a memory of claim 26, wherein the comparing the magnitudes of the currents at the mirror terminal and the first mirror terminal comprises: if the current of the mirror image end is larger than the current of the first mirror image end, the first signal is '0'; if the current of the mirror image end is smaller than the current of the first mirror image end, the first signal is 1.
36. The method of operating a memory of claim 26, wherein the comparing the magnitudes of the currents at the mirror terminal and the second mirror terminal comprises: if the current of the mirror image end is larger than the current of the second mirror image end, the second signal is '0'; if the current of the mirror image terminal is smaller than the current of the second mirror image terminal, the second signal is 1.
37. The method of operating a memory of claim 26, wherein the first transistor is an N-type transistor; the second transistor is an N-type transistor; the third transistor is an N-type transistor.
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