CN114822616A - Sense amplifier, memory and working method of memory - Google Patents
Sense amplifier, memory and working method of memory Download PDFInfo
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- CN114822616A CN114822616A CN202110065296.5A CN202110065296A CN114822616A CN 114822616 A CN114822616 A CN 114822616A CN 202110065296 A CN202110065296 A CN 202110065296A CN 114822616 A CN114822616 A CN 114822616A
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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Abstract
一种灵敏放大器，包括：第一晶体管，第一晶体管的栅极与存储单元的第一位线连接；第二晶体管，第二晶体管的栅极与存储单元的第二位线连接，第二晶体管的源极与第一晶体管的源极连接；第三晶体管，第三晶体管的栅极与存储单元的第二位线连接，第三晶体管的源极与第二晶体管的源极连接，第一晶体管、第二晶体管和第三晶体管的阈值电压不同；镜像单元，包括被镜像端、第一镜像端和第二镜像端，被镜像端与第一晶体管的漏极连接，第一镜像端与第二晶体管的漏极连接，第二镜像端与第三晶体管的漏极连接；检测单元，检测单元与镜像单元的第一镜像端以及镜像单元的第二镜像端连接。所述灵敏放大器电路提升了存储器的整体读写速度。
A sense amplifier, comprising: a first transistor, whose gate is connected to a first bit line of a storage unit; a second transistor, whose gate is connected to a second bit line of the storage unit, and the second transistor The source of the first transistor is connected to the source of the first transistor; the third transistor, the gate of the third transistor is connected to the second bit line of the memory cell, the source of the third transistor is connected to the source of the second transistor, the first transistor The threshold voltages of the second transistor and the third transistor are different; the mirror unit includes a mirrored terminal, a first mirrored terminal and a second mirrored terminal, the mirrored terminal is connected to the drain of the first transistor, and the first mirrored terminal is connected to the second mirrored terminal. The drain of the transistor is connected, the second mirror terminal is connected to the drain of the third transistor; the detection unit is connected to the first mirror terminal of the mirror unit and the second mirror terminal of the mirror unit. The sense amplifier circuit improves the overall read and write speed of the memory.
Description
技术领域technical field
本发明涉及半导体存储器技术领域，具体涉及一种灵敏放大器、存储器和存储器的工作方法。The present invention relates to the technical field of semiconductor memory, in particular to a sense amplifier, a memory and a working method of the memory.
背景技术Background technique
随着手机、平板、个人计算机等电子设备的普及，半导体存储器技术也得到了快速的发展。例如动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)、静态随机存取存储器(Static Random-Access Memory，简称SRAM)的存储器由于高密度、低功耗、低价格等优点，已广泛应用于各种电子设备中。With the popularization of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly. For example, Dynamic Random Access Memory (DRAM) and Static Random-Access Memory (SRAM) have been widely used in high density, low power consumption, low price and other advantages. in various electronic devices.
灵敏放大器(Sense Amplifier，简称SA)是半导体存储器的一个重要组成部分，其主要作用是将位线上的小信号进行放大，从而执行读取或写入操作。A sense amplifier (Sense Amplifier, SA for short) is an important part of a semiconductor memory, and its main function is to amplify a small signal on a bit line to perform a read or write operation.
随着技术的不断进步，半导体存储器的尺寸不断减小，在这种情况下，灵敏放大器中，由于晶体管的失配会对灵敏放大器的输出造成一定影响，从而影响存储器的性能。With the continuous advancement of technology, the size of semiconductor memory is continuously reduced. In this case, in the sense amplifier, due to the mismatch of transistors, the output of the sense amplifier will be affected to a certain extent, thereby affecting the performance of the memory.
发明内容SUMMARY OF THE INVENTION
本发明解决的技术问题是提供一种灵敏放大器、存储器和存储器的工作方法，以提升存储器的性能。The technical problem solved by the present invention is to provide a sense amplifier, a memory and a working method of the memory, so as to improve the performance of the memory.
为解决上述技术问题，本发明技术方案提供一种灵敏放大器，包括：第一晶体管，所述第一晶体管的栅极与存储单元的第一位线连接；第二晶体管，所述第二晶体管的栅极与存储单元的第二位线连接，所述第二晶体管的源极与第一晶体管的源极连接；第三晶体管，所述第三晶体管的栅极与存储单元的第二位线连接，所述第三晶体管的源极与第二晶体管的源极连接，所述第一晶体管的源极、第二晶体管的源极和第三晶体管的源极与接地电压节点耦接，所述第一晶体管、第二晶体管和第三晶体管的阈值电压不同；镜像单元，所述镜像单元包括被镜像端、第一镜像端和第二镜像端，所述被镜像端与第一晶体管的漏极连接，所述第一镜像端与第二晶体管的漏极连接，所述第二镜像端与第三晶体管的漏极连接；检测单元，所述镜像单元的第一镜像端与检测单元连接，所述镜像单元的第二镜像端与检测单元连接。In order to solve the above technical problems, the technical solution of the present invention provides a sense amplifier, comprising: a first transistor, the gate of the first transistor is connected to the first bit line of the memory cell; a second transistor, the second transistor is The gate is connected to the second bit line of the memory cell, the source of the second transistor is connected to the source of the first transistor; the third transistor, the gate of the third transistor is connected to the second bit line of the memory cell , the source of the third transistor is connected to the source of the second transistor, the source of the first transistor, the source of the second transistor and the source of the third transistor are coupled to the ground voltage node, the A transistor, a second transistor and a third transistor have different threshold voltages; a mirror unit, the mirror unit includes a mirrored terminal, a first mirrored terminal and a second mirrored terminal, and the mirrored terminal is connected to the drain of the first transistor , the first mirror terminal is connected to the drain of the second transistor, the second mirror terminal is connected to the drain of the third transistor; the detection unit, the first mirror terminal of the mirror unit is connected to the detection unit, the The second mirror end of the mirror unit is connected to the detection unit.
可选的，所述镜像单元被镜像端包括：第四晶体管，所述第四晶体管的源极与电源电压节点连接，所述第四晶体管的漏极与第一晶体管的漏极连接，所述第四晶体管的栅极与第一晶体管的漏极连接。Optionally, the mirrored end of the mirroring unit includes: a fourth transistor, the source of the fourth transistor is connected to the power supply voltage node, the drain of the fourth transistor is connected to the drain of the first transistor, the The gate of the fourth transistor is connected to the drain of the first transistor.
可选的，所述镜像单元第一镜像端包括：第五晶体管，所述第五晶体管的源极与电源电压节点连接，所述第五晶体管的漏极与第二晶体管的漏极连接，所述第五晶体管的栅极与第四晶体管的栅极连接；所述检测单元与第五晶体管的漏极连接。Optionally, the first mirror end of the mirror unit includes: a fifth transistor, the source of the fifth transistor is connected to the power supply voltage node, the drain of the fifth transistor is connected to the drain of the second transistor, so The gate of the fifth transistor is connected to the gate of the fourth transistor; the detection unit is connected to the drain of the fifth transistor.
可选的，所述镜像单元第二镜像端包括：第六晶体管，所述第六晶体管的源极与电源电压节点连接，所述第六晶体管的漏极与第三晶体管的漏极连接，所述第六晶体管的栅极与第四晶体管的栅极以及第五晶体管的栅极连接；所述检测单元与第六晶体管的漏极连接。Optionally, the second mirror end of the mirroring unit includes: a sixth transistor, the source of the sixth transistor is connected to the power supply voltage node, the drain of the sixth transistor is connected to the drain of the third transistor, so The gate of the sixth transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor; the detection unit is connected to the drain of the sixth transistor.
可选的，所述第四晶体管为P型晶体管；第五晶体管为P型晶体管；所述第六晶体管为P型晶体管。Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.
可选的，所述镜像单元还包括电压输入节点，所述电压输入节点与电源电压节点连接。Optionally, the mirroring unit further includes a voltage input node, and the voltage input node is connected to a power supply voltage node.
可选的，所述第一晶体管的阈值电压大于第二晶体管的阈值电压；所述第三晶体管的阈值电压大于第一晶体管的阈值电压。Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
可选的，还包括：第一反相器和第二反相器；所述第一反相器与镜像单元第一镜像端和检测单元连接；所述第二反相器与镜像单元第二镜像端和检测单元连接。Optionally, it further includes: a first inverter and a second inverter; the first inverter is connected to the first mirror end of the mirror unit and the detection unit; the second inverter is connected to the second mirror of the mirror unit The mirror end is connected to the detection unit.
可选的，所述第一晶体管为N型晶体管；第二晶体管为N型晶体管；所述第三晶体管为N型晶体管。Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.
可选的，还包括：第七晶体管，所述第七晶体管的漏极与存储单元的第二位线以及第三晶体管的栅极连接，所述第七晶体管的源极与接地电压节点连接，所述第七晶体管的栅极与第三晶体管的栅极连接。Optionally, it also includes: a seventh transistor, the drain of the seventh transistor is connected to the second bit line of the memory cell and the gate of the third transistor, the source of the seventh transistor is connected to the ground voltage node, The gate of the seventh transistor is connected to the gate of the third transistor.
可选的，所述第七晶体管为N型晶体管。Optionally, the seventh transistor is an N-type transistor.
可选的，还包括：第八晶体管，所述第八晶体管的漏极与存储单元的第二位线以及第二晶体管的栅极连接，所述第八晶体管的源极与接地电压节点连接，所述第八晶体管的栅极与第二晶体管的栅极连接。Optionally, it also includes: an eighth transistor, the drain of the eighth transistor is connected to the second bit line of the memory cell and the gate of the second transistor, the source of the eighth transistor is connected to the ground voltage node, The gate of the eighth transistor is connected to the gate of the second transistor.
可选的，所述第八晶体管为N型晶体管。Optionally, the eighth transistor is an N-type transistor.
可选的，还包括：第九晶体管，所述第九晶体管的漏极与存储单元的第一位线以及第一晶体管的栅极连接，所述第九晶体管的源极与接地电压节点连接，所述第九晶体管的栅极与第一晶体管的栅极连接。Optionally, it also includes: a ninth transistor, the drain of the ninth transistor is connected to the first bit line of the memory cell and the gate of the first transistor, the source of the ninth transistor is connected to the ground voltage node, The gate of the ninth transistor is connected to the gate of the first transistor.
可选的，所述第九晶体管为N型晶体管。Optionally, the ninth transistor is an N-type transistor.
可选的，还包括：第十晶体管，所述第十晶体管的漏极与第一晶体管的源极、第二晶体管的源极以及第三晶体管的源极连接，所述第十晶体管的源极与接地电压节点连接。Optionally, it further includes: a tenth transistor, the drain of the tenth transistor is connected to the source of the first transistor, the source of the second transistor and the source of the third transistor, the source of the tenth transistor is connected Connect to the ground voltage node.
可选的，所述第十晶体管为N型晶体管。Optionally, the tenth transistor is an N-type transistor.
相应地，本发明技术方案还提供一种存储器，包括：若干存储单元，所述存储单元包括第一位线和第二位线；与存储单元连接的灵敏放大器，所述灵敏放大器包括：第一晶体管，所述第一晶体管的栅极与存储单元的第一位线连接；第二晶体管，所述第二晶体管的栅极与存储单元的第二位线连接，所述第二晶体管的源极与第一晶体管的源极连接；第三晶体管，所述第三晶体管的栅极与存储单元的第二位线连接，所述第三晶体管的源极与第二晶体管的源极连接，所述第一晶体管的源极、第二晶体管的源极和第三晶体管的源极与接地电压节点耦接，所述第一晶体管、第二晶体管和第三晶体管的阈值电压不同；镜像单元，所述镜像单元包括被镜像端、第一镜像端和第二镜像端，所述被镜像端与第一晶体管的漏极连接，所述第一镜像端与第二晶体管的漏极连接，所述第二镜像端与第三晶体管的漏极连接；检测单元，所述镜像单元的第一镜像端与检测单元连接，所述镜像单元的第二镜像端与检测单元连接；与灵敏放大器连接的读取单元。Correspondingly, the technical solution of the present invention also provides a memory, including: a plurality of storage units, the storage units include a first bit line and a second bit line; a sense amplifier connected to the storage unit, the sense amplifier includes: a first bit line transistor, the gate of the first transistor is connected to the first bit line of the memory cell; the second transistor, the gate of the second transistor is connected to the second bit line of the memory cell, and the source of the second transistor connected to the source of the first transistor; a third transistor, the gate of the third transistor is connected to the second bit line of the memory cell, the source of the third transistor is connected to the source of the second transistor, the The source of the first transistor, the source of the second transistor and the source of the third transistor are coupled to the ground voltage node, and the threshold voltages of the first transistor, the second transistor and the third transistor are different; the mirror unit, the The mirror unit includes a mirrored terminal, a first mirrored terminal and a second mirrored terminal, the mirrored terminal is connected to the drain of the first transistor, the first mirrored terminal is connected to the drain of the second transistor, and the second mirrored terminal is connected to the drain of the second transistor. The mirror terminal is connected to the drain of the third transistor; the detection unit, the first mirror terminal of the mirror unit is connected to the detection unit, the second mirror terminal of the mirror unit is connected to the detection unit; the read unit connected to the sense amplifier .
可选的，所述镜像单元被镜像端包括：第四晶体管，所述第四晶体管的源极与电源电压节点连接，所述第四晶体管的漏极与第一晶体管的漏极连接，所述第四晶体管的栅极与第一晶体管的漏极连接。Optionally, the mirrored end of the mirroring unit includes: a fourth transistor, the source of the fourth transistor is connected to the power supply voltage node, the drain of the fourth transistor is connected to the drain of the first transistor, the The gate of the fourth transistor is connected to the drain of the first transistor.
可选的，所述镜像单元第一镜像端包括：第五晶体管，所述第五晶体管的源极与电源电压节点连接，所述第五晶体管的漏极与第二晶体管的漏极连接，所述第五晶体管的栅极与第四晶体管的栅极连接；所述检测单元与第五晶体管的漏极连接。Optionally, the first mirror end of the mirror unit includes: a fifth transistor, the source of the fifth transistor is connected to the power supply voltage node, the drain of the fifth transistor is connected to the drain of the second transistor, so The gate of the fifth transistor is connected to the gate of the fourth transistor; the detection unit is connected to the drain of the fifth transistor.
可选的，所述镜像单元第二镜像端包括：第六晶体管，所述第六晶体管的源极与电源电压节点连接，所述第六晶体管的漏极与第三晶体管的漏极连接，所述第六晶体管的栅极与第四晶体管的栅极以及第五晶体管的栅极连接；所述检测单元与第六晶体管的漏极连接。Optionally, the second mirror end of the mirroring unit includes: a sixth transistor, the source of the sixth transistor is connected to the power supply voltage node, the drain of the sixth transistor is connected to the drain of the third transistor, so The gate of the sixth transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor; the detection unit is connected to the drain of the sixth transistor.
可选的，所述第四晶体管为P型晶体管；第五晶体管为P型晶体管；所述第六晶体管为P型晶体管。Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.
可选的，所述第一晶体管的阈值电压大于第二晶体管的阈值电压；所述第三晶体管的阈值电压大于第一晶体管的阈值电压。Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
可选的，所述灵敏放大器还包括：第一反相器和第二反相器；所述第一反相器与镜像单元第一镜像端和检测单元连接；所述第二反相器与镜像单元第二镜像端和检测单元连接。Optionally, the sense amplifier further includes: a first inverter and a second inverter; the first inverter is connected to the first mirror end of the mirror unit and the detection unit; the second inverter is connected to The second mirror end of the mirror unit is connected to the detection unit.
可选的，所述第一晶体管为N型晶体管；第二晶体管为N型晶体管；所述第三晶体管为N型晶体管。Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.
相应地，本发明技术方案还提供一种存储器的工作方法，包括：提供存储器，所述存储器包括：若干存储单元，所述存储单元包括第一位线和第二位线；与存储单元连接的灵敏放大器，所述灵敏放大器包括：第一晶体管，所述第一晶体管的栅极与存储单元的第一位线连接；第二晶体管，所述第二晶体管的栅极与存储单元的第二位线连接，所述第二晶体管的源极与第一晶体管的源极连接；第三晶体管，所述第三晶体管的栅极与存储单元的第二位线连接，所述第三晶体管的源极与第二晶体管的源极连接，所述第一晶体管的源极、第二晶体管的源极和第三晶体管的源极与接地电压节点耦接，所述第一晶体管、第二晶体管和第三晶体管的阈值电压不同；镜像单元，所述镜像单元包括被镜像端、第一镜像端和第二镜像端，所述被镜像端与第一晶体管的漏极连接，所述第一镜像端与第二晶体管的漏极连接，所述第二镜像端与第三晶体管的漏极连接；检测单元，所述镜像单元的第一镜像端与检测单元连接，所述镜像单元的第二镜像端与检测单元连接；与灵敏放大器连接的读取单元；对镜像端与第一镜像端的电流大小进行比较并输出第一信号；对镜像端与第二镜像端的电流大小进行比较并输出第二信号；所述检测单元对所述第一信号和第二信号进行比较判断，获取比较结果；所述读取单元获取与所述比较结果对应的读周期对存储器进行读取。Correspondingly, the technical solution of the present invention also provides a working method of a memory, including: providing a memory, the memory includes: a plurality of storage units, the storage units include a first bit line and a second bit line; A sense amplifier, the sense amplifier includes: a first transistor, the gate of the first transistor is connected to the first bit line of the storage unit; a second transistor, the gate of the second transistor is connected to the second bit line of the storage unit Line connection, the source of the second transistor is connected to the source of the first transistor; for the third transistor, the gate of the third transistor is connected to the second bit line of the memory cell, and the source of the third transistor connected to the source of the second transistor, the source of the first transistor, the source of the second transistor and the source of the third transistor are coupled to the ground voltage node, the first transistor, the second transistor and the third transistor The threshold voltages of the transistors are different; the mirror unit includes a mirrored terminal, a first mirror terminal and a second mirror terminal, the mirrored terminal is connected to the drain of the first transistor, and the first mirror terminal is connected to the first mirror terminal. The drains of the two transistors are connected, the second mirror terminal is connected to the drain of the third transistor; the detection unit, the first mirror terminal of the mirror unit is connected to the detection unit, and the second mirror terminal of the mirror unit is connected to the detection unit The unit is connected; the read unit connected with the sense amplifier; compares the current magnitude of the mirror end and the first mirror end and outputs a first signal; compares the current magnitude of the mirror end and the second mirror end and outputs a second signal; the The detection unit compares and judges the first signal and the second signal, and obtains a comparison result; the reading unit obtains a read cycle corresponding to the comparison result to read the memory.
可选的，所述读取单元获取对应的读周期对存储器进行读取的方法包括：若所述第一信号与第二信号相同，采用第一读周期对存储器进行读取；若所述第一信号与第二信号不同，采用第二读周期对存储器进行读取。Optionally, the method for the reading unit to obtain the corresponding read cycle to read the memory includes: if the first signal is the same as the second signal, using the first read cycle to read the memory; A signal is different from the second signal, and a second read cycle is used to read the memory.
可选的，所述第一读周期小于第二读周期。Optionally, the first read period is shorter than the second read period.
可选的，所述镜像单元被镜像端包括：第四晶体管，所述第四晶体管的源极与电源电压节点连接，所述第四晶体管的漏极与第一晶体管的漏极连接，所述第四晶体管的栅极与第一晶体管的漏极连接。Optionally, the mirrored end of the mirroring unit includes: a fourth transistor, the source of the fourth transistor is connected to the power supply voltage node, the drain of the fourth transistor is connected to the drain of the first transistor, the The gate of the fourth transistor is connected to the drain of the first transistor.
可选的，所述镜像单元第一镜像端包括：第五晶体管，所述第五晶体管的源极与电源电压节点连接，所述第五晶体管的漏极与第二晶体管的漏极连接，所述第五晶体管的栅极与第四晶体管的栅极连接；所述检测单元与第五晶体管的漏极连接。Optionally, the first mirror end of the mirror unit includes: a fifth transistor, the source of the fifth transistor is connected to the power supply voltage node, the drain of the fifth transistor is connected to the drain of the second transistor, so The gate of the fifth transistor is connected to the gate of the fourth transistor; the detection unit is connected to the drain of the fifth transistor.
可选的，所述镜像单元第二镜像端包括：第六晶体管，所述第六晶体管的源极与电源电压节点连接，所述第六晶体管的漏极与第三晶体管的漏极连接，所述第六晶体管的栅极与第四晶体管的栅极以及第五晶体管的栅极连接；所述检测单元与第六晶体管的漏极连接。Optionally, the second mirror end of the mirroring unit includes: a sixth transistor, the source of the sixth transistor is connected to the power supply voltage node, the drain of the sixth transistor is connected to the drain of the third transistor, so The gate of the sixth transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor; the detection unit is connected to the drain of the sixth transistor.
可选的，所述第四晶体管为P型晶体管；第五晶体管为P型晶体管；所述第六晶体管为P型晶体管。Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.
可选的，所述第一晶体管的阈值电压大于第二晶体管的阈值电压；所述第三晶体管的阈值电压大于第一晶体管的阈值电压。Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.
可选的，所述灵敏放大器还包括：第一反相器和第二反相器；所述第一反相器与镜像单元第一镜像端和检测单元连接；所述第二反相器与镜像单元第二镜像端和检测单元连接。Optionally, the sense amplifier further includes: a first inverter and a second inverter; the first inverter is connected to the first mirror end of the mirror unit and the detection unit; the second inverter is connected to The second mirror end of the mirror unit is connected to the detection unit.
可选的，对镜像端与第一镜像端的电流大小进行比较的方法包括：若所述镜像端电流大于第一镜像端的电流，所述第一信号为“0”；若所述镜像端电流小于第一镜像端的电流，所述第一信号为“1”。Optionally, the method for comparing the current magnitudes of the mirror terminal and the first mirror terminal includes: if the mirror terminal current is greater than the first mirror terminal current, the first signal is "0"; if the mirror terminal current is less than For the current of the first mirror terminal, the first signal is "1".
可选的，对镜像端与第二镜像端的电流大小进行比较的方法包括：若所述镜像端电流大于第二镜像端的电流，所述第二信号为“0”；若所述镜像端电流小于第二镜像端的电流，所述第二信号为“1”。Optionally, the method for comparing the current magnitudes of the mirror terminal and the second mirror terminal includes: if the current of the mirror terminal is greater than the current of the second mirror terminal, the second signal is "0"; if the current of the mirror terminal is less than The current at the second mirror terminal, the second signal is "1".
可选的，所述第一晶体管为N型晶体管；第二晶体管为N型晶体管；所述第三晶体管为N型晶体管。Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.
与现有技术相比，本发明的技术方案具有以下有益效果：Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:
本发明技术方案中的灵敏放大器，所述第一晶体管、第二晶体管和第三晶体管的阈值电压不同，且所述第一晶体管、第二晶体管和第三晶体管分别与镜像单元的被镜像端、第一镜像端和第二镜像端连接。所述第一晶体管、第二晶体管和第三晶体管的阈值电压不同，从而通过第一晶体管、第二晶体管和第三晶体管的电流大小不同，从而检测单元能够对镜像单元第一镜像端和镜像单元第二镜像端输出的信号进行检测比较，根据比较结果的正确与否判断与灵敏放大器连接的存储单元的强弱状态，以便后续采用不同的读周期对强弱状态不同的存储单元进行读取，以提升存储器的整体读写速度，提高了存储器的性能。In the sense amplifier in the technical solution of the present invention, the threshold voltages of the first transistor, the second transistor and the third transistor are different, and the first transistor, the second transistor and the third transistor are respectively connected to the mirrored end, The first mirror end and the second mirror end are connected. The threshold voltages of the first transistor, the second transistor, and the third transistor are different, so that the magnitudes of the currents passing through the first transistor, the second transistor, and the third transistor are different, so that the detection unit can monitor the first mirror end of the mirror unit and the mirror unit. The signal output by the second mirror terminal is detected and compared, and the strength state of the memory cell connected to the sense amplifier is judged according to whether the comparison result is correct or not, so that the memory cells with different strong and weak states can be read in different read cycles subsequently. In order to improve the overall read and write speed of the memory, the performance of the memory is improved.
进一步，所述第一晶体管的阈值电压大于第二晶体管的阈值电压；所述第三晶体管的阈值电压大于第一晶体管的阈值电压。流过所述第一晶体管的电流与镜像单元被镜像端的电流相同，镜像单元被镜像端的电流镜像到镜像单元第一镜像端和镜像单元第二镜像端之后，镜像单元第一镜像端的电流与流经第二晶体管的电流拉平，镜像单元第二镜像端的电流与流经第三晶体管的电流拉平，从而检测单元能够通过判断镜像单元第一镜像端的信号与镜像单元第二镜像端的信号的变化状态是否一致，来判断与灵敏放大器连接的存储单元的强弱状态。若镜像单元第一镜像端的信号与镜像单元第二镜像端的信号相同，则与灵敏放大器连接的存储单元为驱动较强的单元；若镜像单元第一镜像端的信号与镜像单元第二镜像端的信号不同，则与灵敏放大器连接的存储单元为驱动较弱的单元。Further, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor. The current flowing through the first transistor is the same as the current at the mirrored end of the mirroring unit. After the current at the mirrored end of the mirroring unit is mirrored to the first mirroring end of the mirroring unit and the second mirroring end of the mirroring unit, the current at the first mirroring end of the mirroring unit is the same as the current. After the current of the second transistor is leveled, the current of the second mirror end of the mirror unit and the current flowing through the third transistor are leveled, so that the detection unit can judge whether the signal of the first mirror end of the mirror unit and the signal of the second mirror end of the mirror unit change state. It is consistent to judge the strength state of the memory cell connected to the sense amplifier. If the signal of the first mirror end of the mirror unit is the same as the signal of the second mirror end of the mirror unit, the storage unit connected to the sense amplifier is the unit with stronger drive; if the signal of the first mirror end of the mirror unit is different from the signal of the second mirror end of the mirror unit , the storage unit connected with the sense amplifier is the unit with weaker drive.
附图说明Description of drawings
图1是一实施例中电压型灵敏放大器的电路示意图；1 is a schematic circuit diagram of a voltage-type sense amplifier in an embodiment;
图2是本发明实施例中灵敏放大器的电路示意图；2 is a schematic circuit diagram of a sense amplifier in an embodiment of the present invention;
图3是本发明另一实施例中灵敏放大器的电路示意图；3 is a schematic circuit diagram of a sense amplifier in another embodiment of the present invention;
图4是本发明实施例中存储器的工作方法流程图。FIG. 4 is a flowchart of a working method of a memory in an embodiment of the present invention.
具体实施方式Detailed ways
如背景技术所述，现有的存储器性能还有待提升。As described in the background art, the performance of the existing memory needs to be improved.
具体地，以SRAM(动态随机存取存储器)为例，SRAM的性能取决于读操作。存储阵列中的存储单元的驱动能力是不一致的，为了保证SRAM读操作的正确性，字线关断(灵敏放大器开启)时要保证存储阵列中所有存储单元的位线摆幅超过灵敏放大器的失调电压，因此存储阵列的读出延时取决于存储阵列中驱动最弱的存储单元。存储单元的驱动能力较弱，因此存储单元的读出延时相对较大。Specifically, taking SRAM (Dynamic Random Access Memory) as an example, the performance of SRAM depends on the read operation. The drive capability of the memory cells in the memory array is inconsistent. In order to ensure the correctness of the SRAM read operation, when the word line is turned off (the sense amplifier is turned on), it is necessary to ensure that the bit line swing of all memory cells in the memory array exceeds the offset of the sense amplifier. voltage, and therefore the readout latency of the memory array depends on the least driven memory cell in the memory array. The drive capability of the memory cell is relatively weak, so the readout delay of the memory cell is relatively large.
在整个读操作路径中，字线的驱动电路，输出驱动模块对应普通的逻辑电路，可以通过采用低阈值器件和增大晶体管尺寸等方法减小延时；而对于存储阵列的延时，延时的大小由存储单元的驱动能力决定，和逻辑电路相比，SRAM存储单元的驱动能力相对较弱，因此其放电延时相对较大。In the entire read operation path, the word line driver circuit and output driver module correspond to ordinary logic circuits, and the delay can be reduced by adopting low-threshold devices and increasing the size of transistors; for the delay of the memory array, the delay The size of SRAM is determined by the drive capability of the memory cell. Compared with the logic circuit, the drive capability of the SRAM memory cell is relatively weak, so its discharge delay is relatively large.
当电源电压降低至近阈值区时，局部工艺波动导致存储单元位线放电延时的统计分布存在明显的拖尾现象，绝大多数存储单元的放电延时分布在15ns以内，只有少数弱驱动存储单元的放电延时分布在15ns至30ns之间，弱驱动存储单元使得设计裕度随着电源电压的降低进一步变大，过于悲观的设计裕度使存储阵列的性能急剧下降，故SRAM的整体性能急剧降低。When the power supply voltage is reduced to the near-threshold region, local process fluctuations lead to obvious tailing phenomenon in the statistical distribution of the discharge delay of the memory cell bit line. The discharge delay of most memory cells is distributed within 15ns, and only a few weakly driven memory cells The discharge delay of the SRAM is distributed between 15ns and 30ns. The weak drive memory cells make the design margin further increase with the decrease of the power supply voltage. The overly pessimistic design margin causes the performance of the memory array to drop sharply, so the overall performance of the SRAM sharply decreases. reduce.
图1是一种电压型灵敏放大器的电路，适应性地举出一种灵敏放大器，以对局部工艺波动造成的晶体管失配会对灵敏放大器的输出造成的影响进行分析说明。FIG. 1 is a circuit of a voltage-type sense amplifier, and a sense amplifier is adaptively illustrated to analyze and explain the influence of transistor mismatch caused by local process fluctuations on the output of the sense amplifier.
请参考图1，所述灵敏放大器包括：第一晶体管M1；第二晶体管M2，所述第二晶体管M2的漏极与第一晶体管M1的栅极连接，所述第一晶体管M1的漏极与第二晶体管M2的栅极连接；第三晶体管M3和第四晶体管M4，所述第三晶体管M3的源极与第四晶体管M4的源极连接，所述第三晶体管的M3漏极与第四晶体管M4的漏极连接，所述第三晶体管M3的源极和第四晶体管M4的源极与电源电压结点VDD连接，所述第三晶体管M3的漏极和第四晶体管M4的漏极与第一晶体管M1的漏极连接，所述第四晶体管M4的栅极与第一晶体管M1的栅极连接；第五晶体管M5和第六晶体管M6，所述第五晶体管M5的源极与第六晶体管M6的源极连接，所述第五晶体管M5的漏极与第六晶体管M6的漏极连接，所述第五晶体管M5的源极和第六晶体管M6的源极与电源电压结点VDD连接，所述第五晶体管M5的漏极和第六晶体管M6的漏极与第二晶体管M2的漏极连接，所述第六晶体管M6的栅极与第二晶体管M2的栅极连接；第七晶体管M7，所述第七晶体管M7的漏极与第一晶体管M1的源极连接，所述第七晶体管M7的栅极与存储单元的第一位线IN连接；第八晶体管M8，所述第八晶体管M8的漏极与第二晶体管M2的源极连接，所述第八晶体管M8的栅极与存储单元的第二位线INB连接，所述第八晶体管M8的源极与第七晶体管M7的源极连接；第九晶体管M9，所述第九晶体管M9的漏极与第八晶体管M8的源极以及第七晶体管M7的源极连接，所述第九晶体管M9的源极与接地电压节点连接，所述第三晶体管M3的栅极与第九晶体管M9的栅极连接，所述第六晶体管M6的栅极与第九晶体管M9的栅极连接。Please refer to FIG. 1, the sense amplifier includes: a first transistor M1; a second transistor M2, the drain of the second transistor M2 is connected to the gate of the first transistor M1, and the drain of the first transistor M1 is connected to the gate of the first transistor M1. The gate of the second transistor M2 is connected; the third transistor M3 and the fourth transistor M4, the source of the third transistor M3 is connected to the source of the fourth transistor M4, the drain of the third transistor M3 is connected to the fourth transistor M4 The drain of the transistor M4 is connected, the source of the third transistor M3 and the source of the fourth transistor M4 are connected to the power supply voltage node VDD, the drain of the third transistor M3 and the drain of the fourth transistor M4 are connected to the power supply voltage node VDD. The drain of the first transistor M1 is connected, the gate of the fourth transistor M4 is connected to the gate of the first transistor M1; the fifth transistor M5 and the sixth transistor M6, the source of the fifth transistor M5 is connected to the sixth transistor M5 The source of the transistor M6 is connected, the drain of the fifth transistor M5 is connected to the drain of the sixth transistor M6, the source of the fifth transistor M5 and the source of the sixth transistor M6 are connected to the power supply voltage node VDD , the drain of the fifth transistor M5 and the drain of the sixth transistor M6 are connected to the drain of the second transistor M2, the gate of the sixth transistor M6 is connected to the gate of the second transistor M2; the seventh transistor M7, the drain of the seventh transistor M7 is connected to the source of the first transistor M1, the gate of the seventh transistor M7 is connected to the first bit line IN of the memory cell; the eighth transistor M8, the eighth The drain of the transistor M8 is connected to the source of the second transistor M2, the gate of the eighth transistor M8 is connected to the second bit line INB of the memory cell, and the source of the eighth transistor M8 is connected to the seventh transistor M7. The source is connected; the ninth transistor M9, the drain of the ninth transistor M9 is connected to the source of the eighth transistor M8 and the source of the seventh transistor M7, the source of the ninth transistor M9 is connected to the ground voltage node , the gate of the third transistor M3 is connected to the gate of the ninth transistor M9, and the gate of the sixth transistor M6 is connected to the gate of the ninth transistor M9.
所述灵敏放大器中，所述第三晶体管M3、第四晶体管M4、第五晶体管M5和第六晶体管M6为P型晶体管；所述第一晶体管M1、第二晶体管M2、第七晶体管M7、第八晶体管M8和第九晶体管M9为N型晶体管。In the sense amplifier, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are P-type transistors; the first transistor M1, the second transistor M2, the seventh transistor M7, the The eight transistors M8 and the ninth transistor M9 are N-type transistors.
所述灵敏放大器中，局部工艺波动导致存储单元的驱动力较弱时，则与第一位线IN连接的第七晶体管M7以及与第二位线INB连接的第八晶体管M8之间的压差Vinput较小，所述Vinput可能会小于灵敏放大器的偏置电压Voffset，这就使得灵敏放大器的输出结果可能出错，影响存储器的性能。In the sense amplifier, when the driving force of the memory cell is weak due to local process fluctuations, the voltage difference between the seventh transistor M7 connected to the first bit line IN and the eighth transistor M8 connected to the second bit line INB The Vinput is relatively small, and the Vinput may be smaller than the bias voltage Voffset of the sense amplifier, which may cause errors in the output result of the sense amplifier and affect the performance of the memory.
为了解决上述问题，本发明技术方案提供一种灵敏放大器、存储器以及存储器的工作方法，通过使所述灵敏放大器中的第一晶体管、第二晶体管和第三晶体管的阈值电压不同，且所述第一晶体管、第二晶体管和第三晶体管分别与镜像单元的被镜像端、第一镜像端和第二镜像端连接。所述第一晶体管、第二晶体管和第三晶体管的阈值电压不同，从而通过第一晶体管、第二晶体管和第三晶体管的电流大小不同，从而检测单元能够对镜像单元第一镜像端和镜像单元第二镜像端输出的信号进行检测比较，根据比较结果的正确与否判断与灵敏放大器连接的存储单元的强弱状态，以便后续采用不同的读周期对强弱状态不同的存储单元进行读取，以提升存储器的整体读写速度，提高了存储器的性能。In order to solve the above problems, the technical solution of the present invention provides a sense amplifier, a memory and a working method of the memory, by making the threshold voltages of the first transistor, the second transistor and the third transistor in the sense amplifier different, and the A transistor, a second transistor and a third transistor are respectively connected to the mirrored terminal, the first mirror terminal and the second mirror terminal of the mirror unit. The threshold voltages of the first transistor, the second transistor, and the third transistor are different, so that the magnitudes of the currents passing through the first transistor, the second transistor, and the third transistor are different, so that the detection unit can monitor the first mirror end of the mirror unit and the mirror unit. The signal output by the second mirror terminal is detected and compared, and the strength state of the memory cell connected to the sense amplifier is judged according to whether the comparison result is correct or not, so that the memory cells with different strength states can be read in different read cycles later. In order to improve the overall read and write speed of the memory, the performance of the memory is improved.
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
图2是本发明实施例中灵敏放大器的电路示意图。FIG. 2 is a schematic circuit diagram of a sense amplifier in an embodiment of the present invention.
请参考图2，所述灵敏放大器包括：第一晶体管M1，所述第一晶体管M1的栅极与存储单元的第一位线BL连接；Please refer to FIG. 2, the sense amplifier includes: a first transistor M1, the gate of the first transistor M1 is connected to the first bit line BL of the memory cell;
第二晶体管M2，所述第二晶体管M2的栅极与存储单元的第二位线BLB连接，所述第二晶体管M2的源极与第一晶体管M1的源极连接；the second transistor M2, the gate of the second transistor M2 is connected to the second bit line BLB of the memory cell, and the source of the second transistor M2 is connected to the source of the first transistor M1;
第三晶体管M3，所述第三晶体管M3的栅极与存储单元的第二位线BLB连接，所述第三晶体管M3的源极与第二晶体管M2的源极连接，所述第一晶体管M1的源极、第二晶体管M2的源极和第三晶体管M3的源极与接地电压节点耦接，所述第一晶体管M1、第二晶体管M2和第三晶体管M3的阈值电压不同；The third transistor M3, the gate of the third transistor M3 is connected to the second bit line BLB of the memory cell, the source of the third transistor M3 is connected to the source of the second transistor M2, and the first transistor M1 The source of the second transistor M2 and the source of the third transistor M3 are coupled to the ground voltage node, and the threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different;
镜像单元，所述镜像单元包括被镜像端、第一镜像端和第二镜像端，所述被镜像端与第一晶体管M1的漏极连接，所述第一镜像端与第二晶体管M2的漏极连接，所述第二镜像端与第三晶体管M3的漏极连接；a mirroring unit, the mirroring unit includes a mirrored terminal, a first mirrored terminal and a second mirrored terminal, the mirrored terminal is connected to the drain of the first transistor M1, and the first mirrored terminal is connected to the drain of the second transistor M2 The second mirror terminal is connected to the drain of the third transistor M3;
检测单元T，所述镜像单元的第一镜像端与检测单元T连接，所述镜像单元的第二镜像端与检测单元T连接。In the detection unit T, the first mirror end of the mirror unit is connected to the detection unit T, and the second mirror end of the mirror unit is connected to the detection unit T.
在本实施例中，所述镜像单元被镜像端包括：第四晶体管M4，所述第四晶体管M4的源极与电源电压节点VDD连接，所述第四晶体管M4的漏极与第一晶体管M1的漏极连接，所述第四晶体管M4的栅极与第一晶体管M1的漏极连接。In this embodiment, the mirrored end of the mirroring unit includes: a fourth transistor M4, the source of the fourth transistor M4 is connected to the power supply voltage node VDD, and the drain of the fourth transistor M4 is connected to the first transistor M1 The drain of the fourth transistor M4 is connected to the drain of the first transistor M1.
在本实施例中，所述镜像单元第一镜像端包括：第五晶体管M5，所述第五晶体管M5的源极与电源电压节点VDD连接，所述第五晶体管M5的漏极与第二晶体管M2的漏极连接，所述第五晶体管M5的栅极与第四晶体管M4的栅极连接；所述检测单元T与第五晶体管M5的漏极连接。In this embodiment, the first mirror end of the mirror unit includes: a fifth transistor M5, the source of the fifth transistor M5 is connected to the power supply voltage node VDD, and the drain of the fifth transistor M5 is connected to the second transistor The drain of M2 is connected, the gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.
在本实施例中，所述镜像单元第二镜像端包括：第六晶体管M6，所述第六晶体管M6的源极与电源电压节点VDD连接，所述第六晶体管M6的漏极与第三晶体管M3的漏极连接，所述第六晶体管M6的栅极与第四晶体管M4的栅极以及第五晶体管M5的栅极连接；所述检测单元T与第六晶体管M6的漏极连接。In this embodiment, the second mirror terminal of the mirror unit includes: a sixth transistor M6, the source of the sixth transistor M6 is connected to the power supply voltage node VDD, and the drain of the sixth transistor M6 is connected to the third transistor The drain of M3 is connected, the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.
在本实施例中，所述第四晶体管M4为P型晶体管；第五晶体管M5为P型晶体管；所述第六晶体管M6为P型晶体管。In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; and the sixth transistor M6 is a P-type transistor.
所述第一晶体管M1、第二晶体管M2和第三晶体管M3的阈值电压不同，从而通过第一晶体管M1、第二晶体管M2和第三晶体管M3的电流大小不同，从而检测单元T能够对镜像单元第一镜像端和镜像单元第二镜像端输出的信号进行检测比较，根据比较结果的正确与否判断与灵敏放大器连接的存储单元的强弱状态，以便后续采用不同的读周期对强弱状态不同的存储单元进行读取，以提升存储器的整体读写速度，提高了存储器的性能。The threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the magnitudes of the currents passing through the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the detection unit T can detect the mirror unit The signals output by the first mirror terminal and the second mirror terminal of the mirror unit are detected and compared, and the strength state of the memory cell connected to the sense amplifier is judged according to whether the comparison result is correct or not, so that different read cycles can be used for different strength states. The storage unit is read, so as to improve the overall read and write speed of the memory and improve the performance of the memory.
在本实施例中，所述第一晶体管M1的阈值电压大于第二晶体管M2的阈值电压；所述第三晶体管M3的阈值电压大于第一晶体管M1的阈值电压。In this embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.
从而流过所述第一晶体管M1的电流与镜像单元被镜像端的电流相同，镜像单元被镜像端的电流镜像到镜像单元第一镜像端和镜像单元第二镜像端之后，镜像单元第一镜像端的电流与流经第二晶体管M2的电流拉平，镜像单元第二镜像端的电流与流经第三晶体管M3的电流拉平，从而检测单元能够通过判断镜像单元第一镜像端的信号与镜像单元第二镜像端的信号的变化状态是否一致，来判断与灵敏放大器连接的存储单元的强弱状态。若镜像单元第一镜像端的信号与镜像单元第二镜像端的信号相同，则与灵敏放大器连接的存储单元为驱动较强的单元；若镜像单元第一镜像端的信号与镜像单元第二镜像端的信号不同，则与灵敏放大器连接的存储单元为驱动较弱的单元。Therefore, the current flowing through the first transistor M1 is the same as the current at the mirrored end of the mirror unit. After the current at the mirrored end of the mirror unit is mirrored to the first mirror end of the mirror unit and the second mirror end of the mirror unit, the current of the first mirror end of the mirror unit is mirrored. Leveling with the current flowing through the second transistor M2, the current at the second mirror end of the mirror unit is leveled with the current flowing through the third transistor M3, so that the detection unit can determine the signal at the first mirror end of the mirror unit and the signal at the second mirror end of the mirror unit. Whether the state of change is consistent or not, to judge the strength or weakness of the memory cell connected to the sense amplifier. If the signal of the first mirror end of the mirror unit is the same as the signal of the second mirror end of the mirror unit, the storage unit connected to the sense amplifier is the unit with stronger drive; if the signal of the first mirror end of the mirror unit is different from the signal of the second mirror end of the mirror unit , the storage unit connected with the sense amplifier is the unit with weaker drive.
在本实施例中，所述镜像单元还包括电压输入节点(未标示)，所述电压输入节点与电源电压节点VDD连接。In this embodiment, the mirror unit further includes a voltage input node (not marked), and the voltage input node is connected to the power supply voltage node VDD.
在本实施例中，还包括：第一反相器B1和第二反相器B2；所述第一反相器B1与镜像单元第一镜像端和检测单元T连接；所述第二反相器B2与镜像单元第二镜像端和检测单元T连接。In this embodiment, it further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected to the first mirror end of the mirror unit and the detection unit T; the second inverter The device B2 is connected to the second mirror end of the mirror unit and the detection unit T.
所述第一反相器B1用于对第一镜像端输出的电流信号进行整形，使到达所述检测单元T的信号为标准逻辑信号，以便所述检测单元T识别判断，所述标准逻辑信号为第一信号。所述第一信号为所述镜像端与第一镜像端的电流大小比较结果。The first inverter B1 is used to shape the current signal output by the first mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, so that the detection unit T can identify and judge, the standard logic signal for the first signal. The first signal is a result of comparing the magnitude of the current between the mirror terminal and the first mirror terminal.
所述第二反相器B2用于对第二镜像端输出的电流信号进行整形，使到达所述检测单元T的信号为标准逻辑信号，以便所述检测单元T识别判断，所述标准逻辑信号为第二信号。所述第二信号为所述镜像端与第二镜像端的电流大小比较结果。The second inverter B2 is used to shape the current signal output by the second mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, so that the detection unit T can identify and judge, the standard logic signal for the second signal. The second signal is a result of comparing the magnitude of the current between the mirror terminal and the second mirror terminal.
所述第一信号为0或1；所述第二信号为0或1。The first signal is 0 or 1; the second signal is 0 or 1.
在其他实施例中，所述电路还能够不包括所述第一反相器和第二反相器。In other embodiments, the circuit can also exclude the first inverter and the second inverter.
在本实施例中，所述第一晶体管M1为N型晶体管；第二晶体管M2为N型晶体管；所述第三晶体管M3为N型晶体管。In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; and the third transistor M3 is an N-type transistor.
在本实施例中，还包括：第七晶体管M7，所述第七晶体管M7的漏极与存储单元的第二位线BLB以及第三晶体管M3的栅极连接，所述第七晶体管M7的源极与接地电压节点连接，所述第七晶体管M7的栅极与第三晶体管M3的栅极连接。In this embodiment, it further includes: a seventh transistor M7, the drain of the seventh transistor M7 is connected to the second bit line BLB of the memory cell and the gate of the third transistor M3, and the source of the seventh transistor M7 The pole is connected to the ground voltage node, and the gate of the seventh transistor M7 is connected to the gate of the third transistor M3.
所述第七晶体管M7起到镜像电流的作用，流经第七晶体管M7的电流镜像至第三晶体管M3。The seventh transistor M7 acts as a mirror current, and the current flowing through the seventh transistor M7 is mirrored to the third transistor M3.
在其他实施例中，所述电路还能够不包括所述第七晶体管M7。In other embodiments, the circuit can also not include the seventh transistor M7.
在本实施例中，所述第七晶体管M7为N型晶体管。In this embodiment, the seventh transistor M7 is an N-type transistor.
在本实施例中，还包括：第八晶体管M8，所述第八晶体管M8的漏极与存储单元的第二位线BLB以及第二晶体管M2的栅极连接，所述第八晶体管M8的源极与接地电压节点连接，所述第八晶体管M8的栅极与第二晶体管M2的栅极连接。In this embodiment, it further includes: an eighth transistor M8, the drain of the eighth transistor M8 is connected to the second bit line BLB of the memory cell and the gate of the second transistor M2, and the source of the eighth transistor M8 The pole is connected to the ground voltage node, and the gate of the eighth transistor M8 is connected to the gate of the second transistor M2.
所述第八晶体管M8起到镜像电流的作用，流经第八晶体管M8的电流镜像至第二晶体管M2。The eighth transistor M8 functions as a mirror current, and the current flowing through the eighth transistor M8 is mirrored to the second transistor M2.
在其他实施例中，所述电路还能够不包括所述第八晶体管M8。In other embodiments, the circuit can also not include the eighth transistor M8.
在本实施例中，所述第八晶体管M8为N型晶体管。In this embodiment, the eighth transistor M8 is an N-type transistor.
在本实施例中，还包括：第九晶体管M9，所述第九晶体管M9的漏极与存储单元的第一位线BL以及与第一晶体管M1的栅极连接，所述第九晶体管M9的源极与接地电压节点连接，所述第九晶体管M9的栅极与第一晶体管M1的栅极连接。In this embodiment, it further includes: a ninth transistor M9, the drain of the ninth transistor M9 is connected to the first bit line BL of the memory cell and the gate of the first transistor M1, the ninth transistor M9 has a drain The source is connected to the ground voltage node, and the gate of the ninth transistor M9 is connected to the gate of the first transistor M1.
所述第九晶体管M9起到镜像电流的作用，流经第九晶体管M9的电流镜像至第一晶体管M1。The ninth transistor M9 functions as a mirror current, and the current flowing through the ninth transistor M9 is mirrored to the first transistor M1.
在其他实施例中，所述电路还能够不包括所述第九晶体管M9。In other embodiments, the circuit can also not include the ninth transistor M9.
在本实施例中，所述第九晶体管M9为N型晶体管。In this embodiment, the ninth transistor M9 is an N-type transistor.
在本实施例中，还包括：第十晶体管M10，所述第十晶体管M10的漏极与第一晶体管M1的源极、第二晶体管M2的源极以及第三晶体管M3的源极连接，所述第十晶体管M10的源极与接地电压节点连接。In this embodiment, it further includes: a tenth transistor M10, the drain of the tenth transistor M10 is connected to the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3, so The source of the tenth transistor M10 is connected to the ground voltage node.
在本实施例中，所述第十晶体管M10为N型晶体管。In this embodiment, the tenth transistor M10 is an N-type transistor.
所述第十晶体管M10用作开启所述灵敏放大器电路的开关。The tenth transistor M10 is used as a switch for turning on the sense amplifier circuit.
图3是本发明另一实施例中灵敏放大器的电路示意图。FIG. 3 is a schematic circuit diagram of a sense amplifier in another embodiment of the present invention.
请参考图3，所述灵敏放大器包括：第一晶体管M1，所述第一晶体管M1的栅极与存储单元的第一位线BL连接；Please refer to FIG. 3, the sense amplifier includes: a first transistor M1, the gate of the first transistor M1 is connected to the first bit line BL of the memory cell;
第二晶体管M2，所述第二晶体管M2的栅极与存储单元的第二位线BLB连接，所述第二晶体管M2的源极与第一晶体管M1的源极连接；the second transistor M2, the gate of the second transistor M2 is connected to the second bit line BLB of the memory cell, and the source of the second transistor M2 is connected to the source of the first transistor M1;
第三晶体管M3，所述第三晶体管M3的栅极与存储单元的第二位线BLB连接，所述第三晶体管M3的源极与第二晶体管M2的源极连接，所述第一晶体管M1的源极、第二晶体管M2的源极和第三晶体管M3的源极与接地电压节点耦接，所述第一晶体管M1、第二晶体管M2和第三晶体管M3的阈值电压不同；The third transistor M3, the gate of the third transistor M3 is connected to the second bit line BLB of the memory cell, the source of the third transistor M3 is connected to the source of the second transistor M2, and the first transistor M1 The source of the second transistor M2 and the source of the third transistor M3 are coupled to the ground voltage node, and the threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different;
镜像单元，所述镜像单元包括被镜像端、第一镜像端和第二镜像端，所述被镜像端与第一晶体管M1的漏极连接，所述第一镜像端与第二晶体管M2的漏极连接，所述第二镜像端与第三晶体管M3的漏极连接；a mirroring unit, the mirroring unit includes a mirrored terminal, a first mirrored terminal and a second mirrored terminal, the mirrored terminal is connected to the drain of the first transistor M1, and the first mirrored terminal is connected to the drain of the second transistor M2 The second mirror terminal is connected to the drain of the third transistor M3;
检测单元T，所述镜像单元的第一镜像端与检测单元T连接，所述镜像单元的第二镜像端与检测单元T连接。In the detection unit T, the first mirror end of the mirror unit is connected to the detection unit T, and the second mirror end of the mirror unit is connected to the detection unit T.
在本实施例中，所述镜像单元被镜像端包括：第四晶体管M4，所述第四晶体管M4的源极与电源电压节点VDD连接，所述第四晶体管M4的漏极与第一晶体管M1的漏极连接，所述第四晶体管M4的栅极与第一晶体管M1的漏极连接。In this embodiment, the mirrored end of the mirroring unit includes: a fourth transistor M4, the source of the fourth transistor M4 is connected to the power supply voltage node VDD, and the drain of the fourth transistor M4 is connected to the first transistor M1 The drain of the fourth transistor M4 is connected to the drain of the first transistor M1.
在本实施例中，所述镜像单元第一镜像端包括：第五晶体管M5，所述第五晶体管M5的源极与电源电压节点VDD连接，所述第五晶体管M5的漏极与第二晶体管M2的漏极连接，所述第五晶体管M5的栅极与第四晶体管M4的栅极连接；所述检测单元T与第五晶体管M5的漏极连接。In this embodiment, the first mirror end of the mirror unit includes: a fifth transistor M5, the source of the fifth transistor M5 is connected to the power supply voltage node VDD, and the drain of the fifth transistor M5 is connected to the second transistor The drain of M2 is connected, the gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.
在本实施例中，所述镜像单元第二镜像端包括：第六晶体管M6，所述第六晶体管M6的源极与电源电压节点VDD连接，所述第六晶体管M6的漏极与第三晶体管M3的漏极连接，所述第六晶体管M6的栅极与第四晶体管M4的栅极以及第五晶体管M5的栅极连接；所述检测单元T与第六晶体管M6的漏极连接。In this embodiment, the second mirror terminal of the mirror unit includes: a sixth transistor M6, the source of the sixth transistor M6 is connected to the power supply voltage node VDD, and the drain of the sixth transistor M6 is connected to the third transistor The drain of M3 is connected, the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.
在本实施例中，所述第四晶体管M4为P型晶体管；第五晶体管M5为P型晶体管；所述第六晶体管M6为P型晶体管。In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; and the sixth transistor M6 is a P-type transistor.
所述第一晶体管M1、第二晶体管M2和第三晶体管M3的阈值电压不同，从而通过第一晶体管M1、第二晶体管M2和第三晶体管M3的电流大小不同，从而检测单元T能够对镜像单元第一镜像端和镜像单元第二镜像端输出的信号进行检测比较，根据比较结果的正确与否判断与灵敏放大器连接的存储单元的强弱状态，以便后续采用不同的读周期对强弱状态不同的存储单元进行读取，以提升存储器的整体读写速度，提高了存储器的性能。The threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the magnitudes of the currents passing through the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the detection unit T can detect the mirror unit The signals output by the first mirror end and the second mirror end of the mirror unit are detected and compared, and the strength state of the memory cell connected to the sense amplifier is judged according to the correctness of the comparison result, so that different read cycles can be used for different strength states. The storage unit is read, so as to improve the overall read and write speed of the memory and improve the performance of the memory.
在本实施例中，所述第一晶体管M1的阈值电压大于第二晶体管M2的阈值电压；所述第三晶体管M3的阈值电压大于第一晶体管M1的阈值电压。In this embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.
从而流过所述第一晶体管M1的电流与镜像单元被镜像端的电流相同，镜像单元被镜像端的电流镜像到镜像单元第一镜像端和镜像单元第二镜像端之后，镜像单元第一镜像端的电流与流经第二晶体管M2的电流拉平，镜像单元第二镜像端的电流与流经第三晶体管M3的电流拉平，从而检测单元能够通过判断镜像单元第一镜像端的信号与镜像单元第二镜像端的信号的变化状态是否一致，来判断与灵敏放大器连接的存储单元的强弱状态。若镜像单元第一镜像端的信号与镜像单元第二镜像端的信号相同，则与灵敏放大器连接的存储单元为驱动较强的单元；若镜像单元第一镜像端的信号与镜像单元第二镜像端的信号不同，则与灵敏放大器连接的存储单元为驱动较弱的单元。Therefore, the current flowing through the first transistor M1 is the same as the current at the mirrored end of the mirroring unit. After the current at the mirrored end of the mirroring unit is mirrored to the first mirroring end of the mirroring unit and the second mirroring end of the mirroring unit, the current of the first mirroring end of the mirroring unit is mirrored. It is leveled with the current flowing through the second transistor M2, and the current at the second mirror end of the mirror unit is leveled with the current flowing through the third transistor M3, so that the detection unit can judge the signal at the first mirror end of the mirror unit and the signal at the second mirror end of the mirror unit. Whether the state of change is consistent or not, to judge the strength or weakness of the memory cell connected to the sense amplifier. If the signal of the first mirror end of the mirror unit is the same as the signal of the second mirror end of the mirror unit, the storage unit connected to the sense amplifier is the unit with stronger drive; if the signal of the first mirror end of the mirror unit is different from the signal of the second mirror end of the mirror unit , the storage unit connected with the sense amplifier is the unit with weaker drive.
在本实施例中，所述镜像单元还包括电压输入节点(未标示)，所述电压输入节点与电源电压节点VDD连接。In this embodiment, the mirror unit further includes a voltage input node (not marked), and the voltage input node is connected to the power supply voltage node VDD.
在本实施例中，还包括：第一反相器B1和第二反相器B2；所述第一反相器B1与镜像单元第一镜像端和检测单元T连接；所述第二反相器B2与镜像单元第二镜像端和检测单元T连接。In this embodiment, it further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected to the first mirror end of the mirror unit and the detection unit T; the second inverter The device B2 is connected to the second mirror end of the mirror unit and the detection unit T.
所述第一反相器B1用于对第一镜像端输出的电流信号进行整形，使到达所述检测单元T的信号为标准逻辑信号，以便所述检测单元T识别判断，所述标准逻辑信号为第一信号。所述第一信号为所述镜像端与第一镜像端的电流大小比较结果。The first inverter B1 is used to shape the current signal output by the first mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, so that the detection unit T can identify and judge, the standard logic signal for the first signal. The first signal is a result of comparing the magnitude of the current between the mirror terminal and the first mirror terminal.
所述第二反相器B2用于对第二镜像端输出的电流信号进行整形，使到达所述检测单元T的信号为标准逻辑信号，以便所述检测单元T识别判断，所述标准逻辑信号为第二信号。所述第二信号为所述镜像端与第二镜像端的电流大小比较结果。The second inverter B2 is used to shape the current signal output by the second mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, so that the detection unit T can identify and judge, the standard logic signal for the second signal. The second signal is a result of comparing the magnitude of the current between the mirror terminal and the second mirror terminal.
所述第一信号为0或1；所述第二信号为0或1。The first signal is 0 or 1; the second signal is 0 or 1.
在其他实施例中，所述电路还能够不包括所述第一反相器和第二反相器。In other embodiments, the circuit can also exclude the first inverter and the second inverter.
在本实施例中，所述第一晶体管M1为N型晶体管；第二晶体管M2为N型晶体管；所述第三晶体管M3为N型晶体管。In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; and the third transistor M3 is an N-type transistor.
在本实施例中，还包括：第十晶体管M10，所述第十晶体管M10的漏极与第一晶体管M1的源极、第二晶体管M2的源极以及第三晶体管M3的源极连接，所述第十晶体管M10的源极与接地电压节点连接。In this embodiment, it further includes: a tenth transistor M10, the drain of the tenth transistor M10 is connected to the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3, so The source of the tenth transistor M10 is connected to the ground voltage node.
在本实施例中，所述第十晶体管M10为N型晶体管。In this embodiment, the tenth transistor M10 is an N-type transistor.
所述第十晶体管M10用作开启所述灵敏放大器电路的开关。The tenth transistor M10 is used as a switch for turning on the sense amplifier circuit.
图4是本发明实施例中存储器的工作方法流程图。FIG. 4 is a flowchart of a working method of a memory in an embodiment of the present invention.
请参考图4，所述存储器的工作方法包括：Please refer to FIG. 4, the working method of the memory includes:
S100：提供存储器。S100: Provides memory.
所述存储器包括：若干存储单元，所述存储单元包括第一位线和第二位线；与存储单元连接的灵敏放大器；与灵敏放大器连接的读取单元。The memory includes: a plurality of storage units, the storage units include a first bit line and a second bit line; a sense amplifier connected with the storage unit; a read unit connected with the sense amplifier.
S101：对镜像端与第一镜像端的电流大小进行比较并输出第一信号，对镜像端与第二镜像端的电流大小进行比较并输出第二信号。S101: Compare the current magnitudes of the mirror terminal and the first mirror terminal and output a first signal, and compare the current magnitudes of the mirror terminal and the second mirror terminal to output a second signal.
S102：对所述第一镜像端的第一信号和第二镜像端的第二信号进行比较判断，获取比较结果。S102: Compare and judge the first signal of the first mirror end and the second signal of the second mirror end, and obtain a comparison result.
S103：所述读取单元获取与所述比较结果对应的读周期对存储器进行读取。S103: The reading unit acquires a read cycle corresponding to the comparison result to read the memory.
所述灵敏放大器的电路请参考图2，包括：第一晶体管M1，所述第一晶体管M1的栅极与存储单元的第一位线BL连接；第二晶体管M2，所述第二晶体管M2的栅极与存储单元的第二位线BLB连接，所述第二晶体管M2的源极与第一晶体管M1的源极连接；第三晶体管M3，所述第三晶体管M3的栅极与存储单元的第二位线BLB连接，所述第三晶体管M3的源极与第二晶体管M2的源极连接，所述第一晶体管M1的源极、第二晶体管M2的源极和第三晶体管M3的源极与接地电压节点耦接，所述第一晶体管M1、第二晶体管M2和第三晶体管M3的阈值电压不同；镜像单元，所述镜像单元包括被镜像端、第一镜像端和第二镜像端，所述被镜像端与第一晶体管M1的漏极连接，所述第一镜像端与第二晶体管M2的漏极连接，所述第二镜像端与第三晶体管M3的漏极连接；检测单元T，所述镜像单元的第一镜像端与检测单元T连接，所述镜像单元的第二镜像端与检测单元T连接。Please refer to FIG. 2 for the circuit of the sense amplifier, including: a first transistor M1, the gate of the first transistor M1 is connected to the first bit line BL of the memory cell; a second transistor M2, the second transistor M2 The gate is connected to the second bit line BLB of the memory cell, and the source of the second transistor M2 is connected to the source of the first transistor M1; the gate of the third transistor M3 is connected to the gate of the memory cell. The second bit line BLB is connected, the source of the third transistor M3 is connected to the source of the second transistor M2, the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3 The pole is coupled to the ground voltage node, and the threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different; the mirror unit includes a mirrored terminal, a first mirrored terminal and a second mirrored terminal , the mirrored terminal is connected to the drain of the first transistor M1, the first mirror terminal is connected to the drain of the second transistor M2, and the second mirror terminal is connected to the drain of the third transistor M3; the detection unit T, the first mirror end of the mirror unit is connected to the detection unit T, and the second mirror end of the mirror unit is connected to the detection unit T.
在本实施例中，所述读取单元获取对应的读周期对存储器进行读取的方法包括：若所述第一信号与第二信号相同，采用第一读周期对存储器进行读取；若所述第一信号与第二信号不同，采用第二读周期对存储器进行读取。In this embodiment, the method for the reading unit to obtain the corresponding read cycle to read the memory includes: if the first signal is the same as the second signal, using the first read cycle to read the memory; The first signal is different from the second signal, and a second read cycle is used to read the memory.
在本实施例中，所述第一读周期小于第二读周期。In this embodiment, the first read period is smaller than the second read period.
若所述第一信号与第二信号相同，则与灵敏放大器连接的存储单元为驱动较强的单元，采用较短的第一读周期对驱动较强的存储单元进行读取；若所述第一信号与第二信号不同，则与灵敏放大器连接的存储单元为驱动较弱的单元，采用较长的第二读周期对驱动较弱的存储单元进行读取。采用不同的读周期对存储器阵列中强弱状态不同的存储单元进行读取，以提升存储器的整体读写速度，提高了存储器的性能。If the first signal is the same as the second signal, the memory cell connected to the sense amplifier is the one with stronger drive, and a shorter first read cycle is used to read the memory cell with stronger drive; When a signal is different from the second signal, the memory cell connected to the sense amplifier is a cell with a weaker drive, and a longer second read cycle is used to read the memory cell with a weaker drive. Different read cycles are used to read memory cells with different strong and weak states in the memory array, so as to improve the overall read and write speed of the memory and improve the performance of the memory.
在本实施例中，所述第二读周期可以为多个。In this embodiment, the number of the second read cycles may be multiple.
在本实施例中，所述镜像单元被镜像端包括：第四晶体管M4，所述第四晶体管M4的源极与电源电压节点VDD连接，所述第四晶体管M4的漏极与第一晶体管M1的漏极连接，所述第四晶体管M4的栅极与第一晶体管M1的漏极连接。In this embodiment, the mirrored end of the mirroring unit includes: a fourth transistor M4, the source of the fourth transistor M4 is connected to the power supply voltage node VDD, and the drain of the fourth transistor M4 is connected to the first transistor M1 The drain of the fourth transistor M4 is connected to the drain of the first transistor M1.
在本实施例中，所述镜像单元第一镜像端包括：第五晶体管M5，所述第五晶体管M5的源极与电源电压节点VDD连接，所述第五晶体管M5的漏极与第二晶体管M2的漏极连接，所述第五晶体管M5的栅极与第四晶体管M4的栅极连接；所述检测单元T与第五晶体管M5的漏极连接。In this embodiment, the first mirror end of the mirror unit includes: a fifth transistor M5, the source of the fifth transistor M5 is connected to the power supply voltage node VDD, and the drain of the fifth transistor M5 is connected to the second transistor The drain of M2 is connected, the gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.
在本实施例中，所述镜像单元第二镜像端包括：第六晶体管M6，所述第六晶体管M6的源极与电源电压节点VDD连接，所述第六晶体管M6的漏极与第三晶体管M3的漏极连接，所述第六晶体管M6的栅极与第四晶体管M4的栅极以及第五晶体管M5的栅极连接；所述检测单元T与第六晶体管M6的漏极连接。In this embodiment, the second mirror terminal of the mirror unit includes: a sixth transistor M6, the source of the sixth transistor M6 is connected to the power supply voltage node VDD, and the drain of the sixth transistor M6 is connected to the third transistor The drain of M3 is connected, the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.
在本实施例中，所述第四晶体管M4为P型晶体管；第五晶体管M5为P型晶体管；所述第六晶体管M6为P型晶体管。In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; and the sixth transistor M6 is a P-type transistor.
所述第一晶体管M1、第二晶体管M2和第三晶体管M3的阈值电压不同，从而通过第一晶体管M1、第二晶体管M2和第三晶体管M3的电流大小不同，从而检测单元T能够对镜像单元第一镜像端和镜像单元第二镜像端输出的信号进行检测比较，根据比较结果的正确与否判断与灵敏放大器连接的存储单元的强弱状态，以便后续采用不同的读周期对强弱状态不同的存储单元进行读取，以提升存储器的整体读写速度，提高了存储器的性能。The threshold voltages of the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the magnitudes of the currents passing through the first transistor M1, the second transistor M2 and the third transistor M3 are different, so that the detection unit T can detect the mirror unit The signals output by the first mirror terminal and the second mirror terminal of the mirror unit are detected and compared, and the strength state of the memory cell connected to the sense amplifier is judged according to whether the comparison result is correct or not, so that different read cycles can be used for different strength states. The storage unit is read, so as to improve the overall read and write speed of the memory and improve the performance of the memory.
在本实施例中，所述第一晶体管M1的阈值电压大于第二晶体管M2的阈值电压；所述第三晶体管M3的阈值电压大于第一晶体管M1的阈值电压。In this embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.
从而流过所述第一晶体管M1的电流与镜像单元被镜像端的电流相同，镜像单元被镜像端的电流镜像到镜像单元第一镜像端和镜像单元第二镜像端之后，镜像单元第一镜像端的电流与流经第二晶体管M2的电流拉平，镜像单元第二镜像端的电流与流经第三晶体管M3的电流拉平，从而检测单元能够通过判断镜像单元第一镜像端的信号与镜像单元第二镜像端的信号的变化状态是否一致，来判断与灵敏放大器连接的存储单元的强弱状态。若镜像单元第一镜像端的信号与镜像单元第二镜像端的信号相同，则与灵敏放大器连接的存储单元为驱动较强的单元；若镜像单元第一镜像端的信号与镜像单元第二镜像端的信号不同，则与灵敏放大器连接的存储单元为驱动较弱的单元。Therefore, the current flowing through the first transistor M1 is the same as the current at the mirrored end of the mirror unit. After the current at the mirrored end of the mirror unit is mirrored to the first mirror end of the mirror unit and the second mirror end of the mirror unit, the current of the first mirror end of the mirror unit is mirrored. It is leveled with the current flowing through the second transistor M2, and the current at the second mirror end of the mirror unit is leveled with the current flowing through the third transistor M3, so that the detection unit can judge the signal at the first mirror end of the mirror unit and the signal at the second mirror end of the mirror unit. Whether the state of change is consistent or not, to judge the strength or weakness of the memory cell connected to the sense amplifier. If the signal of the first mirror end of the mirror unit is the same as the signal of the second mirror end of the mirror unit, the storage unit connected to the sense amplifier is the unit with stronger drive; if the signal of the first mirror end of the mirror unit is different from the signal of the second mirror end of the mirror unit , the storage unit connected with the sense amplifier is the unit with weaker drive.
在本实施例中，所述灵敏放大器还包括：第一反相器B1和第二反相器B2；所述第一反相器B1与镜像单元第一镜像端和检测单元T连接；所述第二反相器B2与镜像单元第二镜像端和检测单元T连接。In this embodiment, the sense amplifier further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected to the first mirror end of the mirror unit and the detection unit T; the The second inverter B2 is connected to the second mirror end of the mirror unit and the detection unit T.
所述第一反相器B1用于对第一镜像端输出的电流信号进行整形，使到达所述检测单元T的信号为标准逻辑信号，以便所述检测单元T识别判断，所述标准逻辑信号为第一信号。所述第一信号为所述镜像端与第一镜像端的电流大小比较结果。所述第二反相器B2用于对第二镜像端输出的电流信号进行整形，使到达所述检测单元T的信号为标准逻辑信号，以便所述检测单元T识别判断，所述标准逻辑信号为第二信号。所述第二信号为所述镜像端与第二镜像端的电流大小比较结果。The first inverter B1 is used to shape the current signal output by the first mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, so that the detection unit T can identify and judge, the standard logic signal for the first signal. The first signal is a result of comparing the magnitude of the current between the mirror terminal and the first mirror terminal. The second inverter B2 is used to shape the current signal output by the second mirror terminal, so that the signal reaching the detection unit T is a standard logic signal, so that the detection unit T can identify and judge, the standard logic signal for the second signal. The second signal is a result of comparing the magnitude of the current between the mirror terminal and the second mirror terminal.
所述第一信号为0或1；所述第二信号为0或1。The first signal is 0 or 1; the second signal is 0 or 1.
对镜像端与第一镜像端的电流大小进行比较的方法包括：若所述镜像端电流大于第一镜像端的电流，所述第一信号为“0”；若所述镜像端电流小于第一镜像端的电流，所述第一信号为“1”。The method for comparing the current magnitudes of the mirror terminal and the first mirror terminal includes: if the current of the mirror terminal is greater than the current of the first mirror terminal, the first signal is "0"; if the current of the mirror terminal is smaller than the current of the first mirror terminal current, the first signal is "1".
对镜像端与第二镜像端的电流大小进行比较的方法包括：若所述镜像端电流大于第二镜像端的电流，所述第二信号为“0”；若所述镜像端电流小于第二镜像端的电流，所述第二信号为“1”。The method for comparing the current magnitudes of the mirror terminal and the second mirror terminal includes: if the current of the mirror terminal is greater than the current of the second mirror terminal, the second signal is "0"; if the current of the mirror terminal is smaller than the current of the second mirror terminal current, the second signal is "1".
在本实施例中，所述第一晶体管M1为N型晶体管；第二晶体管M2为N型晶体管；所述第三晶体管M3为N型晶体管。In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; and the third transistor M3 is an N-type transistor.
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.
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