CN114822426B - Data processing method, data processing device and display panel - Google Patents
Data processing method, data processing device and display panel Download PDFInfo
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- 238000012545 processing Methods 0.000 title claims abstract description 77
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- 238000004364 calculation method Methods 0.000 claims description 19
- 230000005591 charge neutralization Effects 0.000 claims description 11
- 230000002776 aggregation Effects 0.000 abstract description 7
- 238000004220 aggregation Methods 0.000 abstract description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 19
- 238000012886 linear function Methods 0.000 description 9
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- 230000008878 coupling Effects 0.000 description 3
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- BNPSSFBOAGDEEL-UHFFFAOYSA-N albuterol sulfate Chemical compound OS(O)(=O)=O.CC(C)(C)NCC(O)C1=CC=C(O)C(CO)=C1.CC(C)(C)NCC(O)C1=CC=C(O)C(CO)=C1 BNPSSFBOAGDEEL-UHFFFAOYSA-N 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
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Abstract
The embodiment of the invention discloses a data processing method, a data processing device and a display panel, wherein the data processing method comprises the following steps: acquiring a plurality of display data; grouping the plurality of display data to obtain a plurality of groups; obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets; and time-sharing processing display data in the plurality of packets based on the plurality of output delay times and the display control signal corresponding to each of the packets. By time-sharing processing the display data in the packet, the energy aggregation generated when the display driving chip processes a large amount of signals in logic high and logic low changes can be avoided, and the EMI is greatly reduced.
Description
Technical Field
The present invention relates to the field of liquid crystal display, and in particular, to a data processing method, a data processing device, and a display panel.
Background
The Liquid crystal display (Liquid CRYSTAL DISPLAY, LCD) is often subjected to electromagnetic interference (EMI) during operation, and the normal operation of the Liquid crystal display is seriously affected when the EMI is excessive.
At present, a main source of electromagnetic interference of a liquid crystal display is a display Driver IC (Driver IC), and the display Driver IC performs signal processing, for example, an electric field and a magnetic field are generated when the display Driver IC changes between logic high and logic low. Therefore, how to effectively reduce the electromagnetic interference of the liquid crystal display is a problem to be solved.
Disclosure of Invention
The invention aims to overcome the defects and shortcomings of the prior art, and provides a data processing method, a data processing device and a display panel, which can effectively reduce the EMI during the operation of an LCD.
Specifically, in a first aspect, an embodiment of the present invention discloses a data processing method, including: acquiring a plurality of display data; grouping the plurality of display data to obtain a plurality of groups; obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets; and time-sharing processing display data in the plurality of packets based on the plurality of output delay times and the display control signal corresponding to each of the packets.
In one embodiment of the present invention, the display data in the packet is gray data, and the display control signal is a polarity inversion control signal; the time-sharing processing of the display data in the plurality of packets based on the plurality of output delay times and the display control signal corresponding to each of the packets includes: and processing the display data in each group based on the output delay times and the polarity inversion control signals to obtain at least one pair of positive and negative polarity display data corresponding to each group.
In one embodiment of the present invention, the display data in the packet is at least one pair of positive and negative polarity display data, and the display control signal is a charge sharing control signal; the time-sharing processing of the display data in the plurality of packets based on the plurality of output delay times and the display control signal corresponding to each of the packets includes: and performing charge neutralization on each pair of the positive and negative polarity display data in each of the groups based on the plurality of output delay times and the charge sharing control signal.
In one embodiment of the present invention, the grouping the plurality of display data to obtain a plurality of groups includes: and acquiring grouping configuration parameters to group the plurality of display data based on the grouping configuration parameters and grouping rules, thereby obtaining the plurality of groups.
In one embodiment of the present invention, the obtaining, based on the total delay time and the plurality of packets, a plurality of output delay times corresponding to the plurality of packets includes: and calculating and generating the plurality of output delay times based on a preset linear function, the total delay time and the plurality of packets, wherein the output delay time corresponding to a first packet in the plurality of packets is 0, and the output delay times corresponding to other packets except the first packet are sequentially and linearly increased.
In one embodiment of the present invention, the obtaining, based on the total delay time and the plurality of packets, a plurality of output delay times corresponding to the plurality of packets includes: the plurality of output delay times are generated based on a preset nonlinear function, the total delay time and the plurality of packets, wherein the plurality of packets are divided into a front part packet and a rear part packet, the front part packet corresponds to the packets in the rear part packet one by one, and the output delay times of the two packets corresponding to one are the same.
In one embodiment of the present invention, further comprising: re-grouping the plurality of pairs of positive and negative polarity display data to obtain a plurality of second groupings; obtaining a plurality of second output delay times corresponding to the plurality of second packets based on the second total delay time and the plurality of second packets; and time-sharing charge neutralization is performed on each pair of positive and negative polarity display data in each second packet based on the plurality of second output delay times and the charge sharing control signal corresponding to each second packet.
In a second aspect, an embodiment of the present invention also provides a data processing apparatus, including: the system comprises a data acquisition module, a data grouping module, a time calculation module and a data processing module. The data acquisition module is used for acquiring a plurality of display data; the data grouping module is used for grouping a plurality of display data to obtain a plurality of groups; the time calculation module is used for obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets; the data processing module is used for processing the display data in the plurality of packets in a time sharing mode based on the plurality of output delay times and the display control signals corresponding to the packets.
In one embodiment of the present invention, the display data in the packet is gray scale data, the display control signal is a polarity inversion control signal, and the data processing module is specifically configured to: processing the display data in each group based on the plurality of output delay times and the polarity inversion control signal to obtain at least one pair of positive and negative polarity display data corresponding to each group; or the display data in the group is at least one pair of positive and negative polarity display data, the display control signal is a charge sharing control signal, and the data processing module is specifically configured to: and performing charge neutralization on each pair of the positive and negative polarity display data in each of the groups based on the plurality of output delay times and the charge sharing control signal.
In a third aspect, an embodiment of the present invention further provides a display panel, including: the display device comprises a display unit array, a plurality of data lines and a display driving chip. The plurality of data lines are connected with the display unit array; the display driving chip is connected with the plurality of data lines and used for executing any one of the data processing methods.
The technical scheme has the following advantages or beneficial effects:
According to the embodiment of the invention, the display data in the grouping are grouped to process the display data in a time-sharing manner, so that energy aggregation caused by that a display driving chip processes a large amount of display data simultaneously can be avoided, and the electromagnetic interference of the liquid crystal display is effectively reduced. In addition, in the process of processing the display data in the groups in a time-sharing manner, the electric performance and the display effect of the liquid crystal display are not affected, and the electromagnetic interference of the liquid crystal display is effectively reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart showing the steps of a data processing method according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating a data processing method according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a packet with polarity inversion processing disclosed in a second embodiment of the present invention;
FIG. 4 is a schematic diagram showing the comparison of the output delay time of the first scheme and the second scheme according to the second embodiment of the present invention;
FIG. 5 is a waveform comparison diagram of the first scheme and the second scheme according to the second embodiment of the present invention;
Fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating a data processing method according to a third embodiment of the present invention;
FIG. 8 is a schematic grouping diagram of a charge sharing process disclosed in a third embodiment of the present invention;
FIG. 9 is a schematic diagram showing the comparison of output delay time of the first scheme and the second scheme according to the third embodiment of the present invention;
FIG. 10 is a waveform comparison diagram of the first scheme and the second scheme according to the third embodiment of the present invention;
FIG. 11 is a flowchart illustrating a data processing method according to a fourth embodiment of the present invention;
fig. 12 is a schematic structural diagram of a data processing apparatus according to a fifth embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more fully hereinafter with reference to the accompanying drawings and detailed description, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Some embodiments of the present invention are described in detail below with reference to the accompanying drawings. The embodiments described below and features of the embodiments may be combined with each other without conflict.
[ First embodiment ]
As shown in fig. 1, a data processing method disclosed in an embodiment of the present invention includes steps S11 to S17.
S11: acquiring a plurality of display data;
s13: grouping the plurality of display data to obtain a plurality of groups;
s15: obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets;
S17: and processing the display data in the plurality of packets in a time sharing mode based on the plurality of output delay times and the display control signals corresponding to each packet.
Specifically, the display data mentioned in step S11 is, for example, gray scale data or positive and negative polarity display data, where the mentioned gray scale data is, for example, RGB image data, and the mentioned positive and negative polarity display data is, for example, a positive and negative voltage value for driving the LED, that is, a voltage value obtained by performing polarity processing conversion on the gray scale data, and the plurality of display data mentioned in step S11 may be understood as corresponding to a plurality of adjacent data channels respectively, the plurality of adjacent data channels respectively correspond to a plurality of adjacent data lines respectively, and the plurality of adjacent data lines respectively connect a plurality of adjacent display units, for example, LEDs.
Further, step S13 includes, for example: the method comprises the steps of obtaining grouping configuration parameters to group a plurality of display data based on the grouping configuration parameters and grouping rules, and obtaining a plurality of groups.
The mentioned grouping configuration parameter is, for example, n, where the value range of n is, for example, 4-8, although the present embodiment is not limited thereto, the value of n may be adjusted according to practical situations, and the mentioned grouping rule is, for example, 2 n, where it can be understood that two adjacent display data in the plurality of display data are a basic unit. The number of packets M, i.e., m=2ζ, is available based on the packet configuration parameters and the packet rules. For example, the grouping configuration parameter n takes a value of 4, the grouping rule 2 ζ calculates the grouping number m= 2^4 as 16, and the plurality of display data is, for example, 64 display data, so that the calculation shows that the 64 display data are divided into 16 groups, and each group includes 4 display data.
Further, step S15 includes, for example: and calculating and generating the plurality of output delay times based on a preset linear function, the total delay time and the plurality of packets, wherein the output delay time corresponding to a first packet in the plurality of packets is 0, and the output delay times corresponding to other packets except the first packet are sequentially and linearly increased.
The mentioned total delay time T is set to 45ns (nanoseconds), for example, and the total delay time T may also be set to 50ns, although the specific value of the total delay time T is not limited in this embodiment, and may be set according to practical applications, and it is preferable that the mentioned total delay time satisfies T be less than or equal to 50 ns. The mentioned preset linear function is set as, for example, y= [ T/(M-1) ] X-T/(M-1), where Y represents the corresponding output delay time of each packet and X represents the corresponding packet ordinal number (the value of X is a natural number of ≡1).
Of course, the mentioned output delay time may also be calculated based on a preset nonlinear function, and in other embodiments of the present invention, step S15 includes, for example: the plurality of output delay times are generated based on a preset nonlinear function, the total delay time and the plurality of packets, wherein the plurality of packets are divided into a front part packet and a rear part packet, the front part packet corresponds to the packets in the rear part packet one by one, and the output delay times of the two packets corresponding to one are the same.
The preset nonlinear function mentioned can be a quadratic function or a piecewise function, and can be specifically designed according to practical application. The mentioned front part packet and the mentioned rear part packet each comprise e.g. M/2 groups.
The display control signal mentioned in step S17 is, for example, a polarity inversion control signal POL or a charge sharing control signal. The polarity inversion control signal POL mentioned is used to ensure the positive and negative polarities of a plurality of display data, and the polarities of the plurality of display data are inverted according to the polarity inversion control signal, thereby achieving the purpose of preventing the aging of the liquid crystal. The mentioned charge sharing control signal is used for charge neutralization of the positive and negative display data, so that the potentials of the positive and negative display data are firstly reduced to the vicinity of the common voltage VCOM, or the potentials of the positive and negative display data are firstly increased to the vicinity of the common voltage VCOM, and the power consumed in driving operation can be saved.
In summary, in the first embodiment of the present invention, the display driving chip can avoid the energy aggregation caused by processing a large amount of display data at the same time by processing the display data in the packet in a time-sharing manner, so as to effectively reduce the electromagnetic interference of the liquid crystal display. In addition, in the process of processing the display data in the groups in a time-sharing manner, the electric performance and the display effect of the liquid crystal display are not affected, and the electromagnetic interference of the liquid crystal display is effectively reduced.
[ Second embodiment ]
As shown in fig. 2, a second embodiment of the present invention discloses a data processing method, for example, including the following steps:
S11: acquiring a plurality of display data;
s13: grouping the plurality of display data to obtain a plurality of groups;
s15: obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets;
s171: and processing the display data in each group based on the plurality of output delay times and the polarity inversion control signals to obtain at least one pair of positive and negative polarity display data corresponding to each group.
In step S171, the display data mentioned is, for example, gradation data.
It should be understood that, in the data processing method disclosed in the second embodiment of the present invention, the difference between the data processing method disclosed in the first embodiment and the data processing method disclosed in the foregoing first embodiment is that the display data is a specific example of the display data mentioned in the first embodiment, that is, the gray data, and the step S171 disclosed in the present embodiment is a specific description of the step S17 disclosed in the first embodiment, and the rest of the steps are the same as those in the first embodiment, and the related description will be omitted herein with reference to the foregoing first embodiment.
For a better understanding of the present embodiment, the data processing method disclosed in the present embodiment is exemplified below with reference to fig. 2 to 6.
As shown in fig. 6, one embodiment of the present invention discloses a display panel 100 including: the display device includes a display cell array 110, a plurality of data lines DL, a plurality of gate lines GL, a display driving chip 120, and a gate driver 130. The plurality of data lines DL and the plurality of gate lines GL are connected to the display cell array 110, and the gate driver 130 is connected to the plurality of scan lines GL for supplying gate driving signals to the plurality of gate lines GL. The display driving chip 120 is connected to a plurality of data lines DL for performing the data processing method disclosed in the present embodiment. The display driving chip 120 includes a COF type source driver, for example. The mentioned display unit array 110 includes, for example, a plurality of pixels P, and the mentioned plurality of gate lines GL and the mentioned plurality of data lines DL cooperate to perform brightness display of the plurality of pixels P.
For example, the number of the data lines DL is 960, and the aforementioned number of display data can be understood as 960 when the gate driver 130 gates a certain row, for example, the first row, of the display unit array 110. Here, it can be understood that one data line corresponds to one data channel (ch), and 960 data lines DL correspond to 960 data channels ch1 to ch960.
Specifically, the plurality of display data is, for example, a plurality of gray scale data, and the number N of the plurality of gray scale data is, for example, 960, and the specific number can be specifically set according to the corresponding number of data lines. Grouping the plurality of gradation data to obtain a plurality of groups includes, for example: setting the value of the grouping configuration parameter N as 4 and setting the grouping rule 2 ζ, so as to obtain 16 groups based on the grouping configuration parameter 4 and the grouping rule 2 ζ, namely obtaining 16 groups, wherein the number of gray data in each group is N/m=960/16=60. As known from the related art, one polarity inversion control signal POL controls two adjacent gray scale data, and the number of corresponding polarity inversion control signals in each packet is (N/M)/2=60/2=30.
After obtaining the plurality of packets, for example, obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets, where calculating the plurality of output delay times corresponding to the plurality of packets may be implemented by two schemes, for example:
The first scheme is as follows: and calculating and generating a plurality of output delay times based on a preset linear function, the total delay time and a plurality of packets, wherein the output delay time corresponding to a first packet in the plurality of packets is 0, and the output delay time corresponding to other packets except the first packet is sequentially and linearly increased.
Referring to fig. 4 to 5, the total delay time T is set to 45ns, for example, and the number of groups m=16 of packets is obtained by setting the packet configuration parameters and the packet rules mentioned in the present embodiment, and then the output delay time between each packet and its neighboring packets is set to have an interval time of T/(M-1) =3ns. The analytical formula of the preset linear function is referred to as y= [ T/(M-1) ] X-T/(M-1), wherein Y represents the output delay time corresponding to each packet, and X represents the ordinal number of the corresponding packet (the value of X is a natural number starting from 1), so that the delay time calculation function y=3x-3 can be calculated based on the preset linear function, the total delay time, and the plurality of packets. As shown in fig. 4, a straight line a in the rectangular coordinate system is an image representation of the delay time calculation function y=3x-3 corresponding to the first scheme of the present embodiment.
For example, in the first scheme of the present embodiment, the gray data corresponding to chl1-chl60 is the first polarity inversion packet X1, the gray data corresponding to ch61-ch120 is the second polarity inversion packet X2, … …, and the gray data corresponding to ch901-ch960 is the sixteenth polarity inversion packet X16. As can be seen from the foregoing delay time calculation function y=3x—3, the output delay time corresponding to the first polarity inversion packet X1, i.e., X, having a value of 1 is 0ns, the output delay time corresponding to the second polarity inversion packet X2, i.e., X, having a value of 2 is 3ns, … …, and the output delay time corresponding to each polarity inversion packet is sequentially increased by 3ns, so that the output delay time corresponding to the sixteenth polarity inversion packet X16, i.e., X, having a value of 16 is 45ns.
The second scheme is as follows: and calculating and generating a plurality of output delay times based on a preset nonlinear function, the total delay time and a plurality of packets, wherein the plurality of packets are divided into a front part packet and a rear part packet, the front part packet corresponds to the packets in the rear part packet one by one, and the output delay times of the two packets corresponding to one are the same.
Referring to fig. 4 to 6, the total delay time T is set to 45ns, for example, the number of groups m=16 of the packets obtained by setting the packet configuration parameters and the packet rule mentioned in the present embodiment, the 16-group packets are divided into a front-part packet and a rear-part packet, wherein the number of groups M1 of the front-part packet is 8, and the number of groups M2 of the rear-part packet is 8, wherein the output delay time of each packet in the front-part packet corresponds to that of the rear-part packet one by one, and the output delay times of the two packets corresponding to one are the same. The analytical formula of the preset nonlinear function is, for example, a unitary quadratic equation, i.e., y= [ -4T/M (M-2) ]× [ X 2 - (1+m) x+m ], where Y represents the output delay time corresponding to each packet, X represents the ordinal number of the corresponding packet (the value of X is a natural number equal to or greater than 1), the delay time calculation function can be calculated based on the preset nonlinear function, the total delay time and a plurality of packets, when the default value of X is 1, the corresponding Y is 0, and when the value of X is M, i.e., 16, the corresponding Y is 0, and when the value of X is (M/2), i.e., 8 and (M/2+1), i.e., 9, the corresponding Y is equal to T, i.e., 45ns, so that the delay time calculation function y= -45/56 (X 2 -17x+16) can be calculated based on the preset nonlinear function, the total delay time and a plurality of packets. As shown in fig. 4-6, a curve b in the rectangular coordinate system is an image representation of a delay time calculation function y= -45/56 (X 2 -17x+16) corresponding to the second scheme of the present embodiment.
For example, in the second scheme of the present embodiment, the gray data corresponding to ch1 to ch60 is the first polarity inversion packet X1, the gray data corresponding to ch61 to ch120 is the second polarity inversion packet X2, …, the gray data corresponding to ch421 to ch480 is the eighth polarity inversion packet X8, the gray data corresponding to ch481 to ch540 is the ninth polarity inversion packet X9, …, and the gray data corresponding to ch901 to ch960 is the sixteenth polarity inversion packet X16. The total delay time is 45ns, wherein the output delay time of a first polarity inversion packet X1 in the front part packet is 0ns, which corresponds to the output delay time of a sixteenth polarity inversion packet X16 in the rear part packet, the output delay time of the sixteenth polarity inversion packet X16 is 0ns, the output delay time of an eighth polarity inversion packet X8 in the front part packet is 45ns, which corresponds to the output delay time of a ninth polarity inversion packet X9 in the rear part packet, and the output delay time of the ninth polarity inversion packet X9 in the rear part packet is 45ns, based on a preset nonlinear function y= -45/56 (X 2 -17x+16), the output delay time of the second polarity inversion packet X2 in the front part packet is 11.25ns, which corresponds to the output delay time of the fifteenth polarity inversion packet X15 in the rear part packet is 11.25ns, … …, and each polarity inversion packet sequentially obtains a corresponding output delay time according to a preset nonlinear function y= -45/56 (X 2 -17x+16).
In the data processing method disclosed in this embodiment, the display driver chips are used as implementation bodies, for example, for setting one display driver chip, when setting a plurality of display driver chips, the second solution can be understood as an optimal design solution of the first solution, and this optimal design solution can prevent each display driver chip from executing the data processing method disclosed in this embodiment when the plurality of display driver chips work together with the loaded display unit array, if each display driver chip executes the first solution, a problem of uneven left and right display occurs due to a too large delay time difference between the last display data of the previous display driver chip and the first display data of the next display driver chip between two adjacent display driver chips, and the second solution sets the output delay time of the plurality of packets to nonlinear state distribution, so that continuity of data transmission between the adjacent display driver chips can be ensured.
It should be noted that, in other schemes of the present embodiment, the preset nonlinear function mentioned above may also be other nonlinear functions, such as a nonlinear function composed of piecewise functions. And calculating and generating a plurality of output delay times based on a preset piecewise function, the total delay time and a plurality of packets, wherein the plurality of packets are divided into a front part packet and a rear part packet, the front part packet corresponds to the packets in the rear part packet one by one, and the output delay times of the two packets corresponding to one are the same. Specifically, in the front partial packet, the interval time between the output delay time of each packet and its neighboring packet is the same, and in the corresponding rear partial packet, the interval time between the output delay time of each packet and its neighboring packet is also the same.
As shown in fig. 3, after obtaining output delay times of the respective packets, time-sharing processing gray data in the plurality of packets based on the plurality of output delay times and display control signals corresponding to each of the packets specifically includes: in one group, two adjacent gray Data controlled by one polarity inversion control signal POL are described, the two gray Data are input to an input selector input MUX (multiplexer), a positive polarity module and a negative polarity module are used for performing polarity inversion, the input selector input MUX inputs the two gray Data to the positive polarity module and the negative polarity module respectively for performing polarity inversion according to the polarity inversion control signal POL, the positive polarity module performs polarity processing on the input gray Data to obtain positive polarity display Data such as positive voltage, the negative polarity module performs polarity processing on the input gray Data to obtain negative polarity display Data such as negative voltage, and the positive and negative voltages are OUTPUT to an OUTPUT selector OUTPUT MUX so that the OUTPUT selector OUTPUT MUX OUTPUTs the positive and negative voltages to corresponding OUTPUT terminals s_out based on the polarity inversion control signal POL. In the display driving chip, after the 16 groups obtain the corresponding output delay time respectively, polarity inversion processing is performed on the gray data according to the polarity inversion control signal so as to output positive and negative polarity display data, wherein the time of polarity inversion processing of each group is not identical, and the time of polarity inversion processing in a single group is identical, so that energy aggregation generated by simultaneously processing the gray data is avoided, and the EMI is greatly reduced. Taking the foregoing first scheme as an example, the output delay time corresponding to the first polarity inversion packet X1 is 0ns, the output delay time corresponding to the second polarity inversion packet X2 is 3ns, … …, and the output delay time corresponding to the sixteenth polarity inversion packet X16 is 45ns, the display driver chip 120 performs the polarity processing on the data in the first polarity inversion packet X1 at, for example, time t and outputs the data, then the display driver chip 120 performs the polarity processing on the data in the second polarity inversion packet X2 at, for example, time t+3ns and outputs the data after performing the polarity processing on the data in the sixteenth polarity inversion packet X16 at, so that t can be understood as the time t when the display driver chip performs the real-time processing on the data in the first polarity inversion packet X1.
It is worth mentioning that in this process, the ns-level delay time does not affect the electrical performance and the display effect. But can reduce EMI to a great extent. The foregoing example is explained with a total delay time of 45ns, which is on the order of nanoseconds, much smaller than the polarity inversion time, and therefore does not affect polarity inversion and display.
In summary, in the second embodiment of the present invention, by time-sharing processing the gray data in the packet, the energy aggregation generated by processing a large amount of gray data by the display driving chip at the same time can be avoided, so as to effectively reduce electromagnetic interference of the liquid crystal display. In addition, in the process of time-sharing processing the gray data in the groups, the electric performance and the display effect of the liquid crystal display are not affected, and the electromagnetic interference of the liquid crystal display is effectively reduced.
[ Third embodiment ]
As shown in fig. 7, a third embodiment of the present invention discloses a data processing method, for example, including the following steps:
S11: acquiring a plurality of display data;
s13: acquiring grouping configuration parameters to group the plurality of display data based on the grouping configuration parameters and grouping rules to obtain the plurality of groups;
s15: obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets;
s172: and performing charge neutralization on the display data in each group based on the plurality of output delay times and charge sharing control signals.
The plurality of display data mentioned in step S172 are, for example, a plurality of pairs of positive and negative polarity display data, that is, the display data in each packet includes at least one pair of positive and negative polarity display data.
It should be understood that, in the data processing method disclosed in the third embodiment of the present invention, the difference between the data processing method disclosed in the first embodiment and the data processing method disclosed in the foregoing first embodiment is that the plurality of display data are one specific example of the plurality of display data in the first embodiment, that is, the plurality of pairs of positive and negative polarity display data, and the step S172 disclosed in the present embodiment is one specific description of the step S17 disclosed in the first embodiment, and the other steps are the same as those in the first embodiment, and the related description will not be repeated herein with reference to the foregoing first embodiment.
For a better understanding of the present embodiment, the data processing method disclosed in the present embodiment is exemplified below with reference to fig. 6 and fig. 7 to 10.
The data processing method disclosed in the present embodiment is performed in the display driving chip 120 of the display panel 100 shown in fig. 6, for example. For the description of the display panel 100, please refer to the first embodiment described above for the description of fig. 6, and the description is omitted here.
Specifically, the display driving chip 120 acquires a plurality of pairs of positive and negative polarity display data, for example, the pairs of positive and negative polarity display data include a positive polarity display data and a negative polarity display data, for example, 480, so that the number N of corresponding display data, for example, 960, each corresponding to one data line, and the specific number of display data may be specifically set according to the number of corresponding data lines.
After acquiring the plurality of pairs of positive and negative polarity display data, acquiring a grouping configuration parameter to group the plurality of display data based on the grouping configuration parameter and a grouping rule, to obtain the plurality of groups, for example, including: setting the value of the grouping configuration parameter N as 5 and the grouping rule as 2N, so that the grouping number M is 32 based on the grouping configuration parameter 5 and the grouping rule 2N, namely 32 groups are obtained, and the logarithm of positive and negative polarity display data in each group is N/M=480/32=15. As known in the art, one charge sharing control signal controls positive and negative polarity display data of adjacent data lines, i.e. a pair of positive and negative polarity display data, and the number of corresponding charge sharing control signals in each group is (N/M)/2=30/2=15.
After obtaining the plurality of packets, for example, obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets, where calculating the plurality of output delay times corresponding to the plurality of packets may be implemented by two schemes, for example:
The first scheme is as follows: and calculating and generating a plurality of output delay times based on a preset linear function, the total delay time and a plurality of packets, wherein the output delay time corresponding to a first packet in the plurality of packets is 0, and the output delay time corresponding to other packets except the first packet is sequentially and linearly increased.
Referring to fig. 9 to 10, the total delay time is set to, for example, 50ns, and the number of groups obtained by setting the group configuration parameters and the group rule mentioned in this embodiment is m=32, then the interval time of the output delay time between each group and its adjacent group is T/(M-1) ≡1.61ns, and the resolution of the mentioned preset linear function is y= [ T/(M-1) ] X-T/(M-1), where Y represents the output delay time corresponding to each group, and X represents the ordinal number of the corresponding group (the value of X is a natural number starting from 1). As shown in fig. 9, a straight line c in the rectangular coordinate system is an image representation of the delay time calculation function y=1.61X-1.61 corresponding to the first scheme of the present embodiment. For example, in the present embodiment, the positive and negative polarity display data corresponding to ch1 to ch30 is the first charge sharing group X1, the positive and negative polarity display data corresponding to ch31 to ch60 is the second charge sharing group X2, … …, and the positive and negative polarity display data corresponding to ch931 to ch960 is the thirty-second charge sharing group X32. As can be seen from the foregoing delay time calculation function y=1.61X-1.61, the output delay time corresponding to the first charge sharing group X1, i.e., X, having a value of 1 is 0ns, the output delay time corresponding to the second charge sharing group X2, i.e., X, having a value of 2 is about 1.61ns, … …, the output delay time corresponding to each group of charge sharing groups is sequentially increased by about 1.61ns, and the output delay time corresponding to the thirty-second charge sharing group X32, i.e., X, having a value of 32 is about 50ns.
The second scheme is as follows: and calculating and generating a plurality of output delay times based on a preset nonlinear function, the total delay time and a plurality of packets, wherein the plurality of packets are divided into a front part packet and a rear part packet, the front part packet corresponds to the packets in the rear part packet one by one, and the output delay times of the two packets corresponding to one are the same.
Referring to fig. 9 to 10, the total delay time T is set to, for example, 50ns, the packet number m=32 obtained by setting the packet configuration parameter and the packet rule mentioned in the present embodiment, the 32 packets are divided into a front portion packet and a rear portion packet, wherein the number M1 of the front portion packet is 16, and the number M2 of the rear portion packet is 16, wherein the output delay time of each packet in the front portion packet corresponds to the output delay time of the rear portion packet one by one, and the output delay time of the two packets corresponding to one is the same. The analytical formula of the preset nonlinear function is, for example, a unitary quadratic equation, i.e., y= [ -4T/M (M-2) ]× [ X 2 - (1+m) x+m ], a delay time calculation function can be calculated based on the preset nonlinear function, the total delay time, and a plurality of packets, when the default value of X is set to 1, the corresponding Y is 0, when the value of X is set to M, and when the value of X is set to 0, and when the value of X is set to (M/2+1), the corresponding Y is set to T, y= -5/24 (X 2 -33x+32) is obtained, wherein Y represents the output delay time corresponding to each packet, and X represents the ordinal number of the corresponding packet (the value of X is a natural number starting from 1). As shown in fig. 9, a curve d in the rectangular coordinate system is an image representation of a delay time calculation function y= -5/24 (X 2 -33x+32) corresponding to the second scheme of the present embodiment.
For example, in the second scheme of the present embodiment, the positive and negative polarity display data corresponding to ch1-ch30 are the first charge sharing group X1, the positive and negative polarity display data corresponding to ch31-ch60 are the second charge sharing group X2, …, the positive and negative polarity display data corresponding to ch451-ch480 are the sixteenth charge sharing group X16, the positive and negative polarity display data corresponding to ch481-ch510 are the seventeenth charge sharing group X17, …, and the positive and negative polarity display data corresponding to ch931-ch960 are the thirty second charge sharing group X32. The total delay time is 45ns, wherein the output delay time of the first charge sharing packet X1 in the front part packet is 0ns, which corresponds to the output delay time of the thirty-second charge sharing packet X32 in the rear part packet, the output delay time of the thirty-second charge sharing packet X32 is 0ns, the output delay time of the sixteenth charge sharing packet X16 in the front part packet is 50ns based on a preset nonlinear function y= -5/24 (X 2 -33x+32), the value of X is 2, the output delay time of the second charge sharing packet X2 in the front part packet is 6.25ns, which corresponds to the output of the thirty-first charge sharing packet X31 in the rear part packet, the output delay time of the thirty-first charge sharing packet X31 is 6.25ns, … …, and each charge sharing packet sequentially obtains a corresponding output delay time according to a preset nonlinear function y= -45/56 (X 2 -17x+16), wherein the output delay time of the sixteenth charge sharing packet X16 in the front part packet is 50ns, which corresponds to the output delay time of the seventeenth charge sharing packet X16 in the rear part packet is 50ns.
In the data processing method disclosed in this embodiment, the display driver chips are used as implementation bodies, for example, for setting one display driver chip, when setting a plurality of display driver chips, the second solution can be understood as an optimal design solution of the first solution, and this optimal design solution can prevent each display driver chip from executing the data processing method disclosed in this embodiment when the plurality of display driver chips work together with the loaded display unit array, if each display driver chip executes the first solution, a problem of uneven left and right display occurs due to a too large delay time difference between the last display data of the previous display driver chip and the first display data of the next display driver chip between two adjacent display driver chips, and the second solution sets the output delay time of the plurality of packets to nonlinear state distribution, so that continuity of data transmission between the adjacent display driver chips can be ensured.
It should be noted that, in other schemes of the present embodiment, the preset nonlinear function mentioned above may also be other nonlinear functions, such as a nonlinear function composed of piecewise functions. And calculating and generating a plurality of output delay times based on a preset piecewise function, the total delay time and a plurality of packets, wherein the plurality of packets are divided into a front part packet and a rear part packet, the front part packet corresponds to the packets in the rear part packet one by one, and the output delay times of the two packets corresponding to one are the same. Specifically, in the front partial packet, the interval time between the output delay time of each packet and its neighboring packet is the same, and in the corresponding rear partial packet, the interval time between the output delay time of each packet and its neighboring packet is also the same.
As shown in fig. 8, after obtaining the output delay time of each packet, charge neutralization is performed on the display data in each packet based on the plurality of output delay times and the charge sharing control signal, which specifically includes: for example, a charge sharing switch is arranged between two adjacent data lines, and a charge sharing control signal controls the charge sharing switch to perform charge sharing processing, namely, before the charge sharing control signal controls the charge sharing switch to be closed, two adjacent data lines correspondingly have a pair of positive and negative polarity display data, and when the charge sharing control signal controls the charge sharing switch to be closed, the positive and negative polarity display data are neutralized, so that the charge sharing processing is completed. It should be noted that, after the charge sharing process is completed, the display driving chip performs the next polarity inversion process. The time of each group for carrying out charge sharing processing is not identical, and the time of each group for carrying out charge sharing processing is identical, so that energy aggregation generated by simultaneously processing positive and negative polarity data is avoided, and EMI is greatly reduced. Taking the foregoing first scheme as an example, the output delay time corresponding to the first charge sharing group X1 is 0ns, the output delay time corresponding to the second charge sharing group X2 is about 1.61ns, … …, and the output delay time corresponding to the thirty-second charge sharing group X32 is 50ns, the display driver chip 120 performs the charge sharing processing on the data in the first charge sharing group X1 at, for example, time t, and then outputs the data in the second charge sharing group X2 at, for example, time t+1.61ns, and thus, the display driver chip 120 performs the charge sharing processing on the data in the thirty-second charge sharing group X32 at, for example, time t can be understood as the time when the display driver chip performs the real-time processing on the data in the first charge sharing group X1.
It is worth mentioning that in this process, the delay total time has less influence on the discharging process than the discharging total time, and does not affect the discharging and the displaying of the picture, so that the EMI can be reduced to a great extent.
In summary, in the data processing method disclosed in this embodiment, the display data in the group is processed in a time-sharing manner by grouping the plurality of display data, and obtaining the output delay time corresponding to the group based on the total delay time and the group, so as to achieve the effects of delaying the discharge time during the charge sharing operation and reducing the EMI. In the charge sharing process, the total delay time of discharge is far smaller than the total time of discharge, the discharge and the picture display are not affected, and the EMI can be reduced to a great extent.
[ Fourth embodiment ]
As shown in fig. 11, the fourth embodiment of the present invention further provides a data processing method, for example, including the following steps:
s11: acquiring a plurality of gray data;
S13: grouping the plurality of gray data to obtain a plurality of groups;
s15: obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets;
S171: processing the gray data in each group based on the plurality of output delay times and the polarity inversion control signal to obtain at least one pair of positive and negative polarity display data corresponding to each group;
S19: re-grouping the plurality of pairs of positive and negative polarity display data to obtain a plurality of second groupings;
s21: obtaining a plurality of second output delay times corresponding to the plurality of second packets based on the second total delay time and the plurality of second packets;
s23: and carrying out time-sharing charge neutralization on each pair of positive and negative polarity display data in each second grouping based on the plurality of second output delay times and the charge sharing control signals corresponding to each second grouping.
Specifically, the fourth embodiment of the present invention may be understood as a technical solution of combining the aforementioned second embodiment and third embodiment, that is, the data processing method disclosed in this embodiment may not only implement polarity time-sharing processing on gray data in multiple groups, but also further perform time-sharing charge sharing processing on multiple pairs of positive and negative polarity display data after the polarity time-sharing processing, where relevant steps may refer to the aforementioned second embodiment and third embodiment and are not repeated herein.
The second total delay time mentioned in step S21 may be the same as or different from the total delay time mentioned in step S15. The plurality of second packets mentioned in step S19 are, for example, derived from the same packet configuration parameter n as the plurality of packets mentioned in step S13, but may also be derived from different packet configuration parameters n. The steps S11 to S171 are the same as the data processing method disclosed in the second embodiment, and the steps S19 to S23 are grouping and time-sharing processes based on the positive and negative polarity display data obtained in the steps S11 to S171, and are the same as the data processing method disclosed in the third embodiment. The plurality of second packets are referred to as charge-sharing packets, the second total delay time is referred to as charge-sharing processing total delay time, and the second output delay time is referred to as output delay time corresponding to each charge-sharing packet.
The fourth embodiment of the invention can perform time-sharing processing on the gray data in the group and time-sharing processing on the positive and negative polarity display data in the group, and can avoid energy aggregation caused by that the display driving chip processes a large amount of display data at the same time, thereby effectively reducing the electromagnetic interference of the liquid crystal display. In addition, in the process of processing the display data in the groups in a time-sharing manner, the electric performance and the display effect of the liquid crystal display are not affected, and the electromagnetic interference of the liquid crystal display is effectively reduced.
[ Fifth embodiment ]
As shown in fig. 12, other embodiments of the present invention further provide a data processing apparatus 200, for example, including: a data acquisition module 210, a data grouping module 220, a time calculation module 230, and a data processing module 240. Wherein the mentioned data acquisition module 210 is configured to acquire a plurality of display data, the mentioned data grouping module 220 is configured to group the plurality of display data to obtain a plurality of groups, the mentioned time calculation module 230 is configured to obtain a plurality of output delay times corresponding to the plurality of groups based on the total delay time and the plurality of groups, and the mentioned data processing module 240 is configured to time-share-process the display data in the plurality of groups based on the plurality of output delay times and the display control signal corresponding to each group.
The display data in the packet is, for example, gray data, the display control signal is, for example, a polarity inversion control signal, and the data processing module is specifically configured to: and processing the display data in each group based on the plurality of output delay times and the polarity inversion control signals to obtain at least one pair of positive and negative polarity display data corresponding to each group.
The display data in the group is at least one pair of positive and negative polarity display data, the display control signal is a charge sharing control signal, and the data processing module is specifically configured to: each pair of positive and negative polarity display data in each group is charge-neutralized based on a plurality of output delay times and a charge sharing control signal.
Further, the data grouping module 220 is specifically configured to obtain a grouping configuration parameter, so as to group the plurality of display data based on the grouping configuration parameter and the grouping rule, thereby obtaining the plurality of groups.
Further, the time calculation module 230 is specifically configured to calculate and generate the plurality of output delay times based on a preset linear function, the total delay time, and the plurality of packets, where the output delay time corresponding to a first packet of the plurality of packets is 0, and the output delay times corresponding to other packets except the first packet sequentially increase linearly.
In other embodiments of the present invention, the time calculation module 230 is specifically configured to calculate and generate the plurality of output delay times based on a preset nonlinear function, the total delay time, and the plurality of packets, where the plurality of packets are divided into a front portion packet and a rear portion packet, the front portion packet corresponds to a packet in the rear portion packet one to one, and the output delay times of the two packets that correspond to one are the same.
Further, when the display data in the aforementioned packet is gray-scale data and the aforementioned display control signal is a polarity inversion control signal, the data processing apparatus further includes, for example: the data reprocessing module is used for grouping the plurality of pairs of positive and negative polarity display data again to obtain a plurality of second groupings; obtaining a plurality of second output delay times corresponding to the plurality of second packets based on the second total delay time and the plurality of second packets; and time-sharing charge neutralization is performed on each pair of positive and negative polarity display data in each second packet based on the plurality of second output delay times and the charge sharing control signal corresponding to each second packet.
The data processing method implemented by the data processing apparatus according to the present embodiment is as described in the foregoing embodiments, and thus will not be described in detail herein. Optionally, each module, unit and the other operations or functions described above in this embodiment are respectively for implementing the method in the foregoing embodiment.
In the several embodiments provided in the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the singular does not exclude a plurality. The units or means stated in the invention may also be implemented by one unit or means in software or hardware. "first," "second," etc. are used to indicate a name, and do not indicate any particular order.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (5)
1. A method of data processing, comprising:
Acquiring a plurality of display data;
grouping the plurality of display data to obtain a plurality of groups;
Obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets; and
Processing display data in the plurality of packets in a time-sharing manner based on the plurality of output delay times and the display control signal corresponding to each of the packets; the display control signals include a polarity inversion control signal and a charge sharing control signal;
Wherein the obtaining, based on the total delay time and the plurality of packets, a plurality of output delay times corresponding to the plurality of packets includes:
Calculating and generating the plurality of output delay times based on a preset nonlinear function, the total delay time and the plurality of packets, wherein the plurality of packets are divided into a front part packet and a rear part packet, the front part packet corresponds to the packets in the rear part packet one by one, and the output delay times of the two packets corresponding to one are the same; wherein the preset nonlinear function is Y= [ -4T/M (M-2) ]x [ X 2 - (1+M) X+M ], Y represents the corresponding output delay time of each packet, X represents the ordinal number of the corresponding packet, and T represents the total delay time; m represents the number of packets;
The display data in the packet is gray scale data; the time-sharing processing of the display data in the plurality of packets based on the plurality of output delay times and the display control signal corresponding to each of the packets includes:
Processing the display data in each group based on the plurality of output delay times and the polarity inversion control signal to obtain at least one pair of positive and negative polarity display data corresponding to each group; or alternatively
The display data in the packet is at least one pair of positive and negative polarity display data; the time-sharing processing of the display data in the plurality of packets based on the plurality of output delay times and the display control signal corresponding to each of the packets includes:
and performing charge neutralization on each pair of the positive and negative polarity display data in each of the groups based on the plurality of output delay times and the charge sharing control signal.
2. The data processing method according to claim 1, wherein grouping the plurality of display data to obtain a plurality of groups includes:
And acquiring grouping configuration parameters to group the plurality of display data based on the grouping configuration parameters and grouping rules, thereby obtaining the plurality of groups.
3. The data processing method according to claim 1, characterized by further comprising:
Re-grouping the plurality of pairs of positive and negative polarity display data to obtain a plurality of second groupings;
Obtaining a plurality of second output delay times corresponding to the plurality of second packets based on the second total delay time and the plurality of second packets; and
And carrying out time-sharing charge neutralization on each pair of positive and negative polarity display data in each second grouping based on the plurality of second output delay times and the charge sharing control signals corresponding to each second grouping.
4. A data processing apparatus, comprising:
the data acquisition module is used for acquiring a plurality of display data;
A data grouping module for grouping a plurality of display data to obtain a plurality of groups;
the time calculation module is used for obtaining a plurality of output delay times corresponding to the plurality of packets based on the total delay time and the plurality of packets; and
A data processing module, configured to time-share process display data in the plurality of packets based on the plurality of output delay times and display control signals corresponding to each of the packets; the display control signals include a polarity inversion control signal and a charge sharing control signal;
The time calculation module is specifically configured to: calculating and generating the plurality of output delay times based on a preset nonlinear function, the total delay time and the plurality of packets, wherein the plurality of packets are divided into a front part packet and a rear part packet, the front part packet corresponds to the packets in the rear part packet one by one, and the output delay times of the two packets corresponding to one are the same; wherein the preset nonlinear function is Y= [ -4T/M (M-2) ]x [ X 2 - (1+M) X+M ], Y represents the corresponding output delay time of each packet, X represents the ordinal number of the corresponding packet, and T represents the total delay time; m represents the number of packets;
the display data in the group are gray data, the display control signal is a polarity inversion control signal, and the data processing module is specifically configured to: processing the display data in each group based on the plurality of output delay times and the polarity inversion control signal to obtain at least one pair of positive and negative polarity display data corresponding to each group; or alternatively
The display data in the group is at least one pair of positive and negative polarity display data, the display control signal is a charge sharing control signal, and the data processing module is specifically configured to: and performing charge neutralization on each pair of the positive and negative polarity display data in each of the groups based on the plurality of output delay times and the charge sharing control signal.
5. A display panel, comprising:
a display cell array;
a plurality of data lines connected to the display unit array;
A display driver chip connected to the plurality of data lines for performing the data processing method of any one of claims 1 to 3.
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