CN114818573A - Iterative model establishing method and simulation method for cross-point memory array - Google Patents
Iterative model establishing method and simulation method for cross-point memory array Download PDFInfo
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Abstract
The invention discloses an iterative model establishing method and a simulation method of a cross point memory array, belonging to the field of information storage and calculation integration, wherein the model is as follows:
the simulation method comprises the following steps: (S1) initializing the voltages of the nodes in the array, and forming a voltage matrix V by the voltages of the upper node and the lower node of each memory cell up And V down (ii) a (S2) according to I arr[k‑1] ＝G⊙(V up ‑V down ) Calculating the current of each memory cell in the (k-1) th iteration, and calculating the total current flowing through each word line and each bit line; (S3) for the upper node voltage sum of each memory cell in the k iterationThe lower node voltage is updated to update V up And V down (ii) a (S4) iteratively performing (S2) to (S3) until the k-th iteration has an error smaller than epsilon than the last iteration, or a maximum number of iterations is reached. The invention can reduce the time and space complexity of the simulation cross point array.
Description
Technical Field
The invention belongs to the field of information storage and storage-computation integration, and particularly relates to an iterative model establishing method and a simulation method for a cross-point storage array.
Background
Resistive random access memories, magnetoresistive memories, phase change memories, and the like, in which memory cells construct a cross-point memory array by sandwiching memory cells between word lines and bit lines, represent stored information by using high and low values of memory cell resistance, and resistive random access memories are the most commonly used cross-point memory arrays. The positive or negative pulse with a certain amplitude is applied to two ends of the memory unit of the cross point memory array, the resistance of the memory unit can be changed, and the stored resistance can be judged according to the magnitude of the flowing current by applying a smaller reading voltage to the memory unit. Due to the existence of the interconnection line resistance, no matter the writing, reading or calculation operation is performed on the cross point array, the voltage applied by the word line is divided by the interconnection line resistance, so that the writing and reading operation fails or the error of the result of the calculation operation is too large, the cross point array considering the line resistance influence needs to be modeled, and the influence of the simulation line resistance is accurately obtained.
A Resistive Random-Access Memory (ReRAM) is a kind of double-ended passive Memory device, and as shown in fig. 1 (a), a positive or negative pulse with a certain amplitude is applied to two ends of a ReRAM unit, so that the resistance of the unit can be changed. And a smaller reading voltage is applied to the resistance value, so that the stored resistance value can be judged according to the magnitude of the flowing current.
As shown in fig. 1 (b), the ReRAM cell constructs a cross-point memory array by being sandwiched between word lines and bit lines. ReRAM cell area in cross-point array is only 4F 2 (F is the characteristic size) is an effective way to construct a large-capacity high-density storage and energy-efficient computing integrated architecture. The write, read, and compute operations for the cross-point array are described separately below.
As shown in (c) of fig. 1, a half-bias write voltage scheme is generally adopted to perform a write operation on a target cell of a cross-point array, where the target cell is at a full write voltage bias, and cells in the same row and column as the target cell are in a half-selected state, i.e., the voltage across the cells is half of the write voltage, so that only the target cell is written and other cells are not modified. As shown in FIG. 1 (d), a conventional double-ended read scheme is used for a cross-point array, i.e., a read voltage v is applied to a word line where a target cell is located rd And all other word lines and bit lines are grounded, and the reading operation is completed by detecting the current of the bit line where the target unit is located. Meanwhile, the cross point array also has the calculation capability, and the matrix vector multiplication calculation of the analog quantity can be completed in the array in situ. As shown in (e) of fig. 1, voltages involved in the calculation are applied to the word lines
And grounding all bit lines, assuming the ReRAM cell on one bit line conducts as
The current flowing on that bit line can be represented as
The primary voltage vector is completed
And ReRAM cell conductance vector
Analog quantityDot product operation between. The current output by all bit lines of the entire array results in a matrix-vector multiplication operation, where the matrix is the conductance matrix of the ReRAM cells in the cross-point array and the vector is the vector of voltages applied on the word lines.
The conventional complete model modeling approach is shown in fig. 1 (f), where an m × n cross-point array has 2mn + m + n nodes, where mn + m nodes on the word lines are planar on the cross-point array, and mn + n nodes on the bit lines are planar under the cross-point array. Each word line can be regarded as a segment of line resistor r connected between nodes wl Similarly, each bit line can be regarded as a section of line resistor r connected between nodes bl Is constructed in the form of (1). Whether a write, read, or compute operation, can be considered to apply a voltage to a word line
And applying a voltage to the bit line
E.g. in computing operations
I.e. the voltage vector that is involved in the calculation,
i.e., the all 0 vector represents ground. Then, through kirchhoff's current law, the voltages of all nodes can be set up into an equation to form a linear equation system
Wherein
Is a voltage vector formed by all nodes, A is a coefficient matrix of a linear equation set established by kirchhoff current law,
is the result vector of the system of equations. Finally, the system of equations is processedAnd solving to obtain the voltage of each node, and meanwhile, calculating the current flowing out of the bit line through the node voltage so as to accurately evaluate whether the writing and reading operations are successful and calculate the accurate numerical value of the operation. Because the number of the variables of the linear equation set is 2mn + m + n, the solution space complexity of the equation set is O (m) 2 n 2 ) Time complexity of O (m) 3 n 3 )。
In general, the traditional method builds a model of the intersection point storage array based on a linear equation, and performs simulation based on the model, so that the time complexity and the space complexity are high, the simulation efficiency is low, and the simulation overhead is high.
Disclosure of Invention
Aiming at the defects and improvement requirements of the prior art, the invention provides an iterative model establishing method and a simulation method for a cross-point memory array, and aims to reduce the time and space complexity of simulating the cross-point memory array so as to improve the simulation efficiency and reduce the simulation overhead.
To achieve the above object, according to one aspect of the present invention, there is provided an iterative model building method for a cross-point memory array, the cross-point memory array using high and low values of memory cell resistance to represent stored information, the total number m of word lines and the total number n of bit lines of the cross-point memory array satisfying:
the iterative model building method of the cross-point memory array comprises the following steps: for a target memory cell located at (x, y) in a cross-point memory array, the following iterative model is established based on kirchhoff's voltage law:
wherein x and y respectively represent the numbers of the word line and the bit line where the target memory cell is located, x is more than or equal to 1 and less than or equal to m, and y is more than or equal to 1 and less than or equal to n;
representing the voltage applied to the word line in which the target memory cell is located,
indicating the voltage applied to the bit line where the target memory cell is located; r is wl Representing the line resistance, r, between two adjacent nodes on the word line bl The line resistance between two adjacent nodes on the bit line is represented; r x,y Representing the resistance of the memory cell; g max Representing the maximum conductance in the range of conductances that the memory cell can select; i is arr A matrix of currents flowing through each memory cell in the cross-point memory array;
indicating the current of the memory cell at (p, q) in the r-th iteration, the subscript r indicating the number of iterations, and the superscript (p, q) indicating the location of the memory cell.
According to another aspect of the present invention, there is provided a method for simulating a cross-point memory array based on the above iterative modeling method for a cross-point memory array, comprising the steps of:
(S1) initializing voltages of nodes in the cross-point memory array according to the word line voltage and the bit line voltage to be applied, and constituting a voltage matrix V from voltages of upper nodes of the memory cells up A voltage matrix V is formed by the voltages of the lower nodes of the memory cells down Initializing the current iteration number to be k equal to 1;
the upper node of the storage unit is a node formed by intersecting the storage unit and the word line where the storage unit is located, and the lower node of the storage unit is a node formed by intersecting the storage unit and the bit line where the storage unit is located;
(S2) according to I arr[k-1] ＝G⊙(V up -V down ) Calculating the current flowing through each memory cell in the (k-1) th iteration, and calculating the total current flowing through each word line and the total current flowing through each bit line in the (k-1) th iteration according to the current flowing through each memory cell;
g represents a conductance matrix of each memory cell, which indicates a Hadamard product multiplied by corresponding elements of the matrix;
(S3) updating the upper node voltage and the lower node voltage of each memory cell in the k-1 th iteration according to the total current flowing through each word line and the total current flowing through each bit line in the k-1 th iteration, thereby updating the voltage matrix V up And a voltage matrix V down Updating is carried out;
(S4) iteratively executing the steps (S2) to (S3) until the difference value between the voltage of each node in the kth iteration and the voltage of each node in the (K-1) th iteration is smaller than a preset error epsilon, or the iteration frequency reaches a preset maximum iteration frequency K;
(S5) the simulation is ended with the voltage of each node in the last iteration as the simulation result.
In some alternative embodiments, initializing the voltages of the nodes in the cross-point memory array according to the word line voltage and the bit line voltage to be applied in step (S1) includes:
initializing the voltage of each node on the word line to the voltage applied on the corresponding word line; the voltage at each node on a bit line is initialized to the voltage applied to the corresponding bit line.
In some alternative embodiments, initializing the voltages of the nodes in the cross-point memory array according to the word line voltage and the bit line voltage to be applied in step (S1) includes:
according to the word line voltage and the bit line voltage to be applied and the conductance matrix G of each storage unit, searching a corresponding node initial voltage matrix from a pre-established mapping table, and correspondingly initializing the voltage of each node according to the node initial voltage matrix;
the node initial voltage matrix is used for recording the voltage initial value of each node in the simulation process, and the mapping table is used for recording the corresponding relation between the combination of the word line voltage, the bit line voltage and the conductance matrix and the node initial voltage matrix.
Further, the maximum number of iterations K is set as follows:
when the conductance of each memory cell is the maximum conductance, executing the step (S1), after the initialization is completed, iteratively executing the steps (S2) to (S3) until a preset relative error delta is reached;
assigning the value of the iteration number K of the last iteration to the maximum iteration number K;
the relative error is the error of each node voltage obtained by simulation relative to the actual voltage of each node.
Further, in the step (S2), and calculating the total current flowing through each word line and the total current flowing through each bit line in the (k-1) th iteration according to the current flowing through each memory cell, the method includes:
according to
Calculating the total current flowing through the p word lines, wherein p is more than or equal to 1 and less than or equal to m;
according to
And calculating the total current flowing through the q bit word lines, wherein q is more than or equal to 1 and less than or equal to n.
Further, in step (S4), updating the upper node voltage and the lower node voltage of each memory cell in the kth iteration according to the total current flowing through each word line and the total current flowing through each bit line in the kth-1 th iteration includes:
sequentially updating the upper node voltages of the memory cells on the 1 st to nth bit lines, comprising: according to
After updating the voltage of the upper node of the memory cell on the 1 st bit line, according to the method
Updating the word line current; according to
After updating the voltage of the upper node of the memory cell on the jth bit line, according to the method
Updating the word line current; j is 2,3, … n;
update in sequence toThe lower node voltage of the memory cells on m-1 word lines comprises: according to
After the lower node voltage of the memory cell on the m-th word line
Updating the bit line current; according to
After the lower node voltage of the memory cell on the ith word line
Updating the bit line current; i-m-1, m-2, …, 1;
wherein, V wl A voltage vector formed by voltages applied to the word lines, I wl A current vector composed of the currents flowing through the respective word lines calculated in the step (S2); v bl A voltage vector formed by the voltages applied to each bit line, I bl A current vector composed of the currents flowing through the respective bit lines calculated in the step (S2);
a voltage vector consisting of the voltages at the upper nodes of the memory cells on the 1 st bit line,
a voltage vector consisting of the voltages at the upper nodes of the memory cells on the jth bit line,
a current vector consisting of the currents flowing in the memory cells on the 1 st bit line in the (k-1) th iteration,
a current vector consisting of currents flowing in the storage unit on the jth bit line in the (k-1) th iteration;
a voltage vector consisting of the voltages of the lower nodes of the memory cells on the mth word line,
a voltage vector consisting of the voltages of the lower nodes of the memory cells on the ith word line,
a current vector consisting of the currents flowing in the memory cells on the mth word line in the (k-1) th iteration,
and forming a current vector by the current flowing in the memory cell on the ith word line in the (k-1) th iteration.
According to yet another aspect of the present invention, there is provided a computer readable storage medium comprising a stored computer program; when the computer readable storage medium is executed by the processor, the device on which the computer readable storage medium is located is controlled to execute the iterative model building method for the cross-point storage array provided by the invention and/or the simulation method for the cross-point storage array provided by the invention.
Generally, according to the above technical solutions of the present invention, a model of the cross-point memory array is established by establishing an iterative sequence, based on the model, when the simulation is performed on the cross-point memory array, the influence of line resistance can be fully considered, and the time complexity of updating the current flowing through the memory cell each time and the time complexity of updating the node voltage are all o (mn), and in the worst case, that is, in the case where the conductance of each memory cell is the maximum conductance, log needs to be performed γ A number of iterations, wherein,
represents the iterative sequence convergence ratio, and therefore the time complexity of the simulation method is O (mn. log) γ δ); due to each timeThe simulation only needs to record the value of the node voltage, so the space complexity of the simulation method is O (mn). Compared with the traditional modeling and simulation method, the method can effectively reduce the time and space complexity of the simulation cross point array, thereby improving the simulation efficiency and reducing the simulation overhead.
Drawings
Fig. 1 is a schematic diagram of a structure and related principles of a conventional resistive random access memory; the method comprises the following steps of (a) showing a graph of resistance change of a ReRAM unit along with pulses, (b) showing a ReRAM cross-point memory array, (c) showing a half-bias write voltage write operation schematic diagram, (d) showing an all-ground read operation schematic diagram, (e) showing a matrix vector multiplication operation schematic diagram, and (f) showing a cross-point array complete model;
FIG. 2 is a schematic diagram of an iterative model building method for a cross-point memory array according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating the initialization of node voltages in the simulation method for the cross-point memory array according to the embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a simulation method of a cross-point memory array according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In the present application, the terms "first," "second," and the like (if any) in the description and the drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In order to solve the technical problems of high time complexity and high space complexity of the conventional simulation method of the cross-point memory array, the invention provides an iterative model establishing method and a simulation method of the cross-point memory array, and the overall thought of the method is as follows: under the condition of meeting the model convergence condition, the model of the cross point storage array is established in an iterative sequence establishing mode, and the time complexity and the space complexity of the subsequent simulation based on the model are effectively reduced under the condition that the established model can accurately reflect the relation between the current and the voltage in the cross point storage array.
The following are examples.
Example 1:
an iterative model building method of a cross point memory array; in the embodiment, the cross-point memory array represents the stored information by using the high and low values of the resistance of the memory cell, and the total number m of the word lines and the total number n of the bit lines of the cross-point memory array satisfy the following conditions:
in this embodiment, the iterative model building method for a cross-point memory array includes: for a target memory cell located at (x, y) in a cross-point memory array, the following iterative model is established based on kirchhoff's voltage law:
wherein x and y respectively represent the numbers of the word line and the bit line where the target memory cell is located, x is more than or equal to 1 and less than or equal to m, and y is more than or equal to 1 and less than or equal to n;
representing the voltage applied to the word line in which the target memory cell is located,
indicating the voltage applied to the bit line where the target memory cell is located; r is wl Representing the line resistance, r, between two adjacent nodes on the word line bl The line resistance between two adjacent nodes on the bit line is represented; r x,y Representing the resistance of the memory cell; g max Representing the maximum conductance in the range of conductances that the memory cell can select; i is arr A matrix of currents flowing through each memory cell in the cross-point memory array;
indicating the current of the memory cell at (p, q) in the r-th iteration, the subscript r indicating the number of iterations, and the superscript (p, q) indicating the location of the memory cell.
The cross-point memory array model established in this embodiment is an iterative sequence, and on the basis of kirchhoff's voltage law, assuming that the current passing through each memory cell in the current iteration is derived from the memory cell current in the last iteration, the convergence of the model established in this embodiment is verified by combining the correlation principle.
With a current matrix I flowing through each memory cell in a cross-point memory array real Is a variable, and is a function of,
represents the current flowing in the memory cell with position (i, j); complete modeling is carried out based on kirchhoff voltage law: for a target cell with a position of (x, y) in an m × n cross-point memory array and its word line and bit line, as shown in fig. 2, the following kirchhoff voltage equation can be established:
the kirchhoff voltage equation is written in a matrix form as follows:
wherein Λ is x,y And I real Are all in a matrix of m x n,
convolution operations for two matrices of the same size; the following equations may be established for all memory cells:
in equation (1), Λ is (m) 2 )×(n 2 ) A matrix of sizes, a matrix Lambda corresponding to all memory cells x,y Composition is carried out; v represents a matrix formed by the voltage difference between two ends of all the memory cells;
a convolution operation for a step window of (m, n); here, the model is written in the form of a convolution operation, rather than a system of linear equations, to facilitate subsequent model derivation;
and (3) based on the complete model of convolution operation, namely the formula (1), establishing an iterative sequence through formula deformation so that the limit of the sequence is the simulation result of the complete model, and deducing the iterative formula of the sequence. Still for a target cell with (x, y) in an m × n cross point array and its word line and bit line, the following iterative model can be established:
in each iteration, a current matrix I flows through the cells in the cross-point memory array arr Are updated and, therefore, I is obtained arr In the above formula, "is used]"the sequence number indicates the number of iterations and is also the number of terms of the sequence; accordingly, I arr[k] Is the kth term of the sequence, I arr[k-1] Is item k-1 of the sequence; in the iterative model, the current passing through each memory cell in the current iteration (i.e. the k-th iteration) is derived from the memory cell current in the last iteration (i.e. the k-1-th iteration);
writing the above iterative model in a matrix form as follows:
Ψ x，y ＝[R x，y ]
therein, Ψ x,y A matrix of m × n;
for all cells, the following equations are established:
wherein R represents a matrix formed by the resistances of all memory cells, and psi is the matrix psi corresponding to all memory cells x，y Forming; as a hadamard product of multiplication of corresponding elements of the matrix;
further variations on equation (2) above can be written as
Wherein G represents a matrix of conductances of all the memory cells; combining equations (1) and (2), the following equation can be obtained:
subtracting I from both sides simultaneously real It is possible to obtain:
further can be simplified into:
I real -I arr[k] ＝(U-ρ)(I real -I arr[k-1] )
＝(U-ρ) k (I real -I arr[0] )
where U is the identity matrix, I arr[0] Is an initialized current matrix through each cell of the cross-point memory array, the function ρ (X) being a calculation
Therefore, it is
Thereby converging to I for the sequence real A sufficient but not necessary convergence condition is that, in any ith iteration, the current matrix I is obtained by iteration arr[i] With respect to the actual current matrix I real Error of (1) real -I arr[i] Reduced compared to the last iteration, namely:
the division, the absolute value and the less than sign are respectively carried out on each element in the matrix by corresponding division, absolute value and less than comparison of the corresponding elements, J m，n Is a full 1 matrix of size m n.
To further simplify the convergence discrimination equation, assume I real -I arr[i-1] Is equal to xi i ·J m，n In which ξ i Is an arbitrary small amount; for the above convergence condition, for a memory location at an arbitrary position (x, y) in an arbitrary ith iteration, it can be found that:
in the case where the cell conductances are the maximum conductances, i.e., the minimum resistances, the influence of the line resistances is the largest, which is called the worst case. Considering the worst case, the convergence condition discriminant of the sequence can be further simplified as:
G max presentation memory sheetMaximum conductance in the range of conductances selectable by energy, R min Is represented by the formula max Corresponding minimum resistance, G max *R min 1. From the above formula, the sequence convergence rate, i.e., the sequence convergence ratio, is γ. Therefore to achieve an acceptable relative error delta, log is required γ δ iterations. In the non-worst case, the convergence rate will be smaller, i.e., faster convergence speed; since the cross-point memory array satisfies in the present embodiment
That is, the convergence condition is satisfied, so that the iterative model established in this embodiment can finally converge to I real Based on the model, the voltage of each node in the array can be accurately calculated.
Example 2:
a simulation method of a cross-point memory array, which is provided in this embodiment based on the iterative model building method of the cross-point memory array provided in the foregoing embodiment 1, and referring to fig. 3 and fig. 4, the present embodiment includes the following steps:
(S1) initializing voltages of nodes in the cross-point memory array according to the word line voltage and the bit line voltage to be applied, and constituting a voltage matrix V from voltages of upper nodes of the memory cells up A voltage matrix V is formed by the voltages of the lower nodes of the memory cells down Initializing the current iteration number to be k-1;
the upper node of the storage unit is a node formed by intersecting the storage unit and the word line where the storage unit is located, and the lower node of the storage unit is a node formed by intersecting the storage unit and the bit line where the storage unit is located;
as an alternative implementation, in this embodiment, assuming an ideal case without line resistance at the initial time, accordingly, the voltage of each node on the word line is initialized to the voltage applied to the corresponding word line, and the voltage of each node on the bit line is initialized to the voltage applied to the corresponding bit line, as shown in fig. 3;
(S2) according to I arr[k-1] ＝G⊙(V up -V down ) Calculating the flow through the memory cells in the k-1 st iterationCalculating the total current flowing through each word line and the total current flowing through each bit line in the (k-1) th iteration according to the current flowing through each memory cell;
g represents a conductance matrix of each memory cell, which indicates a Hadamard product multiplied by corresponding elements of the matrix;
the calculation method of the total current flowing through the word line and the bit line after the current flowing through each memory cell is obtained includes:
for any p-th word line, summing currents of all memory cells on the word line in the column direction to obtain the total current flowing through the word line
Namely, it is
1≤p≤m；
For any q-th bit line, summing currents of all memory cells on the bit line in a row direction to obtain a total current flowing through the bit line
Namely, it is
1≤q≤n；
The above process of calculating the word line current and the bit line current can be abbreviated as I wl ＝sum(I arr[k-1] 0) and I bl ＝sum(I arr[k-1] 1), wherein sum (I) arr[k-1] 0) represents a pair I arr[k-1] Sum in the column direction of (a), and sum (I) arr[k-1] 1) represents a pair I arr[k-1] Summing the row directions of;
(S3) updating the upper node voltage and the lower node voltage of each memory cell in the k-1 th iteration according to the total current flowing through each word line and the total current flowing through each bit line in the k-1 th iteration, thereby updating the voltage matrix V up And a voltage matrix V down Updating is carried out;
based on kirchhoff's voltage law and kirchhoff's current law, for any pth stripWord line, voltage of 1 st node thereon
Can be controlled by the voltage applied to the word line
Minus line resistance division
Get, then update
Is composed of
Thereby obtaining the cumulative sum of the subsequent currents of the word lines, and thus
Repeating the process to update all the node voltages of the p-th row of word lines;
in the same way, the voltage of each node on the bit line can be updated;
based on the above analysis, as shown in fig. 4, in the present embodiment, the method of updating the node voltage includes:
sequentially updating the upper node voltages of the memory cells on the 1 st to nth bit lines, comprising: according to
After updating the voltage of the upper node of the memory cell on the 1 st bit line, according to the method
Updating the word line current; according to
After updating the voltage of the upper node of the memory cell on the jth bit line, according to the method
Updating the word line current; j is 2,3, … n;
sequentially updating the lower node voltages of the memory cells on the m-1 th word line, comprising: according to
After the lower node voltage of the memory cell on the m-th word line
Updating the bit line current; according to
After the lower node voltage of the memory cell on the ith word line
Updating the bit line current; i ═ m-1, m-2, …, 1;
wherein, V wl A voltage vector formed by voltages applied to the word lines, I wl A current vector composed of the currents flowing through the respective word lines calculated in the step (S2); v bl A voltage vector formed by the voltages applied to each bit line, I bl A current vector composed of the currents flowing through the respective bit lines calculated in the step (S2);
a voltage vector consisting of the voltages at the upper nodes of the memory cells on the 1 st bit line,
a voltage vector consisting of the voltages at the upper nodes of the memory cells on the jth bit line,
a current vector consisting of the currents flowing in the memory cells on the 1 st bit line in the (k-1) th iteration,
a current vector consisting of currents flowing in the memory cell on the jth bit line in the (k-1) th iteration;
a voltage vector consisting of the voltages of the lower nodes of the memory cells on the mth word line,
a voltage vector consisting of the voltages of the lower nodes of the memory cells on the ith word line,
a current vector consisting of the currents flowing in the memory cells on the mth word line in the (k-1) th iteration,
and forming a current vector by the current flowing in the memory cell on the ith word line in the (k-1) th iteration.
(S4) iteratively executing the steps (S2) to (S3) until the difference value between the voltage of each node in the kth iteration and the voltage of each node in the (K-1) th iteration is smaller than a preset error epsilon, or the iteration frequency reaches a preset maximum iteration frequency K;
(S5) in the last iteration, the voltage of each node is used as a simulation result, and the simulation is finished;
as a preferred embodiment, in the embodiment, the maximum number of iterations K is set as follows:
when the conductance of each memory cell is the maximum conductance, executing the step (S1), and after the initialization is completed, iteratively executing the steps (S2) to (S3) until the relative error is less than delta;
and assigning the value of the iteration number K of the last iteration to the maximum iteration number K.
The relative error delta is the error of each node voltage obtained by simulation relative to the actual voltage of each node;
in this embodiment, the maximum iteration number K in the iteration termination conditions is set according to the above manner, and there are two final iteration termination conditions, one of which is that the difference between the simulation results obtained by two adjacent iterations is small (smaller than the error epsilon), and the other is that the error of the simulation result obtained by the current iteration relative to the real result is small (smaller than the relative error delta), so that it is finally ensured that the obtained simulation result has high precision, and thus whether the write-in operation and the read-out operation are successful and the precise numerical value of the calculation operation can be accurately evaluated.
Example 3:
a simulation method of a cross-point memory array, the present embodiment is similar to embodiment 2 described above, except that in the step (S1) of the present embodiment, initializing voltages of nodes in the cross-point memory array according to a word line voltage and a bit line voltage to be applied, includes:
according to the word line voltage and the bit line voltage to be applied and the conductance matrix G of each storage unit, searching a corresponding node initial voltage matrix from a pre-established mapping table, and correspondingly initializing the voltage of each node according to the node initial voltage matrix;
the node initial voltage matrix is used for recording the voltage initial value of each node in the simulation process, and the mapping table is used for recording the corresponding relation between the combination of the word line voltage, the bit line voltage and the conductance matrix and the node initial voltage matrix.
Compared with the embodiment 2, in the embodiment, by pre-establishing the corresponding relationship between the combination of different word line voltages, bit line voltages and conductance matrices and the combination of the upper node initial voltage matrix and the lower node initial voltage matrix, during simulation, the corresponding upper node initial voltage matrix and the lower node initial voltage matrix are found in a table look-up manner, and the node voltages are initialized according to the search result, so that the node voltages are closer to the simulation result at the initial moment, thereby effectively reducing the iteration times required by simulation and further improving the simulation efficiency.
In this embodiment, the mapping table may be created by simulating combinations of different word line voltages, different bit line voltages, and different conductance matrices by using the simulation method described in embodiment 2, and recording the simulation result of the corresponding node voltage, thereby completing the creation of the mapping table.
Example 4:
a computer readable storage medium comprising a stored computer program; when the computer-readable storage medium is executed by the processor, the apparatus where the computer-readable storage medium is located is controlled to execute the method for establishing an iterative model of a cross point storage array provided in embodiment 1 and/or the method for simulating a cross point storage array provided in any one of embodiments 2 to 3.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. An iterative modeling method for a cross-point memory array that uses high and low values of memory cell resistance to represent stored information, wherein the total number of word lines m and the total number of bit lines n of the cross-point memory array satisfy:
the iterative model building method of the cross-point memory array comprises the following steps: for a target memory cell located at (x, y) in the cross-point memory array, establishing an iterative model based on kirchhoff's voltage law as follows:
wherein x and y respectively represent the numbers of the word line and the bit line where the target memory cell is located, x is more than or equal to 1 and less than or equal to m, and y is more than or equal to 1 and less than or equal to n;
representing the voltage applied on the word line in which the target memory cell is located,
representing the voltage applied on the bit line where the target memory cell is located; r is wl Representing the line resistance, r, between two adjacent nodes on the word line bl The line resistance between two adjacent nodes on the bit line is represented; r x,y Representing the resistance of the memory cell; g max Representing the maximum conductance in the range of conductances that the memory cell can select; i is arr A matrix of currents representing currents flowing through each memory cell in the cross-point memory array;
indicating the current of the memory cell at (p, q) in the r-th iteration, the subscript r indicating the number of iterations, and the superscript (p, q) indicating the location of the memory cell.
2. A method for simulating a cross-point memory array based on the iterative modeling method for a cross-point memory array of claim 1, comprising the steps of:
(S1) initializing voltages of nodes in the cross-point memory array according to the word line voltage and the bit line voltage to be applied, and constituting a voltage matrix V from voltages of upper nodes of the memory cells up A voltage matrix V is formed by the voltages of the lower nodes of the memory cells down Initializing the current iteration number to be k equal to 1;
the upper node of the storage unit is a node formed by intersecting the storage unit and the word line where the storage unit is located, and the lower node of the storage unit is a node formed by intersecting the storage unit and the bit line where the storage unit is located;
(S2) according to I arr[k-1] ＝G⊙(V up -V down ) Calculating the current flowing through each memory cell in the (k-1) th iteration, and calculating the total current flowing through each word line and the total current flowing through each bit line in the (k-1) th iteration according to the current flowing through each memory cell;
g represents a conductance matrix of each memory cell, which indicates a Hadamard product multiplied by corresponding elements of the matrix;
(S3) according to the secondThe total current flowing through each word line and the total current flowing through each bit line in the k-1 iteration updates the upper node voltage and the lower node voltage of each memory cell in the k iteration, thereby updating the voltage matrix V up And a voltage matrix V down Updating is carried out;
(S4) iteratively executing the steps (S2) to (S3) until the difference value between the voltage of each node in the kth iteration and the voltage of each node in the (K-1) th iteration is smaller than a preset error epsilon, or the iteration number reaches a preset maximum iteration number K;
(S5) the simulation is ended by using the voltage of each node in the last iteration as the simulation result.
3. The method for simulating a cross-point memory array of claim 2, wherein the step (S1) of initializing voltages of nodes in the cross-point memory array according to the word line voltage and the bit line voltage to be applied comprises:
initializing the voltage of each node on the word line to the voltage applied on the corresponding word line; the voltage at each node on the bit line is initialized to the voltage applied to the corresponding bit line.
4. The method for simulating a cross-point memory array of claim 2, wherein the step (S1) of initializing voltages of nodes in the cross-point memory array according to the word line voltage and the bit line voltage to be applied comprises:
according to the word line voltage and the bit line voltage to be applied and the conductance matrix G of each storage unit, searching a corresponding node initial voltage matrix from a pre-established mapping table, and initializing the voltage of each node correspondingly according to the node initial voltage matrix;
the node initial voltage matrix is used for recording the voltage initial value of each node in the simulation process, and the mapping table is used for recording the corresponding relation between the combination of the word line voltage, the bit line voltage and the conductance matrix and the node initial voltage matrix.
5. Method for simulating a cross-point memory array according to claim 3 or 4, characterized in that the maximum number of iterations K is set as follows:
when the conductance of each memory cell is the maximum conductance, executing the step (S1), and after the initialization is completed, iteratively executing the steps (S2) to (S3) until a preset relative error delta is reached;
assigning the value of the iteration number K of the last iteration to the maximum iteration number K;
the relative error is the error of each node voltage obtained by simulation relative to the actual voltage of each node.
6. The method for simulating a cross-point memory array of claim 5, wherein said step (S2) of calculating the total current flowing through each word line and the total current flowing through each bit line in the (k-1) th iteration based on the currents flowing through the memory cells comprises:
according to
Calculating the total current flowing through the p word lines, wherein p is more than or equal to 1 and less than or equal to m;
according to
And calculating the total current flowing through the q bit word lines, wherein q is more than or equal to 1 and less than or equal to n.
7. The method for simulating a cross-point memory array of claim 6, wherein the step (S4) of updating the upper node voltage and the lower node voltage of each memory cell in the k-th iteration according to the total current flowing through each word line and the total current flowing through each bit line in the k-1 th iteration comprises:
sequentially updating the upper node voltages of the memory cells on the 1 st to nth bit lines, comprising: according to
Updating memory cell on 1 st bit lineAfter the voltage of the upper node of the element, according to
Updating the word line current; according to the following
After updating the voltage of the upper node of the memory cell on the jth bit line, according to the method
Updating the word line current; j is 2,3, … n;
sequentially updating the lower node voltages of the memory cells on the m-1 th word line, comprising: according to
After the lower node voltage of the memory cell on the m-th word line is increased, the lower node voltage of the memory cell is adjusted
Updating the bit line current; according to
After the lower node voltage of the memory cell on the ith word line
Updating the bit line current; i-m-1, m-2, …, 1;
wherein, V wl A voltage vector formed by voltages applied to the word lines, I wl A current vector composed of the currents flowing through the respective word lines calculated in the step (S2); v bl A voltage vector formed by the voltages applied to each bit line, I bl A current vector composed of the currents flowing through the respective bit lines calculated in the step (S2);
is the 1 st bit lineThe voltage vector formed by the voltages of the upper nodes of the memory cells,
a voltage vector consisting of the voltages at the upper nodes of the memory cells on the jth bit line,
a current vector consisting of the currents flowing in the memory cells on the 1 st bit line in the (k-1) th iteration,
a current vector consisting of currents flowing in the memory cell on the jth bit line in the (k-1) th iteration;
a voltage vector consisting of the voltages of the lower nodes of the memory cells on the mth word line,
a voltage vector consisting of the voltages of the lower nodes of the memory cells on the ith word line,
a current vector consisting of the currents flowing in the memory cells on the mth word line in the (k-1) th iteration,
and forming a current vector by the current flowing in the memory cell on the ith word line in the (k-1) th iteration.
8. A computer-readable storage medium comprising a stored computer program; the computer readable storage medium, when executed by a processor, controls an apparatus in which the computer readable storage medium is located to perform the method for iterative modeling of a cross-point memory array of claim 1 and/or the method for simulating a cross-point memory array of any one of claims 2 to 7.
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