CN114816327A - Adder and full-digital memory computing device - Google Patents
Adder and full-digital memory computing device Download PDFInfo
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- CN114816327A CN114816327A CN202210720166.5A CN202210720166A CN114816327A CN 114816327 A CN114816327 A CN 114816327A CN 202210720166 A CN202210720166 A CN 202210720166A CN 114816327 A CN114816327 A CN 114816327A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to an adder and a full-digital memory computing device, and relates to the field of memory computing. IN the adder, an inverter I1, a tube P1, a tube N1 and a tube T1 obtain IN
The result of W, inverted by inverter I3, is the same or result, and with these two signals as the select signal, the combination of inverter I2, transfer gate T2, transfer gate T3, transfer gate T4, and transfer gate T5 yields the final Sum and Cout results; the invention can reduce the power consumption of the adder, thereby reducing the power consumption of the full digital memory computing device.
Description
Technical Field
The present invention relates to the field of memory computing, and in particular, to an adder and a full digital memory computing device.
Background
Under the big background that the data volume of the lower edge calculation is increased rapidly, the operation and data separation mode in the original von Neumann architecture is not suitable for the current times, and the problems of a storage wall and a power consumption wall are easy to generate. To address the large data volume and large throughput of convolutional neural networks, in-memory computing architectures have emerged.
The current mainstream memory computing architecture is still an analog intensive circuit, and the circuit structure is easily interfered by the outside world and has a large precision problem. The full digital memory computing circuit is gradually coming to birth. In the all-digital memory computing circuit, the power consumption of the adder tree structure occupies a main part.
Therefore, how to reduce the power consumption of the adder in the addition tree structure is a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide an adder and a full digital memory computing device, which can reduce the power consumption of the adder and further reduce the power consumption of the full digital memory computing device.
In order to achieve the purpose, the invention provides the following scheme:
an adder, comprising: inverter I1, inverter I2, inverter I3, pipe P1, pipe N1, transfer gate T1, transfer gate T2, transfer gate T3, transfer gate T4, and transfer gate T5;
an input end of the inverter I1 is connected to an input signal IN, an output end of the inverter I1 is connected to a source of the transistor N1 and a control end N of the transmission gate T1, a gate of the transistor N1 is connected to an input signal W, a drain of the transistor N1 is connected to a signal output end of the transmission gate T1, a control end P of the transmission gate T1 is connected to the input signal IN, an input end of the inverter I2 is connected to the input signal Cin, an output end of the inverter I2 is connected to a signal input end of the transmission gate T3, a signal output end of the transmission gate T3 and a signal output end of the transmission gate T2 determine an output signal Sum, a control end P of the transmission gate T3 is connected to an output end of the inverter I3, a control end N of the transmission gate T3 is connected to a signal output end of the transmission gate T1, an input end of the inverter I3 is connected to a signal output end of the transmission gate T1, an output end of the inverter I3 is connected to the control end P of the transmission gate T4 and the control end N of the transmission gate T5, a source of the transistor P1 is connected to the input signal IN, a gate of the transistor P1 is connected to the input signal W, a drain of the transistor P1 is connected to the signal output end of the transmission gate T1, a signal input end of the transmission gate T2 is connected to the input signal Cin, a control end P of the transmission gate T2 is connected to the signal output end of the transmission gate T1, a control end N of the transmission gate T2 is connected to the output end of the inverter I3, a signal input end of the transmission gate T4 is connected to the input signal Cin, a signal input end of the transmission gate T5 is connected to the input signal W, a signal output end of the transmission gate T4 and a signal output end of the transmission gate T5 determine the output signal T, a control end N of the transmission gate T4 is connected to the signal output end of the transmission gate T1, the control terminal P of the transmission gate T5 is connected with the signal output terminal of the transmission gate T1;
the input signal IN and the input signal W are addends, and the input signal Cin is carry input; the output signal Sum is a Sum bit, and the output signal Cout is a carry bit.
Optionally, the pipe P1 is a PMOS pipe.
Optionally, the transistor N1 is an NMOS transistor.
An all-digital memory computing device comprising: the device comprises an input driving module, an SRAM array module, a word line/bit line driving module, a data output module and an addition tree;
the input driving module, the word line/bit line driving module, the data output module and the addition tree are all connected with the SRAM array module;
the input driving module is used for providing an input data pulse signal;
the SRAM array module is used for storing weight and carrying out multiplication operation;
the word line/bit line driving module is used for controlling the on and off of a word line and controlling bit line precharging and reading/writing operations;
the data output module is used for performing read-write operation in a storage mode;
the addition tree includes: a plurality of adders; the addition tree is used for accumulating multiplication results.
Optionally, the SRAM array module comprises: 4 × 4 SRAM cells and 4 × 4 and gates;
the output end of each SRAM unit and the output end of the input driving module are connected with the input end of the corresponding AND gate, and the output end of the AND gate is connected with the addition tree.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the adder and the full digital memory computing device provided by the invention are characterized IN that an inverter I1, a tube P1, a tube N1 and a tube T1 obtain IN
The result of W is inverted by the inverter I3 to obtain the result of the same or the same, and the two signals are used as selection signals, and the inverter I2, the transmission gate T2, the transmission gate T3, the transmission gate T4 and the transmission gate T5 are combined to generate final Sum and Cout results, that is, the calculation of the adder is realized by using less transistor number, and the overall power consumption is further reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of an adder according to the present invention;
FIG. 2 is a schematic diagram of an all-digital memory computing device according to the present invention;
fig. 3 is a schematic structural diagram of an addition tree provided in the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide an adder and a full digital memory computing device, which can reduce the power consumption of the adder and further reduce the power consumption of the full digital memory computing device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1, an adder provided by the present invention includes: inverter I1, inverter I2, inverter I3, pipe P1, pipe N1, transfer gate T1, transfer gate T2, transfer gate T3, transfer gate T4, and transfer gate T5;
the input end of the inverter I1 is connected to an input signal IN, the output end of the inverter I1 is connected to the source of the transistor N1 and the control end N of the transmission gate T1, the gate of the transistor N1 is connected to the input signal W, the drain of the transistor N1 is connected to the signal output end of the transmission gate T1, the control end P of the transmission gate T1 is connected to the input signal IN, the input end of the inverter I2 is connected to the input signal Cin, the output end of the inverter I2 is connected to the signal input end of the transmission gate T3, the signal output end of the transmission gate T3 and the signal output end of the transmission gate T2 determine an output signal Sum, the control end P of the transmission gate T3 is connected to the output end of the inverter I3, the control end N of the transmission gate T3 is connected to the signal output end of the transmission gate T1, the input end of the inverter I3 is connected to the signal output end of the transmission gate T1, an output end of the inverter I3 is connected to the control end P of the transmission gate T4 and the control end N of the transmission gate T5, a source of the transistor P1 is connected to the input signal IN, a gate of the transistor P1 is connected to the input signal W, a drain of the transistor P1 is connected to the signal output end of the transmission gate T1, a signal input end of the transmission gate T2 is connected to the input signal Cin, a control end P of the transmission gate T2 is connected to the signal output end of the transmission gate T1, a control end N of the transmission gate T2 is connected to the output end of the inverter I3, a signal input end of the transmission gate T4 is connected to the input signal Cin, a signal input end of the transmission gate T5 is connected to the input signal W, a signal output end of the transmission gate T4 and a signal output end of the transmission gate T5 determine the output signal T, a control end N of the transmission gate T4 is connected to the signal output end of the transmission gate T1, the control terminal P of the transmission gate T5 is connected with the signal output terminal of the transmission gate T1;
the input signal IN and the input signal W are addends, and the input signal Cin is carry input; the output signal Sum is a Sum bit, and the output signal Cout is a carry bit.
Wherein, the transmission gate T1 is used for generating A when the input signal IN =0
A signal; the transmission gate T2 and the transmission gate T3 function as MUXs for selection and bit output; pass gate T4 and pass gate T5 also function as MUXs for generating carry outputs.
The pipe P1 is a PMOS pipe; the tube N1 is an NMOS tube; the tube P1 and the tube N1 are used to generate the input signal IN =1
Signal of x B.
As shown in fig. 2, the present invention provides an all-digital memory computing device, including: the device comprises an input driving module, an SRAM array module, a word line/bit line driving module, a data output module and an addition tree;
the input driving module, the word line/bit line driving module, the data output module and the addition tree are all connected with the SRAM array module;
the input driving module is used for providing an input data pulse signal; as shown IN FIG. 2, IN3[3], IN3[2], IN3[1], IN3[0], IN2[3], IN2[2], IN2[1], IN2[0], IN1[3], IN1[2], IN1[1], IN1[0], IN0[3], IN0[2], IN0[1], and IN0[0] are input pulse signals. Wherein the numbers outside the bracketed numbers represent different input signals, and the numbers in the bracketed numbers represent the number of bits of the input signals; for example IN3[2] means the 2 nd bit of the 3 rd input pulse signal.
The SRAM array module is used for storing weight and carrying out multiplication operation;
the word line/bit line driving module is used for controlling the on and off of a word line and controlling bit line precharging and reading/writing operations; the output of the word line/bit line driver module is connected to the word line WL of each row in the SRAM array module and the bit line BL and bit line BLB of each column in the SRAM array module.
The data output module is used for performing read-write operation in a storage mode; namely, during MAC operation, data is not read; and the input end of the data output module is connected with the bit line BL and the bit line BLB of each column of SRAM units for data reading.
The addition tree includes: a plurality of adders; the addition tree is used for accumulating multiplication results.
The adder is a 1-bit adder. The addition tree has 16 1bit inputs, and a 6bit addition result and a final output partial sum are obtained through addition tree operation.
As a specific embodiment, the adders in the addition tree are divided into two stages, that is, the first stage is two 4-bit adders (4 1-bit adders) and the second stage is a 5-bit adder (5 1-bit adders), so that a result of 6 bits can be obtained. The structure is a carry transmission from top to bottom, namely, adders are connected in a serial carry mode; and the sum bit is transmitted from left to right, namely the first stage takes the output result of the front stage AND gate as addend input, the second stage takes the sum of the first stage as addend input, and the sums of the front stages are added to obtain the result.
As shown in fig. 3, the addend input of the horizontal adder in the first stage is connected to the output of the and gate in the previous stage, and the output of the sum bit is connected to the addend input of the gate in the next stage; the carry input of the adder in the longitudinal direction is connected with the carry output of the adder at the previous stage, and the carry output is connected with the carry input of the adder at the next stage;
the addend input of the horizontal adder in the second stage is connected with the sum bit output of the adder in the previous stage, and the output of the sum bit is the final result; the carry input of the adder in the longitudinal direction is connected with the carry output of the adder at the previous stage, and the carry output is connected with the carry input of the adder at the next stage;
the SRAM array module includes: 4 × 4 SRAM cells and 4 × 4 and gates;
the output end of each SRAM unit and the output end of the input driving module are connected with the input end of the corresponding AND gate, and the output end of the AND gate is connected with the addition tree.
As a specific example, 4 x 4 SRAM cells are used to store 4-bit weights, one weight per column, and the storage direction corresponds to the MSB and LSB of the input pulse from top to bottom per column.
As a specific embodiment, the input driving module outputs 4 1-bit numbers per row, and each 1-bit number is connected to one end of the input end of the and gate corresponding to each SRAM cell. The AND gates in each row provide 4 1-bit output results, and all the AND gates have 16 1-bit output results.
The operation mode of the memory computing device provided by the invention is a storage mode and a computing mode.
Storage mode: the operation process of the storage mode is similar to that of the traditional SRAM array, row-column selection operation is completed through the word line/bit line driving module to write data, then bit lines BL and BLB are precharged, finally the SRAM unit for reading data is opened through the word line/bit line driving module to read data, and the final reading result is output through the data output module, so that a complete read-write operation is completed.
Calculating a mode: before the calculation mode is started, the weight is written into the SRAM array module through the process in the storage mode, and the 4-bit and 4-bit data is input into the input end of the AND gate through the input driving module. The other input of the AND gate is connected directly to the Q of the SRAM cell, and once the data write operation is complete and the data input has been entered, the bit-wise multiplication operation begins.
And finally, 16 1-bit multiplication and addition results are obtained and are sent into an addition tree, and a final output result is obtained through the addition tree array. The first stage of the addition tree array adds two 4-bit multiplication results according to bits, and two adders are called to obtain two 5-bit results; the second-stage addition tree adds the two 5-bit results to finally obtain a 6-bit partial MAC value.
Compared with a 28T structure of a traditional CMOS, the novel adder structure adopted by the invention reduces the power consumption by nearly one time under the worst condition, and the propagation delay of a critical path is not greatly influenced.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the foregoing, the description is not to be taken in a limiting sense.
Claims (5)
1. An adder, comprising: inverter I1, inverter I2, inverter I3, pipe P1, pipe N1, transfer gate T1, transfer gate T2, transfer gate T3, transfer gate T4, and transfer gate T5;
an input end of the inverter I1 is connected to an input signal IN, an output end of the inverter I1 is connected to a source of the transistor N1 and a control end N of the transmission gate T1, a gate of the transistor N1 is connected to an input signal W, a drain of the transistor N1 is connected to a signal output end of the transmission gate T1, a control end P of the transmission gate T1 is connected to the input signal IN, an input end of the inverter I2 is connected to the input signal Cin, an output end of the inverter I2 is connected to a signal input end of the transmission gate T3, a signal output end of the transmission gate T3 and a signal output end of the transmission gate T2 determine an output signal Sum, a control end P of the transmission gate T3 is connected to an output end of the inverter I3, a control end N of the transmission gate T3 is connected to a signal output end of the transmission gate T1, an input end of the inverter I3 is connected to a signal output end of the transmission gate T1, an output end of the inverter I3 is connected to the control end P of the transmission gate T4 and the control end N of the transmission gate T5, a source of the transistor P1 is connected to the input signal IN, a gate of the transistor P1 is connected to the input signal W, a drain of the transistor P1 is connected to the signal output end of the transmission gate T1, a signal input end of the transmission gate T2 is connected to the input signal Cin, a control end P of the transmission gate T2 is connected to the signal output end of the transmission gate T1, a control end N of the transmission gate T2 is connected to the output end of the inverter I3, a signal input end of the transmission gate T4 is connected to the input signal Cin, a signal input end of the transmission gate T5 is connected to the input signal W, a signal output end of the transmission gate T4 and a signal output end of the transmission gate T5 determine the output signal T, a control end N of the transmission gate T4 is connected to the signal output end of the transmission gate T1, the control terminal P of the transmission gate T5 is connected with the signal output terminal of the transmission gate T1;
the input signal IN and the input signal W are addends, and the input signal Cin is carry input; the output signal Sum is a Sum bit, and the output signal Cout is a carry bit.
2. The adder according to claim 1, wherein said pipe P1 is a PMOS pipe.
3. The adder according to claim 1, wherein said transistor N1 is an NMOS transistor.
4. An all-digital memory computing device, comprising: the device comprises an input driving module, an SRAM array module, a word line/bit line driving module, a data output module and an addition tree;
the input driving module, the word line/bit line driving module, the data output module and the addition tree are all connected with the SRAM array module;
the input driving module is used for providing an input data pulse signal;
the SRAM array module is used for storing weight and carrying out multiplication operation;
the word line/bit line driving module is used for controlling the on and off of a word line and controlling bit line precharging and reading/writing operations;
the data output module is used for performing read-write operation in a storage mode;
the addition tree includes: a plurality of adders according to any one of claims 1 to 3; the addition tree is used for accumulating multiplication results.
5. The all-digital memory computing device according to claim 4, wherein the SRAM array module comprises: 4 × 4 SRAM cells and 4 × 4 and gates;
the output end of each SRAM unit and the output end of the input driving module are connected with the input end of the corresponding AND gate, and the output end of the AND gate is connected with the addition tree.
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