CN114464239A - Memory computing unit - Google Patents
Memory computing unit Download PDFInfo
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- CN114464239A CN114464239A CN202210376261.8A CN202210376261A CN114464239A CN 114464239 A CN114464239 A CN 114464239A CN 202210376261 A CN202210376261 A CN 202210376261A CN 114464239 A CN114464239 A CN 114464239A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention relates to an in-memory computing unit. The unit includes: the device comprises an input module, a storage module and a calculation module; the input of the input module is respectively connected with unsigned input data and an input sign bit, and the output of the input module is respectively connected with a read word line RWL + and a read word line RWL-; the input module is used for carrying out positive and negative input separation of the circuit through Boolean logic operation according to unsigned input data and an input sign bit; the computing unit is respectively connected with the input module, the storage module, a reading bit line RBL + and a reading bit line RBL-; the computing unit is used for carrying out multiplication operation; the storage module is used for storing the weight data. The invention can realize positive and negative separation of input data IN [ i ] and is convenient for restoring the weight data.
Description
Technical Field
The present invention relates to the field of in-memory computing, and more particularly, to an in-memory computing unit.
Background
Most of the existing memory computing unit structures are structures which do not distinguish positive and negative and use the same word line and bit line. And the original structure has poor precision, is easy to generate interference, and is not convenient for restoring the weight data.
Therefore, there is a need for an in-memory computing unit that can achieve positive and negative separation of input data and facilitate repair of weight data.
Disclosure of Invention
The invention aims to provide an in-memory computing unit which can realize positive and negative separation of input data and is convenient for restoring weight data.
In order to achieve the purpose, the invention provides the following scheme:
an in-memory computing unit, comprising: the device comprises an input module, a storage module and a calculation module;
the input of the input module is respectively connected with unsigned input data and an input sign bit, and the output of the input module is respectively connected with a read word line RWL + and a read word line RWL-; the input module is used for carrying out positive and negative input separation of the circuit through Boolean logic operation according to unsigned input data and an input sign bit;
the computing unit is respectively connected with the input module, the storage module, a reading bit line RBL + and a reading bit line RBL-; the computing unit is used for carrying out multiplication operation;
the storage module is used for storing the weight data.
Optionally, the input module comprises: an and gate a1, an and gate a2, and an inverter I1;
the input of the AND gate A1 is connected with unsigned input data and input sign bit, and the output of the AND gate A1 is connected with a read word line RWL +;
two inputs of the AND gate A2 are respectively connected with unsigned input data and the output of the inverter I1, and the output of the AND gate A2 is connected with a read word line RWL-;
the input of the inverter I1 is connected to the input sign bit.
Optionally, the storage module comprises: two SRAM 6T memory cells.
Optionally, the calculation module comprises: tube N1, tube N2, tube N3, and tube N4;
the gate of the transistor N1 is connected with a read word line RWL +, the drain of the transistor N1 is connected with the drain of the transistor N2, and the source of the transistor N1 is connected with a read bit line RBL +; the grid electrode of the tube N2 is connected with the Q end of the SRAM 6T storage unit, and the source electrode of the tube N2 is connected with the ground wire VSS; the gate of the transistor N3 is connected to a read word line RWL-, the drain of the transistor N3 is connected to the drain of the transistor N4, and the source of the transistor N3 is connected to a read bit line RBL-; the gate of the transistor N4 is connected to the Q terminal of another SRAM 6T cell, and the source of the transistor N4 is connected to the ground line VSS.
Optionally, the tube N1, the tube N2, the tube N3, and the tube N4 are all NMOS tubes.
Optionally, the in-memory computing unit includes: a storage mode and a calculation mode.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides an IN-memory computing unit, which separates positive and negative inputs of a circuit through Boolean logic operation according to unsigned input data IN [ i ] and an input sign bit SIGNED; the split word lines and the split bit lines enable the data precision to be higher, and the output precision of more bits can be realized in large-scale integration; the weight storage and dot product calculation adopt different word lines and bit lines, so that the word lines and the bit lines do not interfere with each other, and meanwhile, the weight data can be conveniently modified.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a schematic diagram of a memory computing unit structure according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide an IN-memory computing unit which can realize positive and negative separation of input data IN [ i ] and is convenient for restoring weight data.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic structural diagram of an in-memory computing unit provided by the present invention, and as shown in fig. 1, the in-memory computing unit provided by the present invention includes: the device comprises an input module, a storage module and a calculation module;
the input of the input module is respectively connected with unsigned input data IN [ i ] and an input sign bit SIGNED, and the output of the input module is respectively connected with a read word line RWL + and a read word line RWL-; the input module is used for carrying out positive and negative input separation of the circuit through Boolean logic operation according to unsigned input data IN [ i ] and an input sign bit SIGNED;
the computing unit is respectively connected with the input module, the storage module, a reading bit line RBL + and a reading bit line RBL-; the computing unit is used for carrying out multiplication operation;
the storage module is used for storing the weight data.
The input module includes: an and gate a1, an and gate a2, and an inverter I1;
the input of the and gate a1 is connected to unsigned input data IN [ i ] and input sign bit signal, and the output of the and gate a1 is connected to read word line RWL +;
two inputs of the AND gate A2 are respectively connected with unsigned input data IN [ I ] and the output of the inverter I1, and the output of the AND gate A2 is connected with a read word line RWL-;
the input of the inverter I1 is connected to the input sign bit signal.
The memory module includes: two SRAM 6T memory cells.
The calculation module comprises: tube N1, tube N2, tube N3, and tube N4; the tube N1, the tube N2, the tube N3 and the tube N4 are all NMOS tubes.
The gate of the transistor N1 is connected with a read word line RWL +, the drain of the transistor N1 is connected with the drain of the transistor N2, and the source of the transistor N1 is connected with a read bit line RBL +; the grid electrode of the tube N2 is connected with the Q end of the SRAM 6T storage unit, and the source electrode of the tube N2 is connected with the ground wire VSS; the gate of the transistor N3 is connected to a read word line RWL-, the drain of the transistor N3 is connected to the drain of the transistor N4, and the source of the transistor N3 is connected to a read bit line RBL-; the gate of the transistor N4 is connected to the Q terminal of another SRAM 6T cell, and the source of the transistor N4 is connected to the ground line VSS.
The in-memory computing unit includes: a storage mode and a calculation mode.
The operation process is as follows:
storage mode: the storage mode is completed by the basic SRAM 6T storage unit, and the rest modules are all in the closed state. At this time, input data is stored in BL and BLB, and when the WL signal is enabled, the input is transmitted to the interior of SRAM through NMOS to be latched, and the storage operation is completed.
Calculating a mode: first, weights are stored in the SRAM in a storage mode, and RBL + and RBL-are precharged to a high potential VDD. When the input comes, the input without sign bit and the own sign bit are subjected to Boolean logic operation through an AND gate, so that positive and negative inputs respectively enter two different bit lines. To make RWL + get positive input and RWL-get negative input, table 1 is the true output table of RWL +, which realizes RWL + = SIGNED IN [ i = signal [ + ]]Table 2 is the true output table of RWL-, realized RWL- = -RWL =
The logic of (1).
TABLE 1
TABLE 2
When the input completes positive and negative separation, one word line of RWL + or RWL-is enabled, so that whether the pre-charged RBL + or RBL-is discharged or not is judged through the pipe N1, the pipe N2, the pipe N3 and the pipe N4 according to the weight stored in the SRAM, and the dot product operation is completed.
Compared with the prior art, the method has three main advantages.
The first advantage is positive and negative separation of the input data. This advantage is achieved by the preceding and gates a1, a2 and I1, the separation of positive and negative inputs being accomplished with simple boolean logic;
the second advantage is that the computation mode uses split word lines (RWL +, RWL-) and split bit lines (RBL +, RBL-). Different from a general memory computing structure, the design adopts split word lines and split bit lines to ensure that the data precision is higher, and can realize more bit output precision in large-scale integration;
a third advantage is the separation of storage and computation. In the design, different word lines and bit lines are adopted for weight storage and dot product calculation, so that the word lines and the bit lines do not interfere with each other, and meanwhile, weight data can be conveniently modified.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (6)
1. An in-memory computing unit, comprising: the device comprises an input module, a storage module and a calculation module;
the input of the input module is respectively connected with unsigned input data and an input sign bit, and the output of the input module is respectively connected with a read word line RWL + and a read word line RWL-; the input module is used for carrying out positive and negative input separation of the circuit through Boolean logic operation according to unsigned input data and an input sign bit;
the computing unit is respectively connected with the input module, the storage module, a reading bit line RBL + and a reading bit line RBL-; the computing unit is used for carrying out multiplication operation;
the storage module is used for storing the weight data.
2. The in-memory computing unit of claim 1, wherein the input module comprises: an and gate a1, an and gate a2, and an inverter I1;
the input of the AND gate A1 is connected with unsigned input data and input sign bit, and the output of the AND gate A1 is connected with a read word line RWL +;
two inputs of the AND gate A2 are respectively connected with unsigned input data and the output of the inverter I1, and the output of the AND gate A2 is connected with a read word line RWL-;
the input of the inverter I1 is connected to the input sign bit.
3. The in-memory computing unit of claim 1, wherein the storage module comprises: two SRAM 6T memory cells.
4. The in-memory computing unit of claim 3, wherein the computing module comprises: tube N1, tube N2, tube N3, and tube N4;
the gate of the transistor N1 is connected with a read word line RWL +, the drain of the transistor N1 is connected with the drain of the transistor N2, and the source of the transistor N1 is connected with a read bit line RBL +; the grid electrode of the tube N2 is connected with the Q end of the SRAM 6T storage unit, and the source electrode of the tube N2 is connected with the ground wire VSS; the gate of the transistor N3 is connected to a read word line RWL-, the drain of the transistor N3 is connected to the drain of the transistor N4, and the source of the transistor N3 is connected to a read bit line RBL-; the gate of the transistor N4 is connected to the Q terminal of another SRAM 6T cell, and the source of the transistor N4 is connected to the ground line VSS.
5. The memory computing unit of claim 4, wherein pipe N1, pipe N2, pipe N3, and pipe N4 are NMOS pipes.
6. The in-memory computing unit of any one of claims 1-5, wherein the in-memory computing unit comprises: a storage mode and a calculation mode.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114743575A (en) * | 2022-06-13 | 2022-07-12 | 中科南京智能技术研究院 | Bit line voltage difference calculating circuit for memory calculation |
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| CN111798896A (en) * | 2020-06-01 | 2020-10-20 | 北京航空航天大学 | Memory computing system supporting general computing based on magnetic random access memory |
| CN111880763A (en) * | 2020-07-14 | 2020-11-03 | 安徽大学 | SRAM circuit for realizing multiplication and addition with positive and negative numbers in memory |
| CN113268220A (en) * | 2021-07-21 | 2021-08-17 | 南京后摩智能科技有限公司 | Time domain based in-memory multiplication circuit and time domain based in-memory multiplication circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111798896A (en) * | 2020-06-01 | 2020-10-20 | 北京航空航天大学 | Memory computing system supporting general computing based on magnetic random access memory |
| CN111880763A (en) * | 2020-07-14 | 2020-11-03 | 安徽大学 | SRAM circuit for realizing multiplication and addition with positive and negative numbers in memory |
| CN113268220A (en) * | 2021-07-21 | 2021-08-17 | 南京后摩智能科技有限公司 | Time domain based in-memory multiplication circuit and time domain based in-memory multiplication circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114743575A (en) * | 2022-06-13 | 2022-07-12 | 中科南京智能技术研究院 | Bit line voltage difference calculating circuit for memory calculation |
| CN114743575B (en) * | 2022-06-13 | 2022-08-30 | 中科南京智能技术研究院 | Bit line voltage difference calculating circuit for memory calculation |
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