CN114815572A

CN114815572A - Real-time clock unit circuit capable of automatically calculating week value

Info

Publication number: CN114815572A
Application number: CN202210463902.3A
Authority: CN
Inventors: 任勇; 方梅; 邵金莎
Original assignee: Hangzhou Jinghua Microelectronics Co ltd
Current assignee: Hangzhou Jinghua Microelectronics Co ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2022-07-29

Abstract

The invention provides a real-time clock unit circuit capable of automatically calculating a week value, which comprises a second clock generator, a second counter, a minute counter, an hour counter, a day counter, a month counter, a year counter and a week counter. The real-time clock unit circuit can perform the clock timing function of year, month, day, week, hour, minute and second, can realize the perpetual calendar data of 2000-2099 years, and has the leap year correction function, the alarm clock function and the week automatic calculation function.

Description

Real-time clock unit circuit capable of automatically calculating week value

Technical Field

The invention belongs to the technical field of microelectronic/digital circuits, and particularly relates to a real-time clock unit circuit capable of automatically calculating a week value.

Background

Real-Time clocks (RTCs) are widely used in consumer electronics. Various real-time clock chips or microcontroller MCUs or SoC chips with real-time clock functional modules built in the chips are various and come out endlessly.

Currently, a commercially available real-time clock chip or an MCU or SoC chip with a real-time clock function module built therein needs to perform correct initialization setting on registers of corresponding year, month, day, week, hour, minute, second, etc. in advance, and then the real-time clock can normally operate. The setting of the registers of year, month, day, hour, minute and second does not need complex calculation and is easy to realize. However, the week and the specific year, month and day are related and are in one-to-one correspondence. When setting the week value, a software developer may need to query a paper calendar or a mobile phone or a computer with a calendar storage function, or manually calculate. When the calculation is carried out manually, a certain method must be mastered, and the calculation is troublesome and easy to make mistakes.

Some types of real-time clock chips or MCU or SoC chips with real-time clock function modules built in the chips do not provide a week register. Whereas electronic products that typically provide calendar and time functions all provide week information. In order to obtain the week information, a software developer needs to write a software function according to the year, month and day information provided inside the chip to calculate the week value.

Setting the correct week register initial value and developing the week calculation software additionally increases the workload of software developers and reduces the development efficiency. It should be noted that the week calculation program function may also occupy additional program storage space of the MCU/SoC, and when the program space capacity is small, the software developer needs to consider how to compress the program code as much as possible to save the storage space occupied by the program.

In addition, the value of the week register of the commercially available real-time clock chip or the MCU or SoC chip with the real-time clock function module built therein is not related to the year, month and day in formula calculation, but is merely a counter. If the initial value is set to be wrong, the error phenomenon that the week and the calendar are inconsistent exists after the real-time clock runs, and the error check mark does not exist. Even if the initial value setting is correct, the real-time clock may be disturbed after running, and the like, thereby causing a phenomenon that the week, the month, the day, and the like do not correspond to each other.

If the real-time clock can provide the week value, the trouble of setting the week initial value or compiling the week calculation function by software developers can be avoided, and the development efficiency is improved; meanwhile, the problem that the week value is not matched with the year, month and day value can be avoided.

Disclosure of Invention

The present invention is directed to solve the above technical problems, and provides a real-time clock unit circuit capable of automatically calculating a week value.

In order to achieve the purpose, the invention adopts the following technical scheme:

a real-time clock unit circuit capable of automatically calculating a week value comprises a second clock generator, a second counter, a minute counter, an hour counter, a day counter, a month counter, a year counter and a week counter;

the second clock generator is connected with the second counter, the second clock generator provides a 1Hz clock signal CLK _1HZ, the second counter counts seconds according to the 1Hz clock signal provided by the second clock generator, the second counter, the minute counter, the hour counter, the day counter, the month counter and the year counter are sequentially connected and respectively provide carry signals for the next counter, and the year counter, the month counter and the day counter respectively input a year value year, a month value month and a day value day to the week counter; the month counter inputs a month value month to the day counter, the year counter comprises a leap year judgment module, the leap year judgment module inputs a year value year, the leap year judgment module judges whether the leap year is the leap year according to the input year value year and outputs a leap year indication signal leap, if the leap year is the leap year, the leap output is 1, if not, the leap output is 0, and the year counter inputs the leap year indication signal leap to the day counter;

the week calculator comprises a code value conversion module, a division 4 operation module, a month correction decoding module, a summation calculation module and a surplus to 7 module, the week calculator realizes the calculation of a week value within 2000-2099 hundred years, the week calculator calculates an input year value year, a month value month and a day value day in combination with an input leap year indication signal leap, and the week calculator outputs a week value week corresponding to the day; the month correction decoding module inputs the month value month and the leap year indication signal leap output by the leap year judging module, and respectively outputs a corresponding correction decoding value to different months according to the month and leap year marks; the code value conversion module is used for converting BCD code values of the year value year and the day value day input into the week calculator into natural binary code values; the 4-dividing operation module performs 4-dividing operation on the year value year converted by the code value conversion module, the result is an integer, only a quotient value is taken as the result, and the remainder is discarded; the summation calculation module sums the year value year converted by the code value conversion module, the day value day converted by the code value conversion module, the corrected decoding value output by the month correction decoding module, and the year division 4 rounding result output by the division 4 operation 4 module; and the 7-complementation module is used for dividing the value output by the summation calculation module by 7 to carry out complementation processing, and the remainder is the output week value week corresponding to the day.

As a preferred technical solution, the real-time clock unit circuit capable of automatically calculating a week value further includes an alarm clock generator, the alarm clock generator inputs a day count value, a week count value, an hour count value, a minute count value, and a second count value, and inputs an alarm clock day value, an alarm clock week value, an alarm clock hour value, an alarm clock minute value, and an alarm clock second value according to an alarm clock, the alarm clock generator includes a first selector, a second selector, a first comparator, a second comparator, a third comparator, a fourth comparator, an or one, an or two, an or three, a nand one, an or four, and a first selector, the first selector inputs an alarm clock day value and an alarm clock week value, the second selector inputs a day count value and a week count value, and inputs a WDSEL control bit of 0 or 1 to the first selector and the second selector to select a comparison day or a week, the fourth comparator inputs an alarm clock day value, an alarm clock second output by the first selector, a second selector, and a second selector output, The alarm clock generator comprises a day/week alarm register, a time alarm register, a minute alarm register, a second alarm register, a day/week alarm register, a time alarm register, a minute alarm register and a second alarm register, wherein the alarm clock generator outputs an alarm mark FLAG if the alarm time of the alarm clock is consistent with the current time, the alarm clock generator respectively provides a shielding control bit MSK4, an MSK3, an MSK2 and an MSK1, or the alarm mark FLAG1 and the shielding control bit MSK1 signals input from the first input of the door I and output from the second input of the alarm mark FLAG2 and the shielding control bit MSK2 signals input from the second input of the door II, or the alarm mark FLAG3 and the shielding control bit MSK3 signals input from the third input of the comparator, the alarm FLAG4 and the mask control bit MSK4 signals output by the four-input-OR-gate comparator are input, the mask control bits MSK1, MSK2, MSK3 and MSK4 signals are input by the first NAND gate, the mask control bits MSK4, MSK3, MSK2 and MSK1 are alarm mask control bits of day/week, time, minute and second respectively, corresponding fields are masked when the alarm mask control bits are 1, the output of the first AND-gate, the first OR-gate, the second OR-gate, the third OR-gate, the fourth OR-gate, the first NAND-gate, the enable bit RTCEN signal and the control bit TAEN signal are input by the first AND-gate, and the alarm FLAG TAIF signal is output by the first AND-gate.

As a preferred technical solution, the real-time clock unit circuit capable of automatically calculating the week value further comprises a read-write access control circuit, the read-write access control circuit comprises a register read-write access bus, a control register RTC _ CR and a status register RTC _ SR, the second counter, the minute counter, the hour counter, the day counter, the month counter, the year counter and the week counter respectively comprise a second register, a minute register, an hour register, a day register, a month register, a year register and a week register, the register access bus is respectively connected with the second register, the minute register, the hour register, the day register, the month register, the year register, the week register, the day/week alarm register, the hour alarm register, the minute alarm register, the second alarm register, the control register RTC _ CR and the status register RTC _ SR, the control register RTC _ CR comprises a control bit TAEN and an enable bit RTCEN, the control bit TAEN and the enable bit RTCEN are connected to the alarm clock generator, the status register RTC _ SR comprises an alarm flag bit TAIF, and the alarm flag bit TAIF is connected to the alarm clock generator.

As a preferred technical solution, the control register RTC _ CR includes a register bit a12_24, the register bit a12_24 is connected to the time alarm register, the control register RTC _ CR includes a register bit N12_24, and the register bit N12_24 is connected to the hour counter.

As a preferred technical solution, the real-time clock unit circuit capable of automatically calculating the week value further includes a real-time clock interrupt circuit, the real-time clock interrupt circuit includes a third selector, a second and gate, a third and gate, a fifth or gate, a second/half second interrupt enable register RTCIE, a second/half second interrupt flag register RTCIF, an alarm clock interrupt enable register TAIE, an alarm clock interrupt flag register TAIF, the control register RTC _ CR includes an enable bit RTCEN and an RTCINTS bit for generating a selection control signal of the RTCIF flag bit, the second clock generator further provides a half second signal CLK _2HZ, the status register RTC _ SR includes an RTCIF flag bit, the three selectors input CLK _1HZ and CLK _2HZ, the selection control signal RTCINTS is connected to a selection control input terminal of the third selector, an alarm clock flag TAIF signal output by the alarm clock generator is registered to the alarm interrupt flag register TAIF, the output end of the alarm clock interrupt flag register TAIF and the output end of the alarm clock interrupt enable register TAIE are connected with the input end of the AND gate III, the output end of the AND gate II and the output end of the AND gate III are connected with the input end of the OR gate V, and the output end of the OR gate V outputs an RTC interrupt signal rtcint.

As a preferred technical scheme, the second clock generator comprises an on-chip high-frequency RC clock IHRC, an on-chip low-frequency RC clock ILRC, an external crystal oscillator clock XTOSC, a prescaler, a selector IV, an AND gate IV and a synchronous frequency divider, wherein the on-chip high-frequency RC clock IHRC is connected with the prescaler and then connected with the input end of the selector IV, the on-chip low-frequency RC clock ILRC and the external crystal oscillator clock XTOSC are connected with the input end of the selector IV, the control register RTC _ CR comprises RTCCKS [1:0] register bits, the RTCCKS [1:0] register bits are connected with the selector IV and the control input end of the synchronous frequency divider, an RTC _ CLK signal output by the selector IV, an enable bit RTCEN of the control register RTC _ CR are connected with the input end of the AND gate IV, an RTC _ GCS signal output by the AND gate IV is connected with the clock input end of the synchronous frequency divider, and the synchronous frequency divider outputs CLK _1HZ, ILRC, the external crystal oscillator clock XTOSC and the synchronous frequency divider, The CLK _2HZ signal.

As a preferred technical solution, the real-time clock unit circuit capable of automatically calculating the week value includes an APB bus, the second clock generator, the second counter, the minute counter, the hour counter, the day counter, the month counter, the year counter, and the week counter are all connected to the APB bus, the APB bus includes an APB synchronous read register, the APB synchronous read register includes a latch controller, and a year latch, a month latch, a day latch, a week latch, an hour latch, a minute latch, and a second latch connected to the latch controller, the working clock of the latch controller is a system clock sclsyk on the APB bus, and the year latch, the month latch, the day latch, the week latch, the hour latch, the minute latch, and the second latch are respectively connected to the year counter, the month counter, the day counter, the week counter, the hour latch, the minute latch, and the second latch, Hour counter, minute counter, second counter.

As a preferred technical scheme, the real-time clock unit circuit capable of automatically calculating the week value comprises an I2C/SPI bus or a UART communication port, and all registers of the real-time clock unit circuit are accessed through the I2C/SPI/UART communication port.

After the technical scheme is adopted, the invention has the following advantages:

the invention provides a real-time clock unit circuit, which can automatically calculate the week value; before the real-time clock works, the initialization setting for the week is not needed, and the week value is not calculated manually; week calculation function software does not need to be developed, so that a part of program space can be saved; the week value is calculated by a pure hardware circuit in real time, and the calculation speed is higher than that of software; the week calculation method is relatively simple, and the hardware circuit occupies relatively few logic resources; the week value changes along with the change of the annual, monthly and daily values, so that the problem that the week value and the annual, monthly and daily value are not matched can be avoided; the working clock source can be configured selectively, so that the flexibility and convenience in application are improved; when the circuit is applied to an MCU/SoC chip, the interrupts can be used by the MCU/SoC for management related to a low power consumption mode.

Drawings

FIG. 1 is a logic circuit diagram of a real time clock unit circuit that can automatically calculate week values;

FIG. 2 is a second clock generator logic circuit diagram;

FIG. 3 is a schematic view of a week counter module interface;

FIG. 4 is a logic circuit diagram of the day counter module;

FIG. 5 is a logic circuit diagram of the leap year determination module;

FIG. 6 is a computational schematic of a code value conversion module;

FIG. 7 is a logic circuit diagram of a code value conversion module;

FIG. 8 is a diagram of month correction decode logic that may be implemented;

FIG. 9 is a block diagram of a module for complementation of 7;

FIG. 10 is a logic circuit diagram of an alarm clock generator;

FIG. 11 is a logic circuit diagram of a real-time clock interrupt circuit;

FIG. 12 is a schematic diagram of a real-time clock unit circuit being hooked to an APB bus;

FIG. 13 is a logic circuit diagram of an APB synchronous read register;

FIG. 14 is a circuit diagram of a latch controller;

FIG. 15 is a schematic diagram of a real time clock unit circuit connected to an I2C/SPI bus or UART communication port;

FIG. 16 is a logic circuit diagram of the I2C interface control circuit;

FIG. 17 is a logic circuit diagram of the control circuit of the SPI communication interface;

FIG. 18 is a logic circuit diagram of a UART communication interface control circuit;

fig. 19 is a waveform diagram of the input/output timing of the day counter.

Detailed Description

The present invention will be described in further detail with reference to the following drawings and specific examples.

As shown in fig. 1, a real-time clock unit circuit capable of automatically calculating a week value includes a second clock generator, a second counter, a minute counter, an hour counter, a day counter, a month counter, a year counter, a week counter, an alarm clock generator, and a read-write access control circuit. If the alarm clock function is not needed, the alarm clock generator logic circuit can be deleted.

The real-time clock unit circuit comprises year, month, day, time, minute and second counters, and each counter corresponds to a register. Accordingly, the week calculator corresponds to a week register. The alarm clock generator corresponds to four alarm value registers of day/week, time, minute and second. The read-write access interface control circuit is correspondingly provided with a control register RTC _ CR and a status register RTC _ SR.

All register arrangements are shown in the register set of table 1, for a total of 13 bytes.

TABLE 1 register set

The register values of the year, the month, the day, the hour, the minute, the second and the week and the register values related to the alarm clock time are all represented by BCD codes.

The second clock generator is connected with the second counter, the second clock generator provides a 1Hz clock signal CLK _1HZ, the second counter counts seconds according to the 1Hz clock signal provided by the second clock generator, the second counter, the minute counter, the hour counter, the day counter, the month counter and the year counter are sequentially connected and respectively provide carry signals for the next counter, and the year counter, the month counter and the day counter respectively input a year value year, a month value month and a day value day to the week counter. The month counter inputs a month value month to the day counter, the year counter comprises a leap year judgment module, the leap year judgment module inputs a year value year, the leap year judgment module judges whether the leap year is the leap year according to the input year value year and outputs a leap year indication signal leap, if the leap year is the leap year, the leap output is 1, if not, the leap output is 0, and the year counter inputs the leap year indication signal leap to the day counter.

The real-time clock unit circuit can perform the clock timing function of year, month, day, week, hour, minute and second, can realize the perpetual calendar data of 2000-2099 years, and has the leap year correction function, the alarm clock function and the week automatic calculation function. The alarm clock function can be matched with the week/date, the time, the minute and the second and respectively provides a shielding function.

The read-write access interface control circuit bridges the interaction between an external system bus (such as an APB bus) or a communication interface (such as a UART (universal asynchronous receiver/transmitter), an SPI (serial peripheral interface), an I2C communication interface and a register inside the unit circuit. The external system bus or the communication interface can access all registers in the real-time clock unit circuit through the read-write access interface control circuit. Except that the week register is a read-only register, the rest registers are all readable and writable registers. The initial values of year, month, day, hour, minute and second, the time value of the alarm clock, the control register and the like can be set through writing operation. Calendar time information of the current year, month, day, week, hour, minute, second, status register information, and the like can be acquired by the read operation.

The read-write access control circuit comprises a register read-write access bus, a control register RTC _ CR and a status register RTC _ SR. The second counter, the minute counter, the hour counter, the day counter, the month counter, the year counter and the week counter respectively comprise a second register, a minute register, an hour register, a day register, a month register, a year register and a week register, the register access bus is respectively connected with a second register, a minute register, an hour register, a day register, a month register, a year register, a week register, a day/week alarm register, a time alarm register, a minute alarm register, a second alarm register, a control register RTC _ CR and a status register RTC _ SR, the control register RTC _ CR comprises a control bit TAEN and an enable bit RTCEN, the control bit TAEN and the enable bit RTCEN are connected with the alarm clock generator, the status register RTC _ SR comprises an alarm flag bit TAIF, and the alarm flag bit TAIF is connected with the alarm clock generator.

The control register RTC _ CR includes a register bit a12_24, the register bit a12_24 is connected to the time alarm register, the control register RTC _ CR includes a register bit N12_24, and the register bit N12_24 is connected to the hour counter.

The second clock generator provides a 1Hz clock signal CLK _1HZ for use by the second counter. While also providing the half-second signal CLK _2 HZ. The status register RTC _ SR is provided with an RTCIF flag bit, and the trigger signal of the status register RTC _ SR can select to use CLK _1HZ or CLK _2 HZ. The corresponding select control signal is the RTCINTS bit in the control register RTC _ CR. When the selected trigger signal comes, the RTCIF flag bit can be triggered to be 1. The interrupt flag bit can be cleared by writing prescribed data to the corresponding bit of the status register through the read-write access interface control circuit. The specified data can specify the use data 0 in advance, namely the status register bit is written with 0 for zero clearing; it may also be specified in advance that the use data 1, i.e. the status register bit, is write 1 clear. Whether the 1hz clock signal and the half second signal are provided will be controlled by the module enable bit RTCEN in the control register. If the module is not enabled, the second clock generator and the like do not work any more, so that the power consumption of the circuit is reduced.

The working clock source of the real-time clock is not limited to the external 32768Hz crystal oscillator clock, and other frequency generators, such as a high-frequency RC oscillator clock (for example, with a frequency in the order of megahertz) and a low-frequency RC oscillator clock (for example, with a frequency in the order of kilohertz), may be used alternatively to increase the flexibility of the circuit. The clock selection depends on the clock source selection control bits (RTCCKS) in the control register.

In MCU/SoC, the unit circuit working clock source has three options: an on-chip high-frequency RC clock IHRC (24 MHz), an on-chip low-frequency RC clock ILRC (32 kHz), and an external crystal oscillator clock XTOSC (32768 Hz). Three clock source signals are selected by the RTCCKS [1:0] register bits in the control register.

As shown in fig. 2, the second clock generator comprises an on-chip high frequency RC clock IHRC, an on-chip low frequency RC clock ILRC, an external crystal oscillator clock XTOSC, a prescaler, a selector four, an and gate four, and a synchronous divider, the on-chip high-frequency RC clock IHRC is connected with the prescaler and then is connected with the input end of the selector IV, the on-chip low-frequency RC clock ILRC and the external crystal oscillator clock XTOSC are connected with the input end of the selector IV, the control register RTC-CR comprises RTCCKS [1:0] register bits, the RTCCKS [1:0] register bits are connected with the control input ends of the four selectors and the synchronous frequency divider, the RTC _ CLK signal output by the selector four and the enabling bit RTCEN of the control register RTC _ CR are connected with the input end of the AND gate four, the RTC _ GCLK signal output by the AND gate IV is connected with the clock input end of the synchronous frequency divider, and the synchronous frequency divider outputs CLK _1HZ and CLK _2HZ signals.

The IHRC is prescaled (division factor 750) to reduce the frequency to 32kHz, which is the same order of magnitude as the ILRC, XTOSC frequencies. RTC _ CLK is obtained after RTCCKS [1:0] selection. RTC _ CLK is clock gated by RTCEN _ CEN to obtain RTC _ GCLK, which is provided to the synchronous frequency divider. The synchronous frequency divider determines a frequency division coefficient for dividing RTC _ GCLK according to the value of RTCCKS [1:0 ]. When XTOSC is selected, the division factor is set to 16384, resulting in a clock signal of CLK _2 HZ. When IHRC or ILRC is selected, the division factor is set to 16000, resulting in a CLK _2HZ clock signal. The CLK _1HZ signal is a divide-by-two of CLK _2 HZ.

The second counter is driven by the second clock CLK _1HZ to automatically increment by 1 every second counting of one second clock pulse. When the second counts to 59, the second count will return to 0 when the second clock pulse comes, and a carry will be generated to the minute counter. The second count is 0 to 59 cycles.

The effective counting range of the minute counter is 0-59 as that of the second counter. When the minute count reaches 59 and the second counter is again advanced to the minute counter, the minute counter is zeroed and the hour counter is incremented by 1.

The registers corresponding to the other counters carry and count according to the same principle, so that various functions of the module are realized.

The hour counter has two systems which can be selected, namely 12 hours system or 24 hours system. The system selection control bit N12_24 can be dynamically switched at any time without influencing the actual time value. Under the condition of 24 hours, the effective range of the hour counting value is 00-23. Under the 12-hour system, it is not enough to set the valid value to 1-12, and an identification bit needs to be added to indicate the morning or afternoon time.

The number of days per month varies and the number of days in february is divided by leap and non-leap years. The day counter module requires the cooperation of the leap year indication leap signal and the month signal. 1.

Months

3, 5, 7, 8, 10, 12, each month having 31 days; 4. months 6, 9, and 11, each month having 30 days; in month 2, 29 days are available in leap years, and only 28 days are available in non-leap years.

When the day count reaches the bottom of the month and when the hour counter is again advanced to the day counter, then the day count returns to 1 and will be advanced to the month count, which will be incremented by 1. Since the year is only 12 months, the month counter counts 1-12 cycles.

The years 2000-2099 are all fixed in the 21 st century, only the last two digits are reserved in the years, the effective range of a year counter is 00-99, and the total year is one hundred. Because the first two digits of a year are fixed to 20, the rule for leap year determination can be simplified as follows: if the last two digits of a year are multiples of 4, it is a leap year, otherwise it is not a leap year. leap is the leap year indicator: a leap of 1 indicates that the year is leap; a leap of 0 indicates that the year is not a leap year. The leap signal is used for the day counter module and the day counter module.

As shown in fig. 3, the week calculator automatically calculates a corresponding week value based on the year, month, day, and leap year indication signal leap signal. The result effective values of the day counter are 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, and 0x6, which respectively represent sunday, monday, tuesday, wednesday, thursday, friday, and saturday in this order. Because there are many calendars, there are also many ways to calculate the week. Different designs of the day counter circuit can be made depending on different algorithms. The corresponding algorithm can be completed using addition, subtraction, multiplication, division and remainder logic.

In order to reduce the resource cost of circuit implementation as much as possible, this embodiment provides a relatively simple and convenient week calculation formula, as follows:

week=([y/4]+y+mc+d)%7；

wherein week represents a week value, y represents the last two year numbers of 2000-2099, mc represents the modified transcoding of a month, d represents a day, [ y/4] represents that an integer value is obtained after dividing a year by 4, and% 7 represents that a remainder is obtained after 7 is calculated.

Month correction the production rules of transcoding mc: when the year is leap year, the corrected transcoding values of 1-12 months are 5, 1, 2, 5, 0, 3, 5, 1, 4, 6, 2 and 4 respectively; and when the year is a non-leap year, the corrected transcoding values of 1-12 months are 6, 2, 5, 0, 3, 5, 1, 4, 6, 2 and 4 respectively.

Because the formula needs a small number of operations and a small amount of calculation compared with the existing well-known week algorithm formula (such as a Gimeralson calculation formula and a Zeller formula), the circuit can be designed according to the formula, and accordingly, the number of gates can be effectively reduced. The week counter actually implements a circuit scale of about a hundred gates.

The signals required for calculating the week value include a year signal, a leap year indication leap signal, a month signal, and a day signal. Year signal in the range of 00-99. Month signal, range is 01~ 12.

Leap year determination is performed on the year in the year counter module, and a leap year indication leap signal is given according to the year value. If the leap year is the leap year, the leap outputs 1; if not, leap outputs 0.

Leap year judgment rule: because the first two digits of a year are fixed to 20, the rule for leap year determination can be simplified as follows: if the last two digits of the year are multiples of 4, the year is leap year, otherwise the year is not leap year.

The data in the digital circuit is operated on in a binary rule. And the code values of year, month and day are expressed in BCD code. Operating on a value represented by a BCD code according to a binary rule may result in erroneous results. So the BCD code value needs to be converted: the BCD code value of the year or day is converted into a natural binary code value. The tens of the year/day BCD code is multiplied by 10 plus the ones of its BCD code, and the resulting sum is stored as a natural binary number in the circuit. In order to save implementation resources, the multiplication by 10 operation may be replaced by performing left shift by 1 bit and left shift by 3 bits on the ten bits of the BCD code to implement the functions of multiplication by 2 and multiplication by 8, and then adding the two to obtain the result of multiplication by 10.

[ y/4] corresponds to the operation of dividing the year by 4 and rounding the result. To save implementation resources, division can be implemented by logically right-shifting the dividend by two bits.

And the month correction decoding mc outputs a corresponding code value for different months respectively according to the month and leap year indication. The output is decoded by using combinational logic.

And (4) summing calculation of [ y/4] + y + mc + d can be realized by using an adder.

The remainder operation of 7 is to perform modulo 7 processing on the summation calculation value, and the result is the remainder obtained by dividing the summation value by 7.

As shown in fig. 4, in this embodiment, the week calculator includes a code value conversion module, a division 4 operation module, a month correction decoding module, a summation calculation module, and a remainder-to-7 module, and implements calculation of a week value within 2000-2099 hundred years, and the week calculator performs operation on an input year value year, month value month, and day value day in combination with an input leap year indication leap signal, and outputs a week value week corresponding to the day. The month correction decoding module inputs the month value month and the leap year indication signal leap output by the leap year judging module, and respectively outputs a corresponding correction decoding value to different months according to the month and leap year marks. The code value conversion module is used for converting BCD code values of the year value year and the day value day input into natural binary code values. And the 4-division operation module performs 4-division operation on the year value converted by the code value conversion module, the result is an integer, only a quotient value is taken as the result, and the remainder is discarded. The summation calculation module sums the year value year converted by the code value conversion module, the day value day converted by the code value conversion module, the corrected decoding value output by the month correction decoding module, and the year division 4 rounding result output by the division 4 operation module. And the 7-complementation module is used for dividing the value output by the summation calculation module by 7 to carry out complementation processing, and the remainder is the output week value week corresponding to the day.

As shown in fig. 5, the leap year determination module is a leap year determination logic circuit, the input of the leap year determination module inputs the year value year, and the leap year determination module outputs a one-bit indication signal: leap year indication signal leap, if leap year, leap outputs 1, if not, leap outputs 0. Because the first two digits of a year are fixed to 20, the rule for leap year determination can be simplified as follows: if the last two digits of a year are multiples of 4, it is a leap year, otherwise it is not a leap year. The second two digits of the year of the input year value of the leap year judgment module are taken, converted into 8-digit BCD codes which are expressed as year [7:0], and logical operation is carried out on three-digit signals of year [4], year [1] and year [0] in the year [7:0] through a logic circuit: year [4] & lt | year [1] & lt | year [0] or year [4] | year [1] | year [0], when the result of the logical expression year [4] & lt year [1] & lt | year [0] is true, or when the result of the logical expression year [4] | year [1] | year [0] is false, the year is a leap year, otherwise not a leap year.

As shown in fig. 6, the code value conversion module is a BCD-to-binary converter, and the code value conversion module is configured to convert BCD code values of year/day into natural binary code values. The code value conversion module multiplies the upper 4 bits of the BCD code value of year/day by 10 and adds the lower 4 bits of the BCD code thereof, and the sum is stored as a natural binary number in the circuit. In order to save implementation resources, in this embodiment, the multiplication by 10 operation is replaced by performing left shift by 1 bit and 3 bits on the high 4 bits of the BCD code to implement the multiplication by 2 and the multiplication by 8, respectively, and then adding the two to obtain the result of the multiplication by 10.

As shown in fig. 7, the code value conversion module includes a first adder and a second adder, a value obtained by shifting the upper 4 bits of the BCD code value of the year/day value day by one bit to the left and a value obtained by shifting the upper 4 bits of the BCD code value of the year/day value day by three bits to the left are used as the input of the first adder, the lower 4 bits of the BCD code value of the year/day value day and the output value of the first adder are used as the input of the second adder, and the second adder outputs the converted natural binary code value. Operand 1: the decadic code _ in [7:4] of the BCD code is shifted to the left by 3 bits to realize the function of multiplying by 8; operand 2: the decadic code _ in [7:4] of the BCD code is shifted by 1 bit to the left, so that the function of multiplying 2 is realized; operand 3: the bits code _ in [3:0] of the BCD code; the three operands are added to obtain the converted code value output value code _ out [6:0 ]. The core of the circuit is two adders. The adder may be selected from DW01_ add adder modules in the Synopsys, DesignWareIP library, with configurable bit widths for the input A, B and output SUM. Here they are each configured to be 7 bits wide. The converted signal code _ in [6:0] is an input signal, and the converted signal code _ out [6:0] is an output signal. The circuit connection relation is as follows: carry input port CI of adder ADDR1 is connected to logic 0, i.e., ground; the input ports A [6:3] of the adder ADDR1 are connected to code _ in [7:4], A [2:0] are all connected to logic 0, i.e., ground; input ports B [4:1] of adder ADDR1 are connected to code _ in [7:4], B [6], B [5], B [0] are all connected to logic 0, i.e., ground; carry input port CI of adder ADDR2 is connected to carry output port CO of adder ADDR 1; the input port A [6:0] of the adder ADDR2 is connected to the SUM output end of the adder ADDR 1; carry output port CO of adder ADDR2 is not used in the air; the SUM output SUM of the adder ADDR2 is the output code _ out [6:0] of the code value conversion module.

And the 4-division operation module performs 4-division operation on the year value converted by the code value conversion module, the result is an integer, only a quotient value is taken as the result, and the remainder is discarded. In order to save implementation resources, the division by the divide-by-4 operation module in this embodiment is implemented by shifting the dividend by two bits to the right logically. The division function is realized by using a logic right shift mode, is the most basic digital operation in the field of digital design, and belongs to the known technology.

The month correction decoding module is a BCD code correction circuit and comprises two input ends, wherein one input end inputs a month value month, the other input end inputs a leap year indication signal leap value output by the leap year judgment module, the month correction decoding module respectively outputs a corresponding code value to different months according to month and leap year indications, when the year is a leap year, the correction decoding values of 1-12 months are respectively 5, 1, 2, 5, 0, 3, 5, 1, 4, 6, 2 and 4, and when the year is a non-leap year, the correction decoding values of 1-12 months are respectively 6, 2, 5, 0, 3, 5, 1, 4, 6, 2 and 4.

The month correction decoding module inputs leap year indication signal leap and month value month 4:0, and outputs mc 2:0 signal. The logical implementation of mc can be handled according to table 2.

Table 2 month correction decoding truth table:

leap	month[4]	month[3]	month[2]	month[1]	month[0]	mc[2]	mc[1]	mc[0]
									0	0	0	0	0	1	1	1	0
0	0	0	0	1	0	0	1	0
									0	0	0	0	1	1	0	1	0
0	0	0	1	0	0	1	0	1
									0	0	0	1	0	1	0	0	0
0	0	0	1	1	0	0	1	1
									0	0	0	1	1	1	1	0	1
0	0	1	0	0	0	0	0	1
									0	0	1	0	0	1	1	0	0
0	1	0	0	0	0	1	1	0
									0	1	0	0	0	1	0	1	0
0	1	0	0	1	0	1	0	0
									1	0	0	0	0	1	1	0	1
1	0	0	0	1	0	0	0	1
									1	0	0	0	1	1	0	1	0
1	0	0	1	0	0	1	0	1
									1	0	0	1	0	1	0	0	0
1	0	0	1	1	0	0	1	1
									1	0	0	1	1	1	1	0	1
1	0	1	0	0	0	0	0	1
									1	0	1	0	0	1	1	0	0
1	1	0	0	0	0	1	1	0
									1	1	0	0	0	1	0	1	0
1	1	0	0	1	0	1	0	0

as shown in FIG. 8, the present embodiment provides a month correction decoding logic that can be implemented. Wherein sel [5:0] is used as strobe control signal, sel [5] is connected with leap input signal, and sel [4:0] is connected with month [4:0] input signal. All combination cases for sel [5:0] can be divided into 7 groups: strobe control group 0-strobe control group 6. The selected signals have 7 groups, represented in binary: 000. 001, 010, 011, 100, 101, 110, which are all elements of the month correction value. The set of gating control group 1 is {0x08, 0x22, 0x28 }; the set of gating control groups 2 is {0x02, 0x03, 0x11, 0x23, 0x31 }; the set of gating control groups 3 is {0x06, 0x26 }; the set of gating control groups 4 is {0x09, 0x12, 0x29, 0x32 }; the set of gating control groups 5 is {0x04, 0x07, 0x21, 0x24, 0x27 }; the set of gating control groups 6 is {0x01, 0x10, 0x30 }; the set of gated control groups 0 is {0x05, 0x25, other values }; when the strobe signal sel [5:0] value, composed of leap and month [4:0], falls within a strobe control group, the corresponding selected input signal is output to the mc port as the corrected value for the corresponding month. For example, leap =1, month [4:0] is 0x11, sel [5:0] is 0x31, sel value falls into strobe control group 2, and the corresponding input signal 010 is selected and output to mc, i.e., the month correction for leap year 11 month is 2.

The summation calculation module sums the year value year converted by the code value conversion module, the day value day converted by the code value conversion module, the corrected decoding value output by the month correction decoding module, and the year division 4 rounding result output by the division 4 operation module to obtain sum [7:0 ]. The summation calculation module is implemented using an adder, and the summation calculation module can call the DW01_ add adder IP module in the Synopsys' DesignWare IP library.

And the 7-complementation module is used for dividing the value output by the summation calculation module by 7 to carry out complementation processing, and the remainder is the output week value week corresponding to the day.

As shown in fig. 9, the DW _ div divider IP block in the Synopsys' design ware IP library may be called by the pair 7 complementation block, and the bit widths of the inputs a and b may be configured. Here, a is configured to be 8-bit wide and b is configured to be 3-bit wide. a is connected to the output sum [7:0] of the summation calculation module, b is fixed to a constant 7. The remainder output port output value of DW _ div IP is the modulo 7 result value.

The implementation steps of the week calculator are as follows:

1. firstly, inputting set year, month and day signal values and leap year indication leap values, wherein the BCD codes are used for the year, month and day;

2. the hardware circuit automatically calculates and gives the week value, the result is also the BCD code.

The required time from the setting of the year, month and lap signal values to the setting of the week value depends on the specific circuit technology. The automatic calculation circuit for the hundred-year week can be realized by completely using combinational logic, so that the corresponding week value can be calculated in real time according to the values of the year, month and day. Meanwhile, the condition that the corresponding weeks of the year, month and day are inconsistent can be avoided. The automatic week calculation circuit implemented according to fig. 1 and 4 performs week calculation for each of the one hundred years from 2000 to 2099, and the week value for each day is verified to be correct by logic simulation.

For example, to know the week value corresponding to 28 days 9 and 28 in 2017, the input signals year, month and day are set to 0x17, 0x09 and 0x28, respectively, the input signal leap is set to 0, and the result week obtained by the operation of the week automatic calculation circuit is 0x04, which indicates that the day is thursday.

For example, if it is desired to know the day of week corresponding to

day

15, 4 and 2036, year, month and day, the input signals year, month and day are set to 0x36, 0x04 and 0x15, respectively, the input signal leap is set to 1, and the result week obtained by the operation of the automatic day calculation circuit is 0x02, indicating that the day is tuesday.

For example, to know the week value corresponding to 12/7/2059, the input signals year, month, and day are set to 0x59, 0x12, and 0x07, respectively, the input signal leap is set to 0, and the result week obtained by the operation of the week automatic calculation circuit is 0x00, indicating that the day is sunday.

The week calculation circuit can be realized by completely using combinational logic, so that the corresponding week value can be calculated in real time according to the year, month and day values. Meanwhile, the condition that the corresponding weeks of the year, the month and the day are inconsistent can be avoided.

The alarm clock generator realizes the function of an alarm clock. And setting the control bit TAEN in the control register to be 1, and starting the alarm clock function.

As shown in fig. 10, in this embodiment, the alarm clock generator inputs a day count value, a week count value, an hour count value, a minute count value, and a second count value, and inputs an alarm clock day value, an alarm clock week value, an alarm clock hour value, an alarm clock minute value, and an alarm clock second value according to the alarm clock, the alarm clock generator includes a first selector, a second selector, a first comparator, a second comparator, a third comparator, a fourth comparator, a first or second or third or nand gate, or fourth and first and second, the first selector inputs the alarm clock day value and the alarm clock week value, the second selector inputs the day count value and the week count value, the first selector and the second selector input a WDSEL control bit of 0 or 1 to select a comparison day or week, the fourth selector inputs the alarm clock value, the day count value or the alarm clock week count value output by the second selector, the third comparator inputs the small alarm clock hour value, the minute value, the second selector input a second selector output a WDSEL control bit of 0 or 1 to select a comparison day or week count value, and the first selector output a second selector input a second selector output a second selector and a second input a second, An hour counting value, a second comparator inputs an alarm clock minute value and a minute counting value, a first comparator inputs an alarm clock second value and a second counting value, if the alarm clock alarm time is consistent with the current time, the comparator outputs an alarm mark FLAG, the alarm clock generator comprises a day/week alarm register, a time alarm register, a minute alarm register, a second alarm register, a day/week alarm register, a time alarm register, a minute alarm register and a second alarm register respectively provide signals of a shielding control bit MSK4, MSK3, MSK2 and MSK1, signals of an alarm mark FLAG1 and a shielding control bit MSK1 output by the first input comparator, signals of an alarm mark FLAG2 and a shielding control bit MSK2 output by the second input comparator, signals of an alarm mark FLAG3 and a shielding control bit MSK3 output by the third input comparator, or signals of an alarm mark FLAG4 and a shielding control bit MSK4 output by the fourth input comparator, the first NAND gate inputs shielding control bits MSK1, MSK2, MSK3 and MSK4 signals, the shielding control bits MSK4, MSK3, MSK2 and MSK1 are alarm shielding control bits of day/week, time, minute and second respectively, corresponding fields are shielded when the number of the fields is 1, the first AND gate inputs the output of the first OR gate, the second OR gate, the third OR gate, the fourth OR gate, the first NAND gate, an enable bit RTCEN signal and a control bit TAEN signal, and the first AND gate outputs an alarm clock flag TAIF signal.

Through reading and writing the access interface control circuit, can set for the relevant register of alarm clock: day/week, hour, minute, second alarm registers. The comparison day or week may be selected by the WDSEL control bit in the alarm clock register. If the WDSEL control bit is 1, the comparison is performed according to the use day, and if the WDSEL control bit is 0, the comparison is performed according to the use week.

The core of the alarm clock generator is a numerical comparison circuit. When the alarm time of the alarm clock is consistent with the current time, the alarm flag bit TAIF in the status register RTC _ SR will be set. An alarm interrupt may also be generated if an alarm interrupt alarm enable TAIE is turned on.

A register bit a12_24 is set in the control register RTC _ CR. If the bit is 0, the time format set by the alarm clock is 12 hours; if the bit is 1, the time format of the alarm clock setting is 24 hours. If the register bit A12_24 is 0, the set hour alarm clock alarm register value is compared with the hour register under the 12-hour system; otherwise, the time is compared with an hour register under the 24-hour system, so that the matching problem between the current time-hour system and the alarm clock-hour system is solved.

The alarm clock alarm function is programmable and the alarm setting can be triggered by any calendar field of day/week, hour, minute, and second. The alarm clock alarm function can select day/week, time, minute and second for matching and respectively provides a shielding function. When a field is masked (the corresponding MSK control bit is 1), the value is an irrelevant item and does not participate in the comparison of the corresponding calendar field. When all mask settings are on, the alarm clock alarm flag signal TAIF will no longer be generated.

The HOUR register HOUR is arranged with 6 bits. When the hour system selects 12, the highest bit representation is the AM (morning)/PM (afternoon) indicator bit, "0" for AM in the morning and "1" for PM in the afternoon. Time control for 12 hours and 24 hours is shown in Table 3.

TABLE 324 hours system and 12 hours system time comparison table

HOUR register value for 24 HOURs system (hexadecimal)	HOUR register value for 12 HOURs system (hexadecimal system)
		00	12(AM12)
01	01(AM01)
		02	02(AM02)
03	03(AM03)
		04	04(AM04)
05	05(AM05)
		06	06(AM06)
07	07(AM07)
		08	08(AM08)
09	09(AM09)
		10	10(AM10)
11	11(AM11)
		12	32(PM12)
13	21(PM01)
		14	22(PM02)
15	23(PM03)
		16	24(PM04)
17	25(PM05)
		18	26(PM06)
19	27(PM07)
		20	28(PM08)
21	29(PM09)
		22	30(PM10)
23	31(PM11)

The alarm clock alarm function can select day/week, time, minute and second for matching and respectively provides a shielding function. A mask control bit MSK is provided in each alarm register. MSK high is active, i.e. MSK is 1, the alarm value is irrelevant and the calendar field does not trigger an alarm. The four signals MSK1, MSK2, MSK3, MSK4 provide a masking function for the four calendar fields of second, minute, hour, day/week, respectively. When all mask settings are on, the alarm clock alarm flag signal TAIF will no longer be generated. In addition, the premise of generating the alarm clock alarm mark signal is that the module in the control register enables the RTCEN to be started, and the alarm clock function enabling bit TAEN is also started.

As shown in fig. 11, the real-time clock unit circuit capable of automatically calculating a week value further includes a real-time clock interrupt circuit, the real-time clock interrupt circuit includes a third selector, a second and gate, a third and gate, a fifth or gate, a second/half-second interrupt enable register RTCIE, a second/half-second interrupt flag register RTCIF, an alarm clock interrupt enable register TAIE, an alarm clock interrupt flag register TAIF, the control register RTC _ CR includes an enable bit RTCEN and an RTCINTS bit for generating a selection control signal of the RTCIF flag bit, the second clock generator further provides a half-second signal CLK _2HZ, the status register RTC _ SR includes an RTCIF flag bit, the three selectors input CLK _1HZ and CLK _2HZ, the selection control signal RTCINTS is connected to a selection control input terminal of the third selector, the alarm clock interrupt flag TAIF output by the alarm clock generator registers to the alarm interrupt flag register TAIF, the output end of the alarm clock interrupt flag register TAIF and the output end of the alarm clock interrupt enable register TAIE are connected with the input end of the AND gate III, the output end of the AND gate II and the output end of the AND gate III are connected with the input end of the OR gate V, and the output end of the OR gate V outputs an RTC interrupt signal rtcint.

The real-time clock unit circuit provides second interruption and half second interruption, and alternative configuration can be performed according to application requirements. And meanwhile, a programmable alarm clock alarm interruption function is also provided, and alarm setting can be triggered by any calendar field in day/week, time, minute and second. These interrupts may be used by the MCU/SoC to manage the low power mode. Such as waking once every second or when the alarm time of the alarm clock has expired. If the time is considered too long after waking up once every second, half-second interruption can be set and selected to accelerate the response speed.

The second/half second interrupt and the alarm clock interrupt share one rtcint interrupt channel.

As shown in fig. 12, in an embodiment, the rtc unit circuit is hung on the APB bus, which is a scenario of the rtc functional module on the MCU or SoC chip. rtcint interrupt is provided for the NVIC interrupt controller, and when the interrupt occurs, the CPU can be awakened, so that the aim of low-power management control is fulfilled.

The system clock SYSCLK on the APB bus and the operating clock RTC _ CLK of the unit circuit may be from different clock signal sources. When directly reading the values of year, month, day, week, hour, minute and second through the APB interface without synchronization processing, the data sampling may have a metastable state. In order to avoid the phenomenon of reading error data, the reading action is added into a synchronous circuit for processing, and the synchronous circuit comprises an APB synchronous reading register.

As shown in fig. 13, the APB synchronous read register includes a latch controller, and a year latch, a month latch, a day latch, a week latch, an hour latch, a minute latch, and a second latch connected to the latch controller, wherein a working clock of the latch controller is a system clock SYSCLK on the APB bus, and the year latch, the month latch, the day latch, the week latch, the hour latch, the minute latch, and the second latch are respectively connected to a year counter, a month counter, a day counter, a week counter, an hour counter, a minute counter, and a second counter. The working clock of the synchronous circuit is a system clock SYSCLK on the APB bus.

The latch controller is essentially a positive pulse detection circuit. The synchronous trigger signal for reading the register value is a rising edge detection pulse of a half second signal.

As shown in FIG. 14, in the latch controller circuit, the first two DFFs are responsible for synchronizing the incoming signal (using the half-second signal CLK _2 HZ) to the system clock domain of the APB. Then, a DFF and a two-input AND gate are combined to form a positive transition detection pulse of the input signal, wherein the width of the positive transition detection pulse is one system clock period.

For the write operation of the register, in order to minimize the occupation of the logic resource, an asynchronous data write mode may be adopted. And writing the initial values into the registers of year, month, day, hour, minute and second by an APB interface in an asynchronous writing mode. When the register data is initialized, the module work enable bit RTCEN is forbidden first, and when the initial value of the date time register is set, because the unit circuit does not have a work clock, the phenomenon of write failure caused by metastable state can not occur. When the values of other registers are set, the RTCEN enable bit is turned on, and the unit circuit starts to work normally.

In another embodiment, as shown in fig. 15, the rtc unit circuit is hooked up to the I2C/SPI bus or UART communication port, which corresponds to the scenario of a chip dedicated to the rtc.

When only the external crystal oscillator XTOSC (32768Hz) clock is provided, the clock source selection related logic may be fixed to select XTOSC, or the clock source selection logic may be deleted. All registers of the real time clock are accessed through the I2C/SPI/UART communication port. The read-write access interface controls the logic circuit to carry out read-write operation, and the communication protocol can stipulate that one register can be accessed each time, and a plurality of registers can be accessed continuously at one time.

The logic block diagrams of the I2C, SPI, UART communication interface control circuit are shown in fig. 16, 17, and 18, respectively. The function is to analyze the communication frame, perform corresponding read-write operation on the register in the register set, complete the actions of receiving data and sending data, and realize the function of bidirectional communication. Through these communication interfaces, an external system bus or a communication host can access all registers in the unit circuit.

The real-time clock unit circuit comprises the following implementation steps:

1. the external host computer interacts with the read-write access interface control logic circuit through a system bus or a communication interface, and firstly writes correct initial values into the year, month, day, hour, minute and second registers and the hour system selection control bit N12_24 in the unit circuit.

2. If the second interrupt or half second interrupt function is needed, the interrupt source selection control bit RTCINTS is set and the second/half second interrupt enable control bit RTCIE is opened through the read-write access interface control logic circuit.

3. If the alarm clock needs to be set, the alarm clock alarming time is set through the read-write access interface control logic circuit, and the alarm clock enabling control position TAEN is started. If the alarm clock interruption needs to be provided, an alarm clock interruption enabling control bit TAIE needs to be started. The calendar fields (day/week, time, minute and second) are all provided with corresponding shielding control MSK bits, and whether to shield a certain calendar field can be determined according to requirements.

4. The control register is set through the read-write access interface control logic circuit, the working clock source of the real-time clock circuit module is selected, and the module working enabling control bit RTCEN is started.

5. The read-write access interface control logic circuit is used for reading the register to obtain the register values of year, month, day, week, hour, minute and second.

6. The read-write access interface control logic circuit is used for reading the register, and reading the values of RTCIF and TAIF interrupt flag bits in the state register, so that whether second/half second interrupt or alarm clock alarm interrupt occurs can be known. If the second/half-second interrupt enable or the alarm clock alarm interrupt enable is turned on, the interrupt signal rtcint can trigger the MCU or the SoC to transfer to the interrupt processing, such as reading a calendar time value or processing other interrupt tasks needing timing processing. The RTCIF and TAIF interrupt flag bits can be cleared by performing a write operation on the read/write access interface control logic circuit (for the clearing action of the two interrupt flag bits, the clearing action may be defined in advance as write 1 clearing, or may be defined in advance as write 0 clearing).

7.

Step

5 or 6 can be repeatedly executed;

8. when the real-time clock circuit is to be closed, the read-write access interface control logic circuit executes write operation on the control register, and the module work enable bit RTCEN is set to be 0. At this time, the alarm clock function is also turned off regardless of whether TAEN is on enabled.

The focus of the real time clock unit is the week counter. Week calculation is carried out on every day in the hundred years of 2000-2099, and the week value of every day is correct through logic simulation verification. The input signals year, month, day, and leap of the day calculator, and the output signal week. Several samples were taken and the timing waveform between input and output is shown in figure 19. Meanings represented in the waveform diagrams: 9 months and 28 days in 17 years (next year), thursday; 36 years (leap years) 4 months and 15 days, tuesday; 12 months and 7 days in 59 years (next year), sunday; year 92 (leap year) 3 month 31 day, monday.

Other embodiments of the present invention than the preferred embodiments described above will be apparent to those skilled in the art from the present invention, and various changes and modifications can be made therein without departing from the spirit of the present invention as defined in the appended claims.

Claims

1. A real-time clock unit circuit capable of automatically calculating a week value is characterized by comprising a second clock generator, a second counter, a minute counter, an hour counter, a day counter, a month counter, a year counter and a week counter;

2. The circuit of claim 1, further comprising an alarm clock generator for inputting a day count value, a week count value, an hour count value, a minute count value, a second count value, and an alarm clock day value, an alarm clock week value, an alarm clock hour value, an alarm clock minute value, and an alarm clock second value, wherein the alarm clock generator comprises a first selector, a second selector, a first comparator, a second comparator, a third comparator, a fourth comparator, a first gate, a second gate, a third gate, a first gate, a second gate, a nand gate, a fourth gate, and a first gate, the first selector inputs the day count value and the week count value, the second selector inputs the day count value and the week count value, and the first selector and the second selector inputs a WDSEL control bit of 0 or 1 to select a comparison day or week, the fourth comparator inputs the alarm clock day value and day count value or the alarm clock week value and week count value output by the first and second selectors, the third comparator inputs the alarm clock hour value and hour count value, the second comparator inputs the alarm clock minute value and minute count value, the first comparator inputs the alarm clock second value and second count value, if the alarm clock alarm time is consistent with the current time, the comparator outputs an alarm FLAG, the alarm clock generator comprises a day/week alarm register, a time alarm register, a minute alarm register and a second alarm register, the day/week alarm register, the time alarm register, the minute alarm register and the second alarm register respectively provide a shielding control bit MSK4, MSK3, MSK2 and MSK1, or the alarm FLAG FLAG1 and shielding control bit MSK1 signals output by the first comparator input by the first gate, or the alarm FLAG FLAG2 and shielding control bit MSK2 signals output by the second comparator input by the second gate, the alarm FLAG3 and the mask control bit MSK3 signals output by the OR gate three-input comparator three, the alarm FLAG4 and the mask control bit MSK4 signals output by the OR gate four-input comparator four, the alarm mask control bits MSK1, MSK2, MSK3 and MSK4 signals are input by the NAND gate one, the mask control bits MSK4, MSK3, MSK2 and MSK1 are respectively the alarm mask control bits of day/week, hour, minute and second, the corresponding field is masked when 1, the output of the AND gate one, the OR gate two, the OR gate three, the OR gate four and the NAND gate one, the RTCEN signal and the control bit TAEN signal are input by the AND gate one, and the alarm clock alarm FLAG TAIF signal is output by the AND gate one.

3. The circuit of claim 2, further comprising a read/write access control circuit including a register read/write access bus, a control register RTC _ CR and a status register RTC _ SR, wherein the second, minute, hour, day, month, year, and week counters respectively include a second, minute, hour, day, month, year, and week registers, and the register access bus respectively communicates with the second, minute, hour, day, month, year, week, day/week, alarm, time alarm, minute, and alarm registers, The alarm clock comprises a second alarm register, a control register RTC _ CR and a state register RTC _ SR, wherein the control register RTC _ CR comprises a control bit TAEN and an enabling bit RTCEN, the control bit TAEN and the enabling bit RTCEN are connected with the alarm clock generator, the state register RTC _ SR comprises an alarm flag bit TAIF, and the alarm flag bit TAIF is connected with the alarm clock generator.

4. A real time clock unit circuit capable of automatically calculating a week value as claimed in claim 3, wherein said control register RTC _ CR comprises register bits a12_24, said register bits a12_24 being connected to said time alarm register, said control register RTC _ CR comprises register bits N12_24, said register bits N12_24 being connected to an hour counter.

5. The real time clock unit circuit capable of automatically calculating a week value according to claim 3, wherein the real time clock unit circuit capable of automatically calculating a week value further comprises a real time clock interrupt circuit, the real time clock interrupt circuit comprises a selector three, an AND gate two, an AND gate three, an OR gate five, a second/half second interrupt enable register RTCIE, a second/half second interrupt flag register RTCIF, an alarm clock interrupt enable register TAIE, an alarm clock interrupt flag register TAIF, the control register CR comprises an enable bit RTRTCEN and an RTCINTS bit for generating a selection control signal of the RTCIF flag bit, the second clock generator further provides a half second signal CLK _2HZ, the status register RTCSR comprises the RTCIF flag bit RTCIF, the selector three inputs CLK _1HZ and CLK _2HZ, the selection control signal RTCINTS is connected to a selection control input terminal of the selector three, an alarm clock alarm mark TAIF signal output by the alarm clock generator is registered to an alarm clock alarm interruption mark register TAIF, an RTCIF mark bit of the state register RTC _ SR is connected with a second/half-second interruption mark register RTCIF, an output end of the selector III is connected with an input end of the second/half-second interruption mark register RTCIF, an output end of the second/half-second interruption mark register RTCIF and an output end of the second/half-second interruption enable register RTCEE are connected with an input end of the AND gate II, an output end of the alarm clock interruption mark register TAIF and an output end of the alarm clock interruption enable register TAIE are connected with an input end of the AND gate III, an output end of the AND gate II and an output end of the AND gate III are connected with an input end of the OR gate V, and an output end of the OR gate V outputs the RTC interruption signal rtcint.

6. The real time clock unit circuit capable of automatically calculating week values according to claim 5, wherein the second clock generator comprises an on-chip high frequency RC clock IHRC connected to the input terminal of the selector four after being connected to the prescaler, an on-chip low frequency RC clock ILRC connected to the input terminal of the selector four, an external crystal oscillator clock XTOSC connected to the input terminal of the selector four, a prescaler, a selector four, an AND gate four, and a synchronous divider, the control register CR comprises RTCCCKS [1:0] register bits, RTCCCKS [1:0] register bits are connected to the control input terminals of the selector four and the synchronous divider, the RTCCLK _ CLK signal output by the selector four, the enable bit of the control register RTC _ CR are connected to the input terminal of the AND gate four, the RTCLK _ GCLK signal output by the AND gate four is connected to the clock input terminal of the synchronous divider, the synchronous frequency divider outputs CLK _1HZ and CLK _2HZ signals.

7. The rtc unit circuit capable of automatically calculating week values according to any one of claims 3-6, wherein the rtc unit circuit capable of automatically calculating week values comprises an APB bus, and the second clock generator, the second counter, the minute counter, the hour counter, the day counter, the month counter, the year counter and the week counter are all connected to the APB bus, the APB bus comprises an APB synchronous read register, the APB synchronous read register comprises a latch controller and a year latch, a month latch, a day latch, a week latch, an hour latch, a minute latch and a second latch connected to the latch controller, the clock of the latch controller is a system clock SYSCLK on the APB bus, and the year latch, the month latch, the day latch, the week latch, the hour latch, The minute latch and the second latch are respectively connected with a year counter, a month counter, a day counter, a week counter, an hour counter, a minute counter and a second counter.

8. A real time clock unit circuit capable of automatically calculating week values as claimed in any one of claims 3-6, wherein said real time clock unit circuit capable of automatically calculating week values comprises an I2C/SPI bus or UART communication port, all registers of the real time clock unit circuit are accessed through an I2C/SPI/UART communication port.