CN114815425A - Display panel and manufacturing method thereof - Google Patents
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- CN114815425A CN114815425A CN202210492748.2A CN202210492748A CN114815425A CN 114815425 A CN114815425 A CN 114815425A CN 202210492748 A CN202210492748 A CN 202210492748A CN 114815425 A CN114815425 A CN 114815425A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000008439 repair process Effects 0.000 claims abstract description 17
- 230000002093 peripheral effect Effects 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 16
- 230000002159 abnormal effect Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 230000008054 signal transmission Effects 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 239000010409 thin film Substances 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000003705 background correction Methods 0.000 description 2
- 239000003550 marker Substances 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a display panel and a manufacturing method thereof. The display panel comprises a plurality of pixel functional areas, and each pixel functional area comprises a first sub-pixel area and a second sub-pixel area which are adjacent; the display panel also comprises a first conducting layer and a second conducting layer; the first conducting layer comprises a first common signal part which is positioned in the pixel functional area and at least arranged on the peripheral side of the first sub-pixel area; the second conducting layer is arranged on one side of the first conducting layer and comprises a first drain electrode and a second drain electrode which are arranged in each pixel functional area, the distance from the first drain electrode to the first sub-pixel area is smaller than the distance from the first drain electrode to the second sub-pixel area, and the distance from the second drain electrode to the first sub-pixel area is smaller than the distance from the second drain electrode to the second sub-pixel area; wherein, the first common signal part is provided with a mark structure near each first drain. The invention can improve the success rate and the repair efficiency of the dark spot repair of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a manufacturing method thereof.
Background
Thin Film Transistor Liquid Crystal displays (TFT-LCDs) are widely used in the fields of televisions, mobile phones, computers, and the like, and become the mainstream of flat panel displays, due to their advantages of large size, high integration, powerful functions, flexible process, low cost, and the like. A Liquid Crystal display panel, referred to as a Liquid Crystal panel for short, is a main component of a TFT-LCD, and generally comprises a color filter Substrate (CF), a Thin Film Transistor Array Substrate (TFT Array Substrate), and a Liquid Crystal Layer (Liquid Crystal Layer) filled between the two substrates.
In the production process of the array substrate, under the influence of the production process and the external environment, some metal debris or foreign matters and other residues exist in the thin film transistor, so that pixels driven by the thin film transistor become bright spots during display, and further, the image display of the display panel is abnormal. Therefore, it is usually necessary to perform shading repair on the pixels with abnormal display to improve the display quality of the display panel. At present, the method for repairing the array substrate by dark spots is as follows: and cutting off the signal input of the thin film transistor corresponding to the abnormal display pixel by adopting a laser process, so that the liquid crystal corresponding to the abnormal display pixel cannot deflect, and further realizing the dark spot.
Referring to fig. 1 and 2, in a display with a Data Line Sharing (DLS) architecture, two adjacent sub-pixels P1 and P2 respectively input signals through transistors T1 and T2, transistors T1 and T2 share a Data Line D and are respectively connected to two different scan lines G, the transistor T1 is connected to the sub-pixel P1 through a short connector a, and the transistor T2 is connected to the sub-pixel P2 through a long connector b; when the subpixel P1 or P2 is abnormal and needs to perform shading correction on the subpixel P1 or P2, under a backlight, the observed structure diagram is as shown in fig. 2, wherein the structure diagram includes a drain T11 connected to the transistor T1 and a drain T21 connected to the transistor T2, and a pixel electrode connected to the drain is made of a transparent material (for example, ITO), so that the structure diagram cannot be observed, and further, it cannot be determined in the observed fig. 2 which subpixel the drain T11 and the drain T21 are respectively connected to, and further, the shading correction on the subpixel P1 or P2 cannot be accurately and effectively performed.
Disclosure of Invention
The embodiment of the invention provides a display panel and a manufacturing method thereof, which can improve the repair success rate and repair efficiency.
The embodiment of the invention provides a display panel, which comprises a plurality of pixel functional areas, wherein each pixel functional area comprises a first sub-pixel area and a second sub-pixel area which are adjacent;
the display panel further includes:
a substrate;
a first conductive layer; the first common signal part is arranged on one side of the substrate and comprises a first common signal part which is positioned in the pixel functional area and is at least arranged on the peripheral side of the first sub-pixel area;
the second conducting layer is arranged on one side, far away from the substrate, of the first conducting layer and comprises a first drain electrode and a second drain electrode which are arranged in each pixel functional area, the distance from the first drain electrode to the first sub-pixel area is smaller than the distance from the first drain electrode to the second sub-pixel area, and the distance from the second drain electrode to the first sub-pixel area is smaller than the distance from the second drain electrode to the second sub-pixel area;
the pixel electrode layer is arranged on one side, far away from the first conducting layer, of the second conducting layer and comprises a first pixel electrode arranged in the first sub-pixel area and a second pixel electrode arranged in the second sub-pixel area;
the first drain is electrically connected with the first pixel electrode, the second drain is electrically connected with the second pixel electrode, and the first common signal part is provided with a mark structure close to each first drain.
In an embodiment of the invention, the plurality of pixel functional regions are arranged in an array along a first direction and a second direction, and the first direction is different from the second direction, and in each pixel functional region, a first sub-pixel region and a second sub-pixel region are adjacently arranged along the first direction;
and in each pixel function region, the first drain and the second drain are respectively positioned at two opposite sides of the first sub-pixel region, and the mark structure is arranged at one side of the first common signal part close to the first drain along the second direction.
In an embodiment of the invention, in each of the pixel function regions, the first common signal part is disposed around the first sub-pixel region and the second sub-pixel region, and includes a first sub-part located between the first sub-pixel region and the second sub-pixel region, and the mark structure is disposed on a side of the first sub-part close to the first drain.
In an embodiment of the invention, two of the mark structures on two of the first sub-portions adjacent to each other along the first direction are distributed in axial symmetry, or are distributed in central symmetry.
In an embodiment of the invention, in two adjacent first sub-portions along the second direction, a side of one of the first sub-portions where the mark structure is disposed is opposite to or opposite to a side of the other of the first sub-portions where the mark structure is disposed.
In an embodiment of the invention, the mark structure includes a protrusion disposed on the first sub-portion, a length of the protrusion along the first direction is less than or equal to a width of the first sub-portion along the first direction, and a material of the protrusion is the same as a material of the first sub-portion.
In an embodiment of the invention, the first conductive layer further includes a plurality of scan lines extending along the first direction and arranged along the second direction, any scan line is located between the pixel functional regions adjacent to each other along the second direction, and a distance from one end of the protrusion away from the first sub-portion to any position of the scan line is greater than or equal to 6 micrometers.
In an embodiment of the invention, the pixel electrode layer includes a plurality of first connection portions and a plurality of second connection portions, and one of the first connection portions is connected between one of the first pixel electrodes and one of the first drain electrodes, and one of the second connection portions is connected between one of the second pixel electrodes and one of the second drain electrodes;
wherein, the orthographic projection of the mark structure on the substrate is not overlapped with the orthographic projection of the first connecting part on the substrate, and the orthographic projection of the second connecting part on the substrate.
According to the above object of the present invention, a method for manufacturing a display panel is provided, the display panel includes a plurality of pixel functional regions, and each of the pixel functional regions includes a first sub-pixel region and a second sub-pixel region adjacent to each other;
the manufacturing method of the display panel comprises the following steps:
providing a substrate;
forming a first conducting layer on one side of the substrate, wherein the first conducting layer comprises a first common signal part which is positioned in the pixel functional area and at least arranged on the periphery of the first sub-pixel area, and a mark structure is arranged on the first common signal part;
forming a second conducting layer on a side of the first conducting layer away from the substrate, wherein the second conducting layer comprises a first drain electrode and a second drain electrode which are arranged in each pixel function area, the distance from the first drain electrode to the first sub-pixel area is smaller than the distance from the first drain electrode to the second sub-pixel area, the distance from the second drain electrode to the first sub-pixel area is smaller than the distance from the second drain electrode to the second sub-pixel area, and the mark structure is positioned on one side of the first common signal part close to each first drain electrode;
and forming a pixel electrode layer on one side of the second conducting layer, which is far away from the first conducting layer, wherein the pixel electrode layer comprises a first pixel electrode arranged in the first sub-pixel area and a second pixel electrode arranged in the second sub-pixel area, the first drain electrode is electrically connected with the first pixel electrode, and the second drain electrode is electrically connected with the second pixel electrode.
In an embodiment of the present invention, the method for manufacturing the display panel further includes the following steps:
detecting the display state of the display panel and acquiring a repair sub-pixel area with abnormal display;
acquiring the position of the mark structure in the pixel function area where the repair sub-pixel area is located;
identifying the first drain electrode close to the mark structure and the first sub-pixel region corresponding to the first drain electrode;
and if the repair sub-pixel region is the first sub-pixel region, cutting off a signal transmission channel of the first drain electrode, and if the repair sub-pixel region is the second sub-pixel region, cutting off a signal transmission channel of the second drain electrode.
The invention has the beneficial effects that: according to the invention, the mark structure is arranged at the position, close to the first drain electrode, of the first public signal part, so that in the repairing process, the mark structure can be identified to obtain the first drain electrode close to the mark structure, obtain the first sub-pixel region, close to the first drain electrode, in the pixel function region, and determine the second drain electrode and the second sub-pixel region corresponding to the second drain electrode, so that the first sub-pixel region or the second sub-pixel region can be accurately subjected to shading repairing, and the shading repairing success rate and repairing efficiency are improved.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
FIG. 1 is a schematic plan view of a DLS structure of a conventional display panel;
fig. 2 is a schematic distribution diagram of a DLS-architecture routing device of a conventional display panel;
FIG. 3 is a schematic diagram of a planar distribution structure of a display panel according to an embodiment of the present invention;
FIG. 4 is a schematic view of another planar distribution structure of a display panel according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a method for fabricating a display panel according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a structure of repairing a dark spot of a display panel according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Referring to fig. 3 and 4, the display panel includes a plurality of pixel functional regions 101, and each pixel functional region 101 includes a first sub-pixel region 1011 and a second sub-pixel region 1012 adjacent to each other.
Further, the display panel further includes a substrate (not shown), a first conductive layer 20, a second conductive layer 30, and a pixel electrode layer 40; the first conducting layer 20 is disposed on one side of the substrate, and includes a first common signal portion 21 located in the pixel functional region 101 and disposed at least on the periphery of the first sub-pixel region 1011; the second conducting layer 30 is disposed on a side of the first conducting layer 20 away from the substrate, and includes a first drain 31 and a second drain 32 disposed in each pixel functional region 101, a distance from the first drain 31 to the first sub-pixel region 1011 is less than a distance from the first drain 31 to the second sub-pixel region 1012, and a distance from the second drain 32 to the first sub-pixel region 1011 is less than a distance from the second drain 32 to the second sub-pixel region 1012; the pixel electrode layer 40 is disposed on a side of the second conductive layer 30 away from the first conductive layer 20, and the pixel electrode layer 40 includes a first pixel electrode 41 disposed in the first sub-pixel region 1011 and a second pixel electrode 42 disposed in the second sub-pixel region 1012.
The first drain 31 is electrically connected to the first pixel electrode 41, the second drain 32 is electrically connected to the second pixel electrode 42, and the mark structure 25 is disposed at a position of the first common signal portion 21 close to each of the first drains 31.
In the implementation and application process, the mark structure 25 is arranged on the side of the first common signal portion 21 close to the first drain 31, so that in the repairing process, the mark structure 25 can be identified to obtain the first drain 31 close to the mark structure 25, obtain the first sub-pixel region 1011 closer to the first drain 31 in the pixel function region 101, and determine the second drain 32 and the second sub-pixel region 1012 corresponding to the second drain 32, so that the first sub-pixel region 1011 or the second sub-pixel region 1012 can be accurately repaired, and the success rate of repairing and the repairing efficiency are improved.
Specifically, with reference to fig. 3 and fig. 4, the display panel includes a plurality of pixel functional regions 101, each pixel functional region 101 includes a first sub-pixel region 1011 and a second sub-pixel region 1012 adjacent to each other, and the display panel includes a plurality of first sub-pixel regions 1011 and a plurality of second sub-pixel regions 1012.
In the embodiment of the present invention, a first direction X and a second direction Y are set to be perpendicular to each other, the plurality of pixel functional regions 101 are arranged in an array along the first direction X and the second direction Y, the plurality of first sub-pixel regions 1011 and the plurality of second sub-pixel regions 1012 are also arranged in an array along the first direction X and the second direction Y, and the first sub-pixel regions 1011 and the second sub-pixel regions 1012 are disposed adjacent to each other along the first direction X in each pixel functional region 101.
The display panel further comprises a substrate, a first conducting layer 20 arranged on the substrate, a second conducting layer 30 arranged on the first conducting layer 20, and a pixel electrode layer 40 arranged on the second conducting layer 30.
The first conductive layer 20 includes a plurality of scan lines 23 extending along the first direction X and arranged along the second direction, a gate 24 electrically connected to each scan line 23, a first common signal portion 21 surrounding each first sub-pixel area 1011 and each second sub-pixel area 1012, and a second common signal portion 22 located in each first sub-pixel area 1011 and each second sub-pixel area 1012 and connected to the first common signal portion 21. It can be understood that the scan lines 23 are used for transmitting scan signals to the gate electrodes 24, and the first common signal portion 21 and the second common signal portion 22 can transmit common voltage signals therein, and the first common signal portion 21 and the second common signal portion 22 are connected to form a mesh structure distributed on the substrate.
The second conductive layer 30 includes a plurality of data lines 33 extending along the second direction Y and arranged along the first direction X, a plurality of source electrodes 34, a plurality of first drain electrodes 31, and a plurality of second drain electrodes 32, wherein each pixel functional region 101 is located between two adjacent data lines 33; a gate 24, a source 34, a first drain 31 and a second drain 32 are disposed in each pixel functional region 101, and the gate 24, the source 34, the first drain 31 and the second drain 32 are all located outside the first sub-pixel region 1011 and the second sub-pixel region 1012 to prevent the gate 24, the source 34, the first drain 31 and the second drain 32 from affecting the light transmission of the first sub-pixel region 1011 and the second sub-pixel region 1012, and in each pixel functional region 101, the first drain 31 and the second drain 32 are both disposed adjacent to the first sub-pixel region 1011, i.e., the distance from the first drain 31 to the first sub-pixel region 1011 is less than the distance from the first drain 31 to the second sub-pixel region 1012, and the distance from the second drain 32 to the first sub-pixel region 1011 is less than the distance from the second drain 32 to the second sub-pixel region 1012.
Preferably, in each pixel functional region 101, the first drain electrode 31 and the second drain electrode 32 are disposed adjacent to the first sub-pixel region 1011 along the second direction Y, and the first drain electrode 31 and the second drain electrode 32 are respectively disposed on two opposite sides of the first sub-pixel region 1011 along the second direction Y.
The pixel electrode layer 40 includes a plurality of pixel electrodes, and the plurality of pixel electrodes includes a plurality of first pixel electrodes 41 and a plurality of second pixel electrodes 42, wherein each of the first pixel electrodes 41 is correspondingly disposed in a first sub-pixel region 1011, and each of the second pixel electrodes 42 is correspondingly disposed in a second sub-pixel region 1012. In the embodiment of the invention, in each pixel functional region 101, the first drain 31 is electrically connected to the first pixel electrode 41, and the second drain 32 is electrically connected to the second pixel electrode 42; the pixel electrode layer 40 further includes a plurality of first connection portions 43 and a plurality of second connection portions 44, each first connection portion 43 is connected between a corresponding first drain electrode 31 and the first pixel electrode 41, and each second connection portion 44 is connected between a corresponding second drain electrode 32 and the second pixel electrode 42; specifically, one end of the first connection portion 43 is connected to the first pixel electrode 41, and the other end is connected to the first drain electrode 31 through the via 45, and one end of the second connection portion 43 is connected to the second pixel electrode 42, and the other end is connected to the second drain electrode 32 through the via 45.
In the embodiment of the present invention, in each pixel function region 101, the first drain 31 and the second drain 32 are located on two opposite sides of the first sub-pixel region 1011 along the second direction Y, so that the distance from the first drain 31 to the first sub-pixel region 1011 is less than the distance from the first drain 31 to the second sub-pixel region 1012, the distance from the second drain 32 to the first sub-pixel region 1011 is less than the distance from the second drain 32 to the second sub-pixel region 1012, that is, the connection distance between the first drain 31 and the first pixel electrode 41 is less than the connection distance between the second drain 32 and the second pixel electrode 42, and correspondingly, the length of the first connection portion 43 along the first direction X is less than the length of the second connection portion 44 along the first direction X.
However, in the process of performing the shading repair for display, since the pixel electrode layer 40 needs to satisfy the requirement of light transmission, and is generally made of a transparent conductive material, an image observed under backlight is as shown in fig. 3, the pixel electrode layer 40 cannot be observed, and the connection relationship between the first drain electrode 31 and the second drain electrode 32 and the first sub-pixel region 1011 and the second sub-pixel region 1012 cannot be determined. In the embodiment of the present invention, the mark structure 25 is disposed at the position of the first common signal portion 21 close to the first drain 31, that is, in each pixel function region 101, the distance from the first drain 31 to the mark structure 25 is smaller than the distance from the second drain 32 to the mark structure 25, and the mark structure 25 is disposed at the side of the first common signal portion 21 close to the first drain 31 and away from the second drain 32 along the second direction Y, so that the position of the mark structure 25 can be obtained to identify that the position close to the mark structure 25 is the first drain 31, that is, the first drain 31 corresponds to a sub-pixel region (i.e., the first sub-pixel region 1011) adjacent to the first drain 31, and the second drain 32 corresponds to another sub-pixel region (i.e., the second sub-pixel region 1012).
Further, the first common signal part 21 includes a first sub-portion 211 located between the first sub-pixel area 1011 and the second sub-pixel area 1012, and the mark structure 25 is disposed on a side of the first sub-portion 211 close to the first drain 31.
Optionally, the mark structure 25 includes a protrusion 251 disposed on a side of the first sub-portion 211 close to the first drain 31, a length of the protrusion 251 along the first direction X is less than or equal to a width of the first sub-portion 211 along the first direction X, and a material of the protrusion 251 is the same as a material of the first sub-portion 211, that is, the protrusion 251 and the first sub-portion 211 may be integrally formed.
In other embodiments of the present invention, the mark structure 25 may also be a concave portion disposed on a side of the first sub-portion 211 close to the first drain 31, and the shape and size of the concave portion are not limited herein.
In the embodiment of the present invention, any one of the scanning lines 23 is disposed between two adjacent pixel function regions 101 along the second direction Y, and two scanning lines 23 are disposed between two adjacent pixel function regions 101 along the second direction Y, and one of the scanning lines 23 is used for connecting the gate 24 in one of the pixel function regions 101, and the other scanning line 23 is used for connecting the gate 24 in the other pixel function region 101.
It should be noted that, the mark structure 25 is disposed on a side of the first sub-portion 211 close to the first drain 31, that is, the mark structure 25 is also disposed on a side of the first sub-portion 211 close to the scan line 23, in an embodiment of the present invention, a distance from the mark structure 25 to any position of the scan line 23 is less than or equal to 6 micrometers, when the mark structure 25 is connected to the first sub-portion 211, the same electrical signal is applied to the mark structure 25 and the first sub-portion 211, and further in the embodiment of the present invention, the mark structure 25 is disposed farther from the scan line 23, so as to prevent signal crosstalk between the mark structure 25 and the scan line 23. Further, the orthographic projection of the mark structure 25 on the substrate is not overlapped with the orthographic projection of the first connecting portion 43 on the substrate and the orthographic projection of the second connecting portion 44 on the substrate, so as to avoid generating parasitic capacitance and signal crosstalk.
In the embodiment of the present invention, between two adjacent pixel functional regions 101 along the first direction X, a first sub-pixel region 1011 in one pixel functional region 101 is disposed adjacent to a second sub-pixel region 1012 in another pixel functional region 101, that is, in the plurality of pixel functional regions 101 arranged along the first direction X, a first sub-pixel region 1011 and a second sub-pixel region 1012 are alternately arranged; between two adjacent pixel functional regions 101 along the second direction Y, a first sub-pixel region 1011 in one pixel functional region 101 is disposed opposite to a second sub-pixel region 1012 in another pixel functional region 101, and a second sub-pixel region 1012 in one pixel functional region 101 is disposed opposite to the first sub-pixel region 1011 in another pixel functional region 101.
The two mark structures 25 on two adjacent first sub-portions 211 along the first direction X are distributed in an axisymmetric manner, or in a centrosymmetric manner. In two adjacent first sub-portions 211 along the second direction Y, a side of one first sub-portion 211 where the mark structure 25 is disposed is opposite to or opposite to a side of the other first sub-portion 211 where the mark structure 25 is disposed, or a side of one first sub-portion 211 where the mark structure 25 is disposed is opposite to a side of the other first sub-portion 211 where the mark structure 25 is not disposed.
It should be noted that the display panel provided by the embodiment of the invention can be a display panel with DLS architecture, wherein each pixel functional region 101 is located between two adjacent data lines 33, the first sub-pixel region 1011 and the second sub-pixel region 1012 in each pixel functional region 101 are correspondingly connected to the same data line 33, two pixel functional regions 101 adjacent to each other along the first direction X are correspondingly connected to two adjacent data lines 33, and the first sub-pixel area 1011 and the second sub-pixel area 1012 in each pixel functional area 101 correspond to two different scan lines 23 respectively, the two different scan lines 23 are respectively located at two opposite sides of the pixel functional region 101 along the second direction Y, and the first sub-pixel region 1011 and the second sub-pixel region 1012 in two adjacent pixel functional regions 101 along the second direction Y are respectively and correspondingly connected to two adjacent data lines 33. It should be understood that, in the above description, the first sub-pixel region 1011 and the second sub-pixel region 1012 are connected to the data line 33 or the scan line 23 correspondingly, and it is indicated that the source electrode 34 corresponding to the first sub-pixel region 1011 and the source electrode 34 corresponding to the second sub-pixel region 1012 are connected to the corresponding data line 33, or the gate electrode 24 corresponding to the first sub-pixel region 1011 and the gate electrode 24 corresponding to the second sub-pixel region 1012 are connected to the corresponding scan line 23.
In addition, the mark structure 25 is not limited to be disposed on the side of the first sub-portion 211 close to the first drain 31, and in other embodiments of the present invention, when the first drain 31 and the second drain 32 are located on two opposite sides of the first sub-pixel area 1011, the mark structure 25 is disposed on the side of the first common signal portion 21 close to the first drain 31, and can be located on any position of the side as a mark for identifying the first drain 31.
In summary, in the embodiment of the present invention, the mark structure 25 is disposed on the side of the first common signal portion 21 close to the first drain 31, and in the repairing process, the mark structure 25 is identified to obtain the first drain 31 close to the mark structure 25, obtain the first sub-pixel region 1011 in the pixel functional region 101 closer to the first drain 31, and determine the second drain 32 and the second sub-pixel region 1012 corresponding to the second drain 32, so that the first sub-pixel region 1011 or the second sub-pixel region 1012 can be accurately repaired, thereby improving the success rate of repairing and the repairing efficiency.
In addition, an embodiment of the present invention further provides a method for manufacturing a display panel described in the above embodiments, please refer to fig. 3, fig. 4, fig. 5, and fig. 6, in which the display panel includes a plurality of pixel functional regions 101, and each of the pixel functional regions 101 includes a first sub-pixel region 1011 and a second sub-pixel region 1012 adjacent to each other.
The manufacturing method of the display panel comprises the following steps:
and S10, providing a substrate.
S20, forming a first conducting layer 20 on one side of the substrate, wherein the first conducting layer 20 includes a first common signal portion 21 located in the pixel functional region 101 and disposed at least on the periphery of the first sub-pixel region 1011, and the first common signal portion 21 is disposed with the mark structure 25.
A first conductive layer 20 is formed on one side of the substrate, and the first conductive layer 20 includes a plurality of scanning lines 23 extending along the first direction X and arranged along the second direction, a gate 24 electrically connected to each scanning line 23, a first common signal portion 21 surrounding each first sub-pixel region 1011 and each second sub-pixel region 1012, and a second common signal portion 22 located in each first sub-pixel region 1011 and each second sub-pixel region 1012 and connected to the first common signal portion 21. It is understood that the scan lines 23 are used for transmitting scan signals to the gate electrodes 24, the first common signal portion 21 and the second common signal portion 22 can transmit common voltage signals therein, and the first common signal portion 21 and the second common signal portion 22 are connected to each other to form a mesh structure distributed on the substrate.
Note that the mark structure 25 is provided on the side of the first common signal section 21 for each pixel function region 101.
S30, forming a second conducting layer 30 on a side of the first conducting layer 20 away from the substrate, where the second conducting layer 30 includes a first drain 31 and a second drain 32 disposed in each pixel functional region 101, and in each pixel functional region 101, a distance from the first drain 31 to the first sub-pixel region 1011 is less than a distance from the first drain 31 to the second sub-pixel region 1012, a distance from the second drain 32 to the first sub-pixel region 1011 is less than a distance from the second drain 32 to the second sub-pixel region 1012, and the mark structure 25 is located on a side of the first common signal portion 21 close to each first drain 31.
Forming a second conducting layer 30 on a side of the first conducting layer 20 away from the substrate, the second conducting layer including a plurality of data lines 33 extending along the second direction Y and arranged along the first direction X, a plurality of source electrodes 34, a plurality of first drain electrodes 31, and a plurality of second drain electrodes 32, wherein each pixel function region 101 is located between two adjacent data lines 33; a gate 24, a source 34, a first drain 31 and a second drain 32 are disposed in each pixel functional region 101, and the gate 24, the source 34, the first drain 31 and the second drain 32 are all located outside the first sub-pixel region 1011 and the second sub-pixel region 1012 to prevent the gate 24, the source 34, the first drain 31 and the second drain 32 from affecting the light transmission of the first sub-pixel region 1011 and the second sub-pixel region 1012, and in each pixel functional region 101, the first drain 31 and the second drain 32 are both disposed adjacent to the first sub-pixel region 1011, i.e., the distance from the first drain 31 to the first sub-pixel region 1011 is less than the distance from the first drain 31 to the second sub-pixel region 1012, and the distance from the second drain 32 to the first sub-pixel region 1011 is less than the distance from the second drain 32 to the second sub-pixel region 1012.
Preferably, in each pixel functional region 101, the first drain electrode 31 and the second drain electrode 32 are disposed adjacent to the first sub-pixel region 1011 along the second direction Y, and the first drain electrode 31 and the second drain electrode 32 are respectively disposed on two opposite sides of the first sub-pixel region 1011 along the second direction Y.
In the embodiment of the invention, the mark structure 25 is disposed on a side of the first common signal portion 21 close to the first drain 31 and a side far from the second drain 32.
S40, forming a pixel electrode layer 40 on a side of the second conductive layer 30 away from the first conductive layer 20, where the pixel electrode layer 40 includes a first pixel electrode 41 disposed in the first sub-pixel region 1011 and a second pixel electrode 42 disposed in the second sub-pixel region 1012, and the first drain 31 is electrically connected to the first pixel electrode 41, and the second drain 32 is electrically connected to the second pixel electrode 42.
A pixel electrode layer 40 is formed on a side of the second conductive layer 30 away from the first conductive layer 20, the pixel electrode layer 40 includes a plurality of pixel electrodes, and the plurality of pixel electrodes includes a plurality of first pixel electrodes 41 and a plurality of second pixel electrodes 42, wherein each first pixel electrode 41 is correspondingly disposed in a first sub-pixel region 1011, and each second pixel electrode 42 is correspondingly disposed in a second sub-pixel region 1012. In the embodiment of the invention, in each pixel functional region 101, the first drain 31 is electrically connected to the first pixel electrode 41, and the second drain 32 is electrically connected to the second pixel electrode 42; the pixel electrode layer 40 further includes a plurality of first connection portions 43 and a plurality of second connection portions 44, each first connection portion 43 is connected between a corresponding first drain electrode 31 and the first pixel electrode 41, and each second connection portion 44 is connected between a corresponding second drain electrode 32 and the second pixel electrode 42; specifically, one end of the first connection portion 43 is connected to the first pixel electrode 41, and the other end is connected to the first drain electrode 31 through the via 45, and one end of the second connection portion 43 is connected to the second pixel electrode 42, and the other end is connected to the second drain electrode 32 through the via 45.
Further, the manufacturing method of the display panel further comprises the following steps:
and detecting the display state of the display panel and acquiring a repair sub-pixel area with abnormal display.
The position of the marker structure 25 within the pixel function area 101 where the patch sub-pixel area is located is obtained. The images observed under the backlight are shown in fig. 3 and fig. 6, and it is confirmed that the patch sub-pixel region belongs to the pixel functional region 101, and each pixel functional region 101 is located between two adjacent data lines 33. The position of the marker structure 25 within the corresponding pixel function 101 is obtained.
The first drain 31 near the mark structure 25 and the first sub-pixel area 1011 corresponding to the first drain 31 are identified. In the embodiment of the present invention, the first drain 31 and the second drain 32 are respectively located at two opposite sides of the first sub-pixel region 1011, and therefore, a drain located at the same side as the mark structure 25 can be identified as the first drain 31 by the position of the mark structure 25, so that the drain (i.e., the first drain 31) corresponds to the adjacent first sub-pixel region 1011, and the other drain is the second drain 32, and the other drain (i.e., the second drain 32) corresponds to the other sub-pixel region (i.e., the second sub-pixel region 1012) in the corresponding pixel function region 101.
If the repair sub-pixel region is the first sub-pixel region 1011, the signal transmission path of the first drain electrode 31 is cut off, and if the repair sub-pixel region is the second sub-pixel region 1012, the signal transmission path of the second drain electrode 32 is cut off.
In the embodiment of the present invention, taking the repaired sub-pixel area as the first sub-pixel area 1011 as an example, the signal transmission channel of the first drain 31 needs to be cut off, specifically, the laser technology can be used to cut off the side of the first drain 31 close to the source 34 to form the first partition 61, and the laser technology can also be used to cut off the connection portion between the first drain 31 and the first pixel electrode 41, that is, the first connection portion 43 can be cut off by blind cutting to form the second partition 62, so that the first sub-pixel area 1011 forms a dark spot, thereby achieving the purpose of repairing.
In summary, in the embodiment of the invention, the mark structure 25 is disposed on the side of the first common signal portion 21 close to the first drain 31, and then in the repairing process, the mark structure 25 is identified to obtain the first drain 31 close to the mark structure 25, obtain the first sub-pixel region 1011 inside the pixel functional region 101 closer to the first drain 31, and determine the second drain 32 and the second sub-pixel region 1012 corresponding to the second drain 32, so that the first sub-pixel region 1011 or the second sub-pixel region 1012 can be accurately repaired, thereby improving the success rate of repairing and the repairing efficiency.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel and the manufacturing method thereof provided by the embodiment of the invention are described in detail, a specific example is applied in the description to explain the principle and the implementation of the invention, and the description of the embodiment is only used to help understanding the technical scheme and the core idea of the invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A display panel is characterized in that the display panel comprises a plurality of pixel functional areas, and each pixel functional area comprises a first sub-pixel area and a second sub-pixel area which are adjacent;
the display panel further includes:
a substrate;
a first conductive layer; the first common signal part is arranged on one side of the substrate and comprises a first common signal part which is positioned in the pixel functional area and is at least arranged on the peripheral side of the first sub-pixel area;
the second conducting layer is arranged on one side, far away from the substrate, of the first conducting layer and comprises a first drain electrode and a second drain electrode which are arranged in each pixel functional area, the distance from the first drain electrode to the first sub-pixel area is smaller than the distance from the first drain electrode to the second sub-pixel area, and the distance from the second drain electrode to the first sub-pixel area is smaller than the distance from the second drain electrode to the second sub-pixel area;
the pixel electrode layer is arranged on one side, far away from the first conducting layer, of the second conducting layer and comprises a first pixel electrode arranged in the first sub-pixel area and a second pixel electrode arranged in the second sub-pixel area;
the first drain is electrically connected with the first pixel electrode, the second drain is electrically connected with the second pixel electrode, and the first common signal part is provided with a mark structure close to each first drain.
2. The display panel according to claim 1, wherein the plurality of pixel functional regions are arranged in an array along a first direction and a second direction, the first direction is different from the second direction, and a first sub-pixel region and a second sub-pixel region are disposed adjacent to each other along the first direction in each pixel functional region;
and in each pixel function region, the first drain and the second drain are respectively positioned at two opposite sides of the first sub-pixel region, and the mark structure is arranged at one side of the first common signal part close to the first drain along the second direction.
3. The display panel according to claim 2, wherein in each of the pixel function regions, the first common signal portion is disposed around the first sub-pixel region and the second sub-pixel region, and includes a first sub-portion located between the first sub-pixel region and the second sub-pixel region, and the mark structure is disposed on a side of the first sub-portion close to the first drain.
4. The display panel according to claim 3, wherein two of the mark structures on two of the first sub-portions adjacent to each other along the first direction are distributed in axial symmetry or in central symmetry.
5. The display panel according to claim 3, wherein two of the first sub-portions adjacent to each other in the second direction are disposed opposite to or opposite to a side of the other first sub-portion on which the mark structure is disposed.
6. The display panel according to claim 3, wherein the mark structure comprises a protrusion disposed on the first sub-portion, a length of the protrusion along the first direction is less than or equal to a width of the first sub-portion along the first direction, and a material of the protrusion is the same as a material of the first sub-portion.
7. The display panel according to claim 6, wherein the first conductive layer further includes a plurality of scan lines extending in the first direction and arranged in the second direction, any one of the scan lines is located between the pixel functional regions adjacent to each other in the second direction, and a distance from one end of the protrusion away from the first sub-portion to any position of the scan line is greater than or equal to 6 μm.
8. The display panel according to claim 1, wherein the pixel electrode layer comprises a plurality of first connecting portions and a plurality of second connecting portions, one of the first connecting portions is connected between one of the first pixel electrodes and one of the first drain electrodes, and one of the second connecting portions is connected between one of the second pixel electrodes and one of the second drain electrodes;
wherein, the orthographic projection of the mark structure on the substrate is not overlapped with the orthographic projection of the first connecting part on the substrate, and the orthographic projection of the second connecting part on the substrate.
9. The manufacturing method of the display panel is characterized in that the display panel comprises a plurality of pixel functional areas, and each pixel functional area comprises a first sub-pixel area and a second sub-pixel area which are adjacent;
the manufacturing method of the display panel comprises the following steps:
providing a substrate;
forming a first conducting layer on one side of the substrate, wherein the first conducting layer comprises a first common signal part which is positioned in the pixel functional area and at least arranged on the periphery of the first sub-pixel area, and a mark structure is arranged on the first common signal part;
forming a second conducting layer on a side of the first conducting layer away from the substrate, wherein the second conducting layer comprises a first drain electrode and a second drain electrode which are arranged in each pixel function area, the distance from the first drain electrode to the first sub-pixel area is smaller than the distance from the first drain electrode to the second sub-pixel area, the distance from the second drain electrode to the first sub-pixel area is smaller than the distance from the second drain electrode to the second sub-pixel area, and the mark structure is positioned on one side of the first common signal part close to each first drain electrode;
and forming a pixel electrode layer on one side of the second conducting layer, which is far away from the first conducting layer, wherein the pixel electrode layer comprises a first pixel electrode arranged in the first sub-pixel area and a second pixel electrode arranged in the second sub-pixel area, the first drain electrode is electrically connected with the first pixel electrode, and the second drain electrode is electrically connected with the second pixel electrode.
10. The method for manufacturing a display panel according to claim 9, further comprising the steps of:
detecting the display state of the display panel and acquiring a repair sub-pixel area with abnormal display;
acquiring the position of the mark structure in the pixel function area where the repair sub-pixel area is located;
identifying the first drain electrode close to the mark structure and the first sub-pixel region corresponding to the first drain electrode;
and if the repair sub-pixel region is the first sub-pixel region, cutting off a signal transmission channel of the first drain electrode, and if the repair sub-pixel region is the second sub-pixel region, cutting off a signal transmission channel of the second drain electrode.
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