CN114795249A - Brain-computer interface front-end device and brain electrode system - Google Patents
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Abstract
The invention relates to the technical field of brain-computer interfaces, and discloses a brain-computer interface front-end device and a brain electrode system. The brain-computer interface front-end device comprises a control chip, a stimulation module and a test module, wherein the stimulation module is used for generating a stimulation signal, the stimulation signal is used for stimulating a cerebral cortex through the brain electrode structure, and the control chip is used for performing on-off control on a channel of the brain electrode structure and switching input of a test signal and the stimulation signal; the test module is used for receiving the test result signal sent by the control chip and carrying out digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the control chip based on the test signal. After the device is connected with the brain electrode structure, stimulation and collection of the brain electrode can be achieved based on the device, and the control chip can be tested based on the testing module.
Description
Technical Field
The invention relates to the technical field of brain-computer interfaces, in particular to a brain-computer interface front-end device and a brain electrode system.
Background
The brain-computer interface is a cross technology relating to multiple disciplines such as neuroscience, signal detection and signal processing, and has important research significance and great application potential in the fields of biomedicine, nerve rehabilitation, intelligent robots and the like. The method comprises the steps of establishing a direct communication and control channel between the human brain and a computer or other electronic equipment, acquiring electroencephalogram signals from the cerebral cortex, converting the electroencephalogram signals into signals which can be identified by the computer through amplification, filtering, A/D conversion and other processing, preprocessing the signals, extracting characteristic signals, performing mode identification by using the characteristics, and finally converting the characteristic signals into specific instructions for controlling external equipment to realize the control of the external equipment.
Electrophysiological signals in the brain are distributed over a wide spatial and temporal scale. Recording the spiking activity of many individual neurons in brain circuits with high spatial and temporal resolution at the same time is critical to study how the complex nervous system handles information from microscopic to mesoscopic spatial scales, deciphering how brain circuits function and the possible dysfunctions in disease.
However, the high-flux electrode in the prior art has single function, cannot realize signal acquisition in various states, and limits the development of brain-computer interface technology.
Disclosure of Invention
The invention aims to solve the technical problem that the function of a front-end device of a brain-computer interface is single in the prior art.
In order to solve the above technical problem, the present application discloses, in one aspect, a brain-computer interface front-end device, which includes a control chip, a stimulation module, and a test module;
the stimulation module and the test module are respectively connected with the control chip;
the pad area of the control chip is correspondingly connected with the pad structure of the brain electrode structure;
the stimulation module is used for generating a stimulation signal, and the stimulation signal is used for stimulating the cerebral cortex through the brain electrode structure;
the control chip is used for performing on-off control on a channel of the brain electrode structure and switching input of a test signal and the stimulation signal;
the test module is used for receiving the test result signal sent by the control chip and carrying out digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the control chip based on the test signal.
Optionally, the system further comprises a digital-to-analog conversion module and a power supply module;
the digital-to-analog conversion module is connected with the control chip;
the power module is connected with the control chip and the digital-to-analog conversion module;
the power module is used for supplying power to the control chip and the digital-to-analog conversion module;
the power supply module comprises a lithium battery, a first low dropout linear regulator and a second low dropout linear regulator;
the lithium battery is connected with the control chip through the first low-dropout linear regulator;
the lithium battery is connected with the digital-to-analog conversion module through the second low dropout linear regulator;
the digital-to-analog conversion module is used for receiving the electroencephalogram signals sent by the control chip and performing digital-to-analog conversion processing on the electroencephalogram signals.
Optionally, the voltage of the lithium battery comprises 3.7 volts;
the voltage range output by the first low dropout regulator comprises 0.5-3.3V;
the voltage output by the second low dropout regulator comprises 1-1.8V.
Optionally, the channels of the control chip include 128 × 128 channels;
the bonding pad structure comprises 128 x 128 welding points;
the pad area includes 128 × 128 pads;
the welding points of the welding pad structure are correspondingly connected with the welding points of the welding pad area in a one-to-one mode through flip chip welding.
Optionally, the system further includes a Field Programmable Gate Array (FPGA) chip;
the field programmable gate array chip is connected with the control chip, the digital-to-analog conversion module, the test module and the stimulation module;
the field programmable gate array chip is used for supplying power to the test module and the stimulation module and sending the received electroencephalogram signals sent by the digital-to-analog converter to the signal acquisition equipment;
the voltage of the field programmable gate array chip comprises 5 volts.
Optionally, the stimulation voltage range output by the stimulation module is 0-3.3 volts;
the error range of the stimulation voltage value output by the stimulation module and the preset voltage value is 0-0.4 millivolt.
Optionally, the brain electrode structure comprises a contact electrode structure connected with the pad structure;
the contact electrode structure realizes the acquisition of electroencephalogram signals through the contact with the scalp layer.
Optionally, the contact electrode structure includes N contact electrodes; n is an integer greater than or equal to 1;
the bonding pad structure comprises N welding points;
the control chip comprises a processor and N pixel circuits which are connected; the pixel circuits are connected with the N welding spots in a one-to-one corresponding mode;
the processor is used for controlling the on or off of any one of the N contact electrodes by controlling the on or off of any one of the N pixel circuits; and when any one of the pixel circuits is conducted, the processor controls any one of the pixel circuits to output a corresponding stimulation signal or test signal through the received stimulation signal or test signal, and further realizes the stimulation of any one of the contact electrodes to the target cerebral cortex brain or the control of the corresponding pixel circuit test.
Optionally, the contact electrode structure includes M sub-contact electrode structures, where M is an integer greater than or equal to 1;
a preset interval exists between adjacent sub-contact electrode structures in the M sub-contact electrode structures;
the M sub-contact electrode structures are located on the same plane.
The application discloses in another aspect a brain electrode system, which comprises the brain electrode structure and the brain-computer interface front-end device.
The application provides a brain-computer interface front end device has following beneficial effect: the brain-computer interface front-end device comprises a control chip, a stimulation module and a test module, wherein the stimulation module is used for generating a stimulation signal, the stimulation signal is used for stimulating a cerebral cortex through the brain electrode structure, and the control chip is used for performing on-off control on a channel of the brain electrode structure and switching input of a test signal and the stimulation signal; the test module is used for receiving the test result signal sent by the control chip and carrying out digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the control chip based on the test signal. After the device is connected with the brain electrode structure, stimulation and collection of the brain electrode can be achieved based on the device, and testing of the control chip can be achieved based on the testing module.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an alternative front-end brain-computer interface device according to the present application;
FIG. 2 is a schematic structural diagram of an alternative front-end brain-computer interface device of the present application;
FIG. 3 is a schematic diagram of an alternative pixel circuit according to the present application;
FIG. 4 is a schematic diagram of an alternative pixel circuit according to the present application;
FIG. 5 is a schematic diagram of an alternative parallel pixel circuit according to the present application;
FIG. 6 is a schematic view of a first alternative contact electrode arrangement of the present application;
FIG. 7 is a model diagram of the potential distribution of the contact electrode structure at time t 1;
FIG. 8 is a model diagram of the potential distribution of the contact electrode structure at time t 2;
FIG. 9 is an alternative equivalent circuit diagram of the present application in an operational state when the contact electrode is inserted into brain tissue;
FIG. 10 is a schematic view of a second alternative contact electrode arrangement according to the present application;
FIG. 11 is a schematic view of a third alternative contact electrode arrangement of the present application;
fig. 12 is a flow chart of an alternative method of controlling the electroencephalograph of the present application.
The following is a supplementary description of the drawings:
1-a control chip; 2-brain electrode structure; 21-a contact electrode structure; 211 — a first contact electrode; 212-second contact electrode; 22-pad structure; 3-a stimulation module; 4-a test module; 5-a digital-to-analog conversion module; 6-a power supply module; 7-field programmable gate array chip.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the present application. In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
Generally, a device for acquiring electroencephalogram signals only has a function of acquiring electroencephalogram signals, so that the function is single, and the requirement of brain-computer interface exploration which is increasingly developed cannot be met, based on which, the application provides a brain-computer interface front-end device, referring to fig. 1, fig. 1 is a schematic structural diagram of an optional brain-computer interface front-end device in the application, the brain-computer interface front-end device includes a control chip 1, a stimulation module 3 and a test module 4, the stimulation module 3 and the test module 4 are respectively connected with the control chip 1, a pad area of the control chip 1 is correspondingly connected with a pad structure 22 of a brain electrode structure 2, the stimulation module 3 is used for generating stimulation signals, and the stimulation signals are used for stimulating a cerebral cortex through the brain electrode structure 2; the control chip 1 is used for performing on-off control on a channel of the brain electrode structure 2 and switching input of a test signal and the stimulation signal; the test module 4 is used for receiving the test result signal sent by the control chip 1 and performing digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the control chip 1 based on the test signal.
Therefore, the brain-computer interface front-end device provided by the application can not only realize the collection and stimulation of the cerebral cortex, but also realize the test of the pixel circuit in the control chip 1 based on the matching of the control chip 1 and the test module 4. For example, it may be a test for short and open circuits of the following pixel circuit.
In order to better transmit information without distortion and compress data, analog-to-digital conversion needs to be performed on analog signals directly acquired by the electrodes. In an alternative embodiment, referring to fig. 2, fig. 2 is a schematic structural diagram of another alternative brain-computer interface front-end device according to the present application. The front-end device of the brain-computer interface further comprises a digital-to-analog conversion module 5 and a power module 6; the digital-to-analog conversion module 5 is connected with the control chip 1; the power module 6 is connected with the control chip 1 and the digital-to-analog conversion module 5; the power module 6 is used for supplying power to the control chip 1 and the digital-to-analog conversion module 5; the power module 6 comprises a lithium battery, a first low dropout linear regulator and a second low dropout linear regulator; the lithium battery is connected with the control chip 1 through the first low dropout linear regulator; the lithium battery is connected with the digital-to-analog conversion module 5 through the second low dropout linear regulator; the digital-to-analog conversion module 5 is used for receiving the electroencephalogram signals sent by the control chip 1 and performing digital-to-analog conversion processing on the electroencephalogram signals. The lithium battery can ensure the precision of the electric signal, has small noise and can supply power for some sensitive power supplies, for example, part of devices (corresponding pins) in the control chip 1 and part of devices (corresponding pins) in the digital-to-analog conversion module 5, and because the actual electroencephalogram signal is very weak, the actual electroencephalogram signal is only dozens of muV to several mV, and is seriously influenced by noise, the requirement on the noise is very high.
In general, for low density electrodes, area and power constraints can be relaxed, signal amplification and analog-to-digital conversion can be performed on-chip, and the resulting digital data flows to the acquisition board through a serial peripheral interface. However, when the high-density electroencephalogram device is applied, in order to prevent brain tissue damage in the recording process, the area and power of the implant in the brain are greatly limited. Therefore, for the high-flux electrode, a series of processes such as amplification of the neural signal cannot be integrated on the electrode single plate like the existing low-flux active device, an additional PCB is needed, a neural signal amplification chip is integrated on the plate, and then the off-chip conversion is performed by matching with an ADC circuit and the like. However, the current chip integrated on the external circuit board can only realize 32-site flux, and the flux is low.
The control chip in the present application may be MOKOTO, and the brain-computer interface front-end device provided in the present application will be described in detail below by taking the control chip as MOKOTO as an example.
The MOKOTO may include 128 × 128 pixel circuits, and the control chip 11 includes four signal control lines, each signal control line controls one sub-control line on the north and south sides, and each sub-control line is connected with 128 pixel circuits in parallel, so that a maximum of 4 × 2 × 128 — 1024 stimulation channels can be realized by only 4 signal inputs. That is, based on the chip structure that the pixel circuits are respectively disposed on the north and south sides, in order to improve the data conversion efficiency, the digital-to-analog conversion module 5 may include two sub-modules, and one sub-module may be disposed near both the north and south sides of the control chip 1.
Correspondingly, the pad structure 22 includes 128 × 128 pads; the pad area comprises 128 × 128 pads, that is, when the control chip 1 is a MOKOTO chip, the brain electrode structure 1 is a 2640-channel device, and the pad structure 22 of the brain electrode structure 1 is a 30 × 88 pad array; the distance between adjacent welding points is 200 micrometers, and the distance between adjacent pixel circuit units in the MOKOTO chip is 100 micrometers, so that when the distance between the adjacent welding points and the distance between adjacent pixel circuit units in the MOKOTO chip are in flip chip bonding, the integration level can be improved, and the signal quality is ensured; since the distance between the adjacent pads of the brain electrode structure 1 is twice the distance between the adjacent pixel units, the adjacent pads can be connected to the spaced pixel units, so that the number of pads that can be connected to the pixel unit of the MOKOTO is 30 × 64, and since only 8 rows of the MOKOTO chip have corresponding signal lines, only 30 × 8 — 240 channels can be used for the stimulation portion. However, by adjusting the distance between the welding points, the number of corresponding channels can also be changed, which is merely an example of an alternative embodiment.
It should be noted that the number of channels of the control chip may be L times that of 64 channels, where L may be an integer greater than or equal to 2, for example, 64 channels, 128 channels, 256 channels, and the like, and the number of channels of the control chip 1 is mainly 128 × 128 in this embodiment.
Optionally, the acquisition rate of each channel of the control chip 1 is greater than or equal to 40 frames/second, and by multiplexing in the chip, 16 outputs are provided on each side of north and south sides, so that the sampling rate of each output channel is required to be not lower than 128 × 64 × 40/16 — 20.48Msample/s, and furthermore, in order to make the quantization noise far lower than the thermal noise floor, at least 12 bits of resolution of the dac module 5 are required, so that the data transmission rate of the whole chip is not lower than 12 bits × 20.48M × 16 × 2 — 7.86 gbit/s.
In an alternative embodiment, referring to fig. 2, the front-end device of the brain-computer interface further includes a Field Programmable Gate Array (FPGA) chip; the field programmable gate array chip 7 is connected with the control chip 1, the digital-to-analog conversion module 5, the test module 4 and the stimulation module 3; the field programmable gate array chip 7 is used for supplying power to the test module 4 and the stimulation module 3 and sending the received electroencephalogram signals sent by the digital-to-analog converter to the signal acquisition equipment.
Optionally, the voltage of the field programmable gate array chip 7 includes 5 volts, and the field programmable gate array chip 7 may provide power for devices with low accuracy requirements on power supply signals, and is connected with different low dropout linear voltage regulators through the field programmable gate array chip, so that different voltages can be output.
Optionally, the fpga chip 7 may supply power to the digital-to-analog conversion module 5, the stimulation module 3, and the following modules of the control chip 1, where the pins of the digital-to-analog conversion module 5 have DVDD _ TI _ ADC (1.2V), TI _ ADC (1.8V), and MISC (3.3V), the pins of the stimulation module 3 have VREF (3.5V), and the pins of the control chip 1 have VDDIO (3.3V), and VDDD (3.3V); it should be noted that VDDIO and VDDD are pins for supplying power to the control chip 1, VREF is power for the chip in the stimulus module 3 that needs to generate a reference voltage of 3.3V, and since the level range output by the control chip 1 is about 0-3.3V, and the input signal of the digital-to-analog conversion module 5 is required to be about 0-1.8V, and level conversion is needed, the MISC supplies power to the level conversion module located in the digital-to-analog conversion module 5.
In an alternative embodiment, the voltage of the lithium battery comprises 3.7 volts; the voltage range output by the first low dropout regulator comprises 0.5-3.3V; the voltage output by the second low dropout regulator comprises 1-1.8V.
Alternatively, the test result signal output by the control chip 1 may be input via the MBS _ N MBS _ S of the test module 4.
In order to realize a high-precision stimulation signal, in an alternative embodiment, the stimulation module 3 may be a chip, the resolution of the chip is 12 bits, the DNL has only 0.5LSB, the stimulation voltage range output by the stimulation module 3 is 0-3.3 volts, and the error range between the stimulation voltage value output by the stimulation module 3 and the preset voltage value is 0-0.4 mv. The high-precision voltage stimulation device has extremely high precision, and needs a grounding switch besides high-precision voltage stimulation, and is used for conducting grounding after each stimulation period is finished, and releasing unbalanced charges accumulated due to impedance change, power supply mismatching and the like in time, so that long-term cyclic stimulation can be carried out, the electrode voltage is kept within a safety threshold, and irreversible damage to tissue due to charge accumulation is avoided.
According to the above example, the design of the brain-computer interface front-end device provided by the application can provide a good solution for the acquisition and processing of high-flux electroencephalogram signals, and the amplification, filtering, analog-to-digital conversion and stimulation of the signals are integrated on an external PCB, so that the processing and conversion of high-flux electroencephalogram signals are realized; the signal amplification and filtering chip and the analog-to-digital conversion and stimulation module 3 are integrated at the front end of the same neural record and are separated from the probe, so that the pressure in the aspects of noise, power and area of the implant is relieved, and the damage influence on a living body detection object can be reduced to the greatest extent; meanwhile, simultaneous stimulation of 1024 channels at most can be realized, the resolution is as high as 12 bits, and the grounding short circuit is controlled by matching with a switch so as to release accumulated charges in a stimulation gap and realize stimulation charge balance. By matching the device with the brain electrode structure 2, the electrical activity of neurons and the change of nerve molecules in physiological and pathological processes can be accurately recorded, so that how the brain circuit operates and possible dysfunction in diseases can be decoded, the stimulation function is assisted, the stimulation parameters are fed back and adjusted according to the detected result, and early dispute and nerve regulation treatment of brain diseases such as Parkinson, epilepsy and the like are matched.
In an alternative embodiment, the brain electrode structure 2 includes a contact electrode structure 21 connected to the pad structure 22; the contact electrode structure 21 realizes the acquisition of electroencephalogram signals through the contact with the scalp.
In an alternative embodiment, the contact electrode structure 21 includes N contact electrodes; n is an integer greater than or equal to 1; the pad structure 22 includes N pads; the control chip 1 comprises a processor and N pixel circuits which are connected; the pixel circuits are connected with the N welding spots in a one-to-one corresponding mode; the processor is used for controlling the on or off of any one of the N contact electrodes by controlling the on or off of any one of the N pixel circuits; and when any one of the pixel circuits is conducted, the processor controls any one of the pixel circuits to output a corresponding stimulation signal or test signal through the received stimulation signal or test signal, and further realizes the stimulation of any one of the contact electrodes to the target cerebral cortex brain or the control of the corresponding pixel circuit test.
In an alternative embodiment, the contact electrode structure includes M sub-contact electrode structures, where M is an integer greater than or equal to 1; a preset interval exists between adjacent sub-contact electrode structures in the M sub-contact electrode structures; the M sub-contact electrode structures are located on the same plane. The N contact electrodes may be uniformly distributed on the M sub-contact electrode structures, or may be non-uniformly distributed as needed, which is not limited herein.
It should be noted that, in order to implement isolation and protection for adjacent sub-control lines, a separation circuit is further provided between adjacent sub-control lines, the above-mentioned N pixel circuits are not necessarily all pads of the control chip, but correspond to N contact electrodes, and actually, the control chip may include M pixel circuits, where M is an integer greater than N.
In a possible embodiment, referring to fig. 3, fig. 3 is a schematic structural diagram of an alternative pixel circuit according to the present application. Each pixel circuit comprises a first capacitor C1, a first switch S1, a second switch S2 and a third switchA switch S3 and a fourth switch S4, wherein a first terminal of the first capacitor C1 is connected to a signal input line V0, a second terminal of the first capacitor C1 is connected to a first terminal of the second switch S2, a first terminal of the first switch S1 is connected to a second terminal of the first capacitor C1, a second terminal of the first switch S1 is connected to the signal input line V0, the signal input line V0 is connected to the processor, a second terminal of the second switch S2 is connected to a first terminal of the third switch S3, and a third terminal of the second switch S2 is connected to a transverse control signal line S3 X[n] Connection of the transverse control signal line S X[n] Is connected with the processor; the second terminal of the third switch S3 is connected to the first terminal of the fourth switch S4, and the third terminal of the third switch S3 is connected to the vertical control signal line S Y[m] Connection of the longitudinal control signal line S Y[m] Is connected with the processor; the first terminal of the fourth switch S4 is connected to an output port, the output port is connected to a corresponding pad, and the second terminal of the fourth switch S4 is connected to the test signal processing circuit. The first switch S1 realizes outputting the stimulation signal or the test signal to the corresponding contact electrode through the cooperation with the fourth switch S4; the processor inputs a stimulus signal or a test signal to the pixel circuit through the signal input line V0; the processor passes through the transverse control signal line S X[n] Controlling the second switch S2 to be turned on or off; the processor passes through the longitudinal control signal line S Y[m] Controlling the third switch S3 to open or close.
Alternatively, the two selection signal lines, i.e., the transverse control signal line S X[n] And a longitudinal control signal line S Y[m] Controlled by a register in the processor so that a pixel circuit to be operated can be selected from 128 × 128 pixel circuits, i.e., the above-described lateral control signal line S can be used X[n] And a longitudinal control signal line S Y[m] To select the number of stimulation channels desired to be achieved, to achieve a selection of adjustable stimulation channels, S in FIG. 3 X[n] Represents the nth row of transverse control signal lines; s Y[m] The mth column of vertical control signal lines is shown.
Alternatively, the first switch S1 and the fourth switch S4 may be controlled to be turned on or off based on a user operation, and since the first switch S1 and the fourth switch S4 are turned on and off to form different control signals, when the first switch S1 and the fourth switch S4 are turned on, a "0" may be output, so that the processor controls a voltage signal externally input to the signal input line V0 to flow to the output port as a stimulation signal, and further reach the contact electrode; in contrast, if "1" is output when the first switch S1 and the fourth switch S4 are closed, the processor controls the voltage signal externally input to the signal input line V0 to flow to the amplifying circuit as a test signal, and finally to be output to an externally connected signal analyzing device through the other I/O port of the chip to observe the signal.
It should be noted that the above and below test signals refer to that when the control chip receives a test signal, the control chip tests a target pixel circuit to determine whether the pixel circuit can normally operate, and the test signals can be determined according to different test result signals output by the control chip; in most cases, the control chip mainly collects electroencephalogram signals of a target brain. Outputting the acquired brain electrical signals can be realized by controlling to close the fourth switch S4.
Of course, the first switch S1 and the fourth switch S4 may be controlled by the processor based on an external trigger signal.
Similarly, other switches in the pixel circuit, such as the second switch S2, the third switch S3, and the following fifth switch S5, can be controlled in the above two ways, which is not limited herein.
In a possible embodiment, referring to fig. 4, fig. 4 is a schematic structural diagram of an alternative pixel circuit according to the present application. To realize more stimulation types, the analysis of nerve signals under diversified stimulation is satisfied. Each pixel circuit further includes a second capacitor C2 and a fifth switch S5; a first end of the second capacitor C2 is connected to a first end of the fourth switch S4, and a second end of the second capacitor C2 is connected to the corresponding pad; a first terminal of the fifth switch S5 is connected to the first terminal of the capacitor, and a second terminal of the fifth switch S5 is connected to the second terminal of the capacitor; the processor controls the pixel circuit to output a direct current or an alternating current by controlling the opening or closing of the fifth switch S5. That is, whether the second capacitor C2 is short-circuited or not can be controlled by controlling the on or off of the fifth switch S5, and it can be set that when the fifth switch S5 is off, 0 is output, ac is input to the signal input line V0, otherwise, when the fifth switch S5 is on, 1 is output, short-circuited to the second capacitor C2, and dc is input to the signal input line V0.
Optionally, referring to fig. 5, fig. 5 is a schematic structural diagram of an optional parallel pixel circuit according to the present application. FIG. 5 shows two parallel pixel circuits belonging to the same row, so that the signal line S can be controlled by the same horizontal line X[n] Connected, the longitudinal control signal line of the first pixel circuit is S Y[m] The vertical control signal line of the second pixel circuit is S Y[m+1] . When a plurality of pixel units are connected in parallel, the analogy is carried out in sequence, and the analogy comprises that a plurality of longitudinal control signal lines S Y[m] A controlled pixel cell.
In a possible embodiment, the contact electrode structure 21 further includes a flexible substrate and an insulating layer, N contact electrodes are disposed on the flexible substrate, the insulating layer is disposed on the N contact electrodes, the insulating layer includes N electrode holes, and the N electrode holes correspond to the N contact electrodes one to one.
It should be noted that, when different pixel circuits correspond to contact electrodes arranged in different ways, since the areas of the contact electrodes in the brain tissue and the distances from the contact electrodes to the brain tissue may be different, the area of the stimulated tissue, the number of stimulation channels, the stimulation form, the stimulation intensity, and the like may be affected by adjusting the corresponding relationship between the contact electrodes and the pixel circuits; for example, when the contact electrode is located at a relatively large distance from the corresponding site of the brain tissue, the intensity of the stimulation voltage/current needs to be increased in order to achieve the required stimulation energy, and conversely, the intensity of the stimulation voltage/current needs to be decreased.
In order to realize charge balance, the complexity of an external integrated circuit is reduced, and the circuit area is reduced. In one possible embodiment, referring to fig. 6, fig. 6 is a schematic layout diagram of a first alternative contact electrode of the present application. The top of the flexible substrate includes a first side and a second side opposite to each other, the M first contact electrodes 211 are located on the first side, the M second contact electrodes 212 are located on the second side, and a second preset distance exists between adjacent first contact electrodes 211; the second predetermined distance is greater than or equal to the first predetermined distance, and the second predetermined distance exists between the adjacent second contact electrodes 212. The first contact electrode 211 inputs a first stimulation signal subsequently, the second contact electrode 212 inputs a second stimulation signal, and the first stimulation signal and the second stimulation signal are signals with equal amplitude, phase and shape, so as to realize charge balance in the corresponding brain tissue region.
It should be noted that the first stimulation signal and the second stimulation signal are not instantaneous signals, but signals with equal amplitude, phase and shape formed in a short time; the signals formed at times t1 and t2 below are also signals of equal amplitude, phase and shape.
The principle of achieving charge balance based on the contact electrode structure 21 in fig. 6 will be explained below:
the contact electrode structure 21 in fig. 6 comprises 24 pairs of contact electrodes, each contact electrode comprising a first contact electrode 211 on a first side and a second contact electrode 212 on a second side; it should be understood that when the contact electrode receives the stimulation signal, the brain tissue contacted by the contact electrode is injected with electric charges, and thus the peripheral potential is changed. Assuming that at time t0, the first signal input line V1 connected to the first contact electrode 211 and the second signal input line V2 connected to the second contact electrode 212 are both free from voltage signal input, the potential of the tissue contacting the contact electrodes is equal everywhere, and is in a relatively balanced state. Referring to fig. 7, fig. 7 is a model diagram of the potential distribution of the contact electrode structure at time t 1. When the first signal input line V1 inputs a signal having an amplitude of "1" and the second signal input line V2 inputs a signal having an amplitude of "0" at time t1, the first contact electrode 211 on the first side is brought into a high potential due to the injected charges, the second contact electrode 212 on the second side is brought into a relatively low potential, and the adjacent first and second contact electrodes 211 and 212 are brought into contact with each otherThe two contact electrodes 212 are located to form a potential difference, and thus have I sti Flows from the first contact electrode 211 to the second contact electrode 212 as shown in fig. 7. Referring to fig. 8, fig. 8 is a model diagram of the potential distribution of the contact electrode structure at time t 2. At time t2, the first signal input line V1 receives a signal of "0" in amplitude, the second signal input line V2 receives a signal of "1" in amplitude, the first contact electrode 211 on the first side is at a low potential, the second contact electrode 212 on the second side is at a high potential, and I sti From the second contact electrode 212 to the first contact electrode 211. Since the first contact electrode 211 and the second contact electrode 212 paired with each other are actually very close to each other, the current formed by the potential difference can be considered to flow only between the two electrodes and hardly diffuse outward, and an equivalent schematic diagram of a loop formed by the first contact electrode 211-tissue-second contact electrode 212 is shown in fig. 9, where fig. 9 is an alternative equivalent circuit diagram of the present application in a working state when the contact electrodes are inserted into brain tissue. In a very short time, it can be considered that I with equal and opposite directions is generated at the time t1 and the time t2 sti Therefore, after time t2, the charges injected into the brain tissue by the stimulation are cancelled out, and the charge balance is achieved. The stimulation is alternately input through the two signal lines, so that the charge balance problem is solved, the brain tissue damage and the electrode electrolysis are avoided, the integration level is improved, and the external circuit is simplified.
In fig. 9, Re is the contact electrode resistance, R and Ci are the equivalent resistance and capacitance in the brain tissue, respectively, and Rs is the resistance existing between the two contact electrode paths.
In one possible embodiment, referring to fig. 10, fig. 10 is a schematic diagram of a second alternative contact electrode arrangement of the present application. The N contact electrodes forming a set of contact electrodes, the set of contact electrodes comprising a first set of contact electrodes and a second set of contact electrodes, the first contact electrode set is located at the first side, the second contact electrode set is located at the second side, the first contact electrodes 211 and the second contact electrodes 212 in the first contact electrode set are staggered along the length direction of the flexible substrate, the sum of the number of first contact electrodes 211 and the number of second contact electrodes 212 in the first set of contact electrodes is equal to M, the first contact electrodes 211 and the second contact electrodes 212 in the second contact electrode set are staggered along the length direction of the flexible substrate, the sum of the number of the first contact electrodes 211 and the number of the second contact electrodes 212 in the second contact electrodes 212 is equal to M, the contact electrodes of the first contact electrode set are arranged in the same manner as the contact electrodes of the second contact electrode 212.
In another possible embodiment, referring to fig. 11, fig. 11 is a schematic diagram of a third alternative contact electrode arrangement of the present application. The contact electrodes of the first contact electrode set are arranged in a manner opposite to the arrangement of the contact electrodes of the second contact electrode 212.
In addition, when the electroencephalogram module stimulates brain tissues, the voltage control mode can be selected, and balanced bidirectional voltage pulses can be generated by an external circuit and input to the signal input line V0 to realize charge-balanced electrical stimulation, so that 1024-channel stimulation with 4 different stimulation waveforms can be realized.
In one possible embodiment, the signal input line V0 includes 3 sub-signal input lines V0, and the phase difference between adjacent sub-signal input lines V0 arranged along a predetermined direction is 120 degrees. That is, when the positions of the electrodes controlled by the three signal lines to stimulate form an angle of just 120 ° and the external three signal input ports give the initial stimulation with a phase difference of 120 °, it is possible to form autonomous power generation, i.e., to continue the signals by means of the phase difference without supplying the stimulation signals from the external voltage generator. The same principle can be used for forming a phase difference of 90 degrees by using four signal wires to form a four-phase generator, which is an excellent development point in the future wireless, sustainable and energy-saving design.
In summary, in the brain electrode module provided by the present application, the control chip 1 includes a plurality of pixel circuits corresponding to the plurality of contact electrodes of the brain electrode structure 1, so that different stimulation channels can be controlled to be turned on, stimulation of adjustable sites can be realized, configurable bipolar voltage stimulation can be used to realize charge balance, complexity of an external integrated circuit can be reduced, and circuit area can be reduced; while the optional dc/ac stimulation can be adapted to the specific experimental scenario. This application has not only realized the high channel stimulation, further compensatied the amazing blank of high channel in the market, can also adapt to the change of the different demands in biomedical field, possesses higher flexibility, has reduced the research and development cost, has shortened the experimental period.
The application also discloses a brain electrode system which comprises the brain electrode structure 2 and the brain-computer interface front-end device. See in particular the description above.
In consideration of crosstalk existing among signals of ten thousand orders of magnitude and high requirements on noise quality, an active circuit is not integrated on a contact electrode of the brain electrode structure 2, the active circuit is only responsible for collection and transmission of brain electrical signals, a control chip 1 is additionally used for amplifying and filtering the collected ten thousand signals, the processed signals are multiplexed at the north and south ends of a brain electrical signal processing chip and are respectively output through 16I/O ports, a circuit on a PCB is transmitted to a field programmable gate array chip 7 through a series of conversion in an SPI mode for integrated control of data, and finally the field programmable gate array chip 7 transmits the signals to a client through a ten thousand megabits cable for visual processing. Based on the brain electrode system, the functions of acquisition, stimulation and test can be realized, and high-flux signal transmission can be realized.
Referring to fig. 12, fig. 12 is a flowchart illustrating an alternative method for controlling the electroencephalograph of the present application. The present application also discloses a control method of a brain electrode system, which is applied to the brain electrode module, the control method comprising the following steps:
s1101: and acquiring a site control signal.
S1102: and controlling the opening of the pixel circuit of the corresponding position based on the position control signal.
Referring to the above description, the signal line S can be controlled by controlling the several rows of the transverse control signal line S X[n] And the longitudinal control signal line S of the second column Y[m] Accordingly, the corresponding second switch S2 and the third switch S3 may be controlled to be turned on and off to achieve overall conduction of the corresponding pixel circuit.
S1103: a function control signal is received.
Alternatively, the functional control signal may include two kinds, one is a control signal for controlling the pixel circuit to output the stimulus/test signal; the other is a control signal for controlling the pixel circuit to output dc/ac.
S1104: and controlling the pixel circuit to output a stimulation signal or a test signal based on the function control signal so as to stimulate the contact electrode to a target brain or control the corresponding pixel circuit.
Referring to the above description, the stimulation signal or the test signal may be inputted through the signals generated by the received opening and closing of the first switch S1 and the fourth switch S4, and then inputted into the brain tissue through the output port when the stimulation signal is received, and inputted into the amplifying circuit when the test signal is received.
Determining whether the stimulus signal input into the pixel circuit is ac or dc can also be achieved by controlling the opening or closing of the fifth switch S5. The specific implementation is described in detail in the above description, and is not described in detail herein.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A brain-computer interface front-end device is characterized by comprising a control chip (1), a stimulation module (3) and a test module (4);
the stimulation module (3) and the test module (4) are respectively connected with the control chip (1);
the pad area of the control chip (1) is correspondingly connected with the pad structure (22) of the brain electrode structure (2);
the stimulation module (3) is used for generating a stimulation signal which is used for stimulating the cerebral cortex through the brain electrode structure (2);
the control chip (1) is used for performing on-off control on a channel of the brain electrode structure (2) and switching input of a test signal and the stimulation signal;
the test module (4) is used for receiving the test result signal sent by the control chip (1) and carrying out digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the control chip (1) based on the test signal.
2. The brain-computer interface front-end device according to claim 1, further comprising a digital-to-analog conversion module (5) and a power supply module (6);
the digital-to-analog conversion module (5) is connected with the control chip (1);
the power supply module (6) is connected with the control chip (1) and the digital-to-analog conversion module (5);
the power supply module (6) is used for supplying power to the control chip (1) and the digital-to-analog conversion module (5);
the power supply module (6) comprises a lithium battery, a first low dropout linear regulator and a second low dropout linear regulator;
the lithium battery is connected with the control chip (1) through the first low-dropout linear regulator;
the lithium battery is connected with the digital-to-analog conversion module (5) through the second low dropout linear regulator;
the digital-to-analog conversion module (5) is used for receiving the electroencephalogram signals sent by the control chip (1) and performing digital-to-analog conversion processing on the electroencephalogram signals.
3. The brain-computer interface front end device of claim 2, wherein the voltage of the lithium battery comprises 3.7 volts;
the voltage range output by the first low dropout regulator comprises 0.5-3.3V;
and the voltage output by the second low dropout regulator comprises 1-1.8V.
4. The brain-computer interface front-end device according to claim 1, wherein the channels of the control chip (1) include 128 x 128 channels;
the pad structure (22) comprises 128 x 128 pads;
the pad area comprises 128 x 128 welding spots;
the welding points of the welding pad structure (22) are correspondingly connected with the welding points of the welding pad area in a one-to-one mode through flip chip.
5. The brain-computer interface front end device according to claim 1, further comprising a Field Programmable Gate Array (FPGA) chip;
the field programmable gate array chip (7) is connected with the control chip (1), the digital-to-analog conversion module (5), the test module (4) and the stimulation module (3);
the field programmable gate array chip (7) is used for supplying power to the test module (4) and the stimulation module (3) and sending the received electroencephalogram signals sent by the digital-to-analog converter to a signal acquisition device;
the voltage of the field programmable gate array chip (7) comprises 5 volts.
6. The brain-computer interface front end device according to claim 1, wherein the stimulation voltage output by the stimulation module (3) is in the range of 0-3.3 volts;
the error range of the stimulation voltage value output by the stimulation module (3) and the preset voltage value is 0-0.4 millivolt.
7. The brain-computer interface front end device according to claim 1, wherein the brain electrode structure (2) includes a contact electrode structure (21) connected to the pad structure (22);
the contact electrode structure (21) realizes the acquisition of electroencephalogram signals through the contact with the scalp.
8. The brain-computer interface front end device according to claim 7, wherein the contact electrode structure (21) comprises N contact electrodes; n is an integer greater than or equal to 1;
the pad structure (22) comprises N welding points;
the control chip (1) comprises a processor and N pixel circuits which are connected; the pixel circuits are connected with the N welding spots in a one-to-one corresponding mode;
the processor is used for controlling the on or off of any one of the N contact electrodes by controlling the on or off of any one of the N pixel circuits; and when any one of the pixel circuits is conducted, the processor controls any one of the pixel circuits to output a corresponding stimulation signal or test signal through the received stimulation signal or test signal, and further realizes the stimulation of any one of the contact electrodes to the target cerebral cortex brain or the control of the corresponding pixel circuit test.
9. The brain-computer interface front end device according to claim 7, wherein the contact electrode structure (21) comprises M sub-contact electrode structures (21), wherein M is an integer greater than or equal to 1;
a preset interval exists between adjacent sub-contact electrode structures (21) in the M sub-contact electrode structures (21);
the M sub-contact electrode structures (21) are located on the same plane.
10. A brain electrode system comprising the brain electrode structure (2) and the brain-computer interface front-end device according to any one of claims 1 to 9.
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