CN114793053A

CN114793053A - Switching converter circuit and driving circuit with adaptive dead time

Info

Publication number: CN114793053A
Application number: CN202110897436.5A
Authority: CN
Inventors: 廖庭维; 陈建馀; 游焜煌; 邱建维; 杨大勇
Original assignee: Richtek Technology Corp
Current assignee: Richtek Technology Corp
Priority date: 2021-01-25
Filing date: 2021-08-05
Publication date: 2022-07-26
Also published as: TW202230943A; TWI764792B

Abstract

A switching converter circuit and a driving circuit having an adaptive dead time therein. The switching converter circuit is used for switching the voltage of one end of the inductor according to the pulse width modulation signal so as to convert the input voltage into the output voltage. The switched-mode converter circuit has a drive circuit including an upper bridge driver, a lower bridge driver, an upper bridge sense circuit, and a lower bridge sense circuit. The upper bridge sensing circuit is used for sensing the grid-source voltage of the upper bridge metal oxide semiconductor field effect transistor and generating a lower bridge enabling signal so as to enable the lower bridge driver to switch the lower bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal. The lower bridge sensing circuit is used for sensing the grid-source voltage of the lower bridge metal oxide semiconductor field effect transistor and generating an upper bridge enabling signal so as to enable the upper bridge driver to switch the upper bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal.

Description

Switching converter circuit and driving circuit with adaptive dead time therein

Technical Field

The present invention relates to a switching converter circuit, and more particularly, to a switching converter circuit with adaptive dead time and capable of avoiding short-circuit current. The invention also relates to a driver circuit in a switched-mode converter circuit.

Background

Fig. 1A shows a circuit diagram of a prior art switching converter circuit 10. The switching converter circuit 10 includes a driving circuit 11 and a power stage circuit 12. As shown, the power stage circuit 12 includes an upper bridge switch 121, a lower bridge switch 122, and an inductor 123. The driving circuit 11 generates an upper bridge signal UG and a lower bridge signal LG according to a Pulse Width Modulation (PWM) signal P1. The upper switch 121 and the lower switch 122 operate according to the upper signal UG and the lower signal LG, respectively, to convert the input voltage Vin into the output voltage Vout and generate the inductor current IL flowing through the inductor 123 of the power stage circuit 12.

In the switching converter circuit 10 shown in fig. 1A, the power stage circuit 12 is a buck power stage circuit. During normal operation, the upper bridge switch 121 and the lower bridge switch 122 are turned on alternately to switch the end of the inductor 123 electrically connected to the phase node LX between the input voltage Vin and the ground potential GND, so that the inductor current IL is alternately switched between the following two current paths: firstly, an input voltage Vin flows through the upper bridge switch 121 to the phase node LX and then flows through the inductor L to the output end; the other is from the ground potential GND through the lower switch 122 to the phase node LX and through the inductor L to the output terminal. In normal operation, the upper bridge switch 121 and the lower bridge switch 122 must be prevented from being turned on simultaneously to avoid circuit breakdown (shoot through), which may cause circuit damage. Therefore, dead time (dead time) is required to separate the conduction periods of the upper and

lower bridge switches

121 and 122 in which neither of the upper and

lower bridge switches

121 and 122 is conductive.

Fig. 1B shows a circuit diagram of a driving circuit 11 in the prior art. As shown in fig. 1B, the driving circuit 11 includes latch circuits 111 and 112, a level shift circuit 113, an inverter 114,

delay circuits

115 and 116, and other inverters. The PWM signal P1 is used as a reset signal of the latch circuit 111, when the PWM signal P1 is low, the latch circuit 111 outputs high voltage, and after passing through the level shift circuit 113 and then through 3 inverters, the generated upper bridge signal UG is low voltage, and the upper bridge switch 121 is not turned on. When the PWM signal P1 goes high, it is necessary to determine whether to turn the upper bridge signal UG high according to the output signal of the delay circuit 116, so as to turn on the upper bridge switch 121.

On the other hand, the PWM signal P1 passes through the inverter 114, the inverted signal thereof serves as the reset signal of the latch circuit 112, when the PWM signal P1 is high, the latch circuit 112 outputs high, and the generated lower bridge signal LG passes through 3 inverters to be low, without turning on the lower bridge switch 122. When the PWM signal P1 turns to low, it is necessary to determine whether to turn the lower bridge signal LG to high according to the output signal of the delay circuit 115, so as to turn on the upper bridge switch 121.

The output signal of the latch circuit 111 is delayed by the delay circuit 115 for a predetermined upper-bridge delay time, and then is inputted to the latch circuit 112 as a setting signal of the latch circuit 112, so that the latch circuit 112 can generate the lower-bridge signal LG according to the inverted signal of the PWM signal P1. On the other hand, the output signal of the latch circuit 112 is delayed by a predetermined delay time of the next bridge by the delay circuit 116, and then is input to the latch circuit 111 as a setting signal of the latch circuit 111, so that the latch circuit 111 generates the up-bridge signal UG according to the PWM signal P1.

The upper bridge delay time must be long enough to cover the dead time after the upper bridge switch 121 finishes conducting; and the pull-down delay time must be long enough to cover the dead time after the pull-down switch 122 finishes conducting, so as to avoid the simultaneous conduction of the pull-up switch 121 and the pull-down switch 122. The driving circuit 11 generates a bootstrap voltage BOOT according to the dc voltage VCC. The level shift circuit 113 level-shifts (level shift) the PWM signal P1 having passed through the latch circuit 111 to a boot voltage domain.

Referring to fig. 1A, in the normal operation of the switching converter circuit 10, the dead time is a fixed predetermined period. After the lower bridge switch 122 is turned on, the upper bridge switch 121 is turned on after a fixed dead time, and after the dead time, the parasitic diode LD in the lower bridge switch 122 is converted from forward bias to reverse bias. During another dead time, after the upper bridge switch 121 is turned on and before the lower bridge switch 122 is turned on, the parasitic diode LD in the lower bridge switch 122 is switched from the reverse bias to the forward bias, and during the dead time, the inductor current IL flows through the parasitic diode LD in the lower bridge switch 122 from the ground potential GND to the phase node LX and then flows through the inductor L. That is, in one switching cycle of the upper bridge switch 121 and the lower bridge switch 122, during the two dead times, the PN interface of the parasitic diode LD in the lower bridge switch 122 has two bias voltage inversions, resulting in the loss of power and time of reverse recovery charge (Qrr).

In normal operation of the prior art switching converter circuit 10, the dead time must be preset to a fixed time long enough to meet the different dead time requirements caused by the errors of the electronic components and circuits in the switching converter circuit 10 in various manufacturing processes. That is, the dead time must be preset to exceed the maximum value among the requirements of different dead times due to various errors, so as to prevent the upper switch 121 and the lower switch 122 from being turned on simultaneously. As a result, for most of the switching converter circuits 10 requiring only a short dead time, the excessive dead time will result in a severe power and time loss of the reverse recovery charge and a severe power loss of the forward conduction, thereby resulting in a relatively low conversion efficiency.

Compared with the prior art, the switching converter circuit with adaptive dead time and the driving circuit thereof provided by the invention can avoid short-circuit current caused by the simultaneous conduction of the upper bridge switch and the lower bridge switch, and reduce the electric energy loss of reverse recovery charge and forward conduction so as to improve the conversion efficiency.

Disclosure of Invention

In one aspect, the present invention provides a switching converter circuit for switching a first terminal of an inductor between a first voltage and a second voltage according to a Pulse Width Modulation (PWM) signal to convert an input voltage into an output voltage, the switching converter circuit comprising: a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) coupled between the first voltage and the first end of the inductor; a lower bridge MOSFET coupled between the second voltage and the first end of the inductor; and a driving circuit, comprising: an upper bridge driver for generating an upper bridge driving signal according to the PWM signal to drive the upper bridge MOSFET; a lower bridge driver for generating a lower bridge driving signal according to the PWM signal to drive the lower bridge MOSFET; an upper bridge sensing circuit for sensing a gate-source voltage of the upper bridge MOSFET and generating a lower bridge enable signal according to the gate-source voltage of the upper bridge MOSFET to indicate a non-conductive state of the upper bridge MOSFET, wherein the lower bridge enable signal enables the lower bridge driver to switch the lower bridge MOSFET according to the PWM signal; and a lower bridge sensing circuit for sensing a gate-source voltage of the lower bridge MOSFET and generating an upper bridge enable signal according to the gate-source voltage of the lower bridge MOSFET to indicate a non-conductive state of the lower bridge MOSFET, wherein the upper bridge enable signal enables the upper bridge driver and switches the upper bridge MOSFET according to the PWM signal.

From another perspective, the present invention also provides a driving circuit of a switching converter circuit, comprising: an upper bridge driver for generating an upper bridge driving signal according to a PWM signal to drive an upper bridge MOSFET; a lower bridge driver for generating a lower bridge driving signal according to the PWM signal to drive a lower bridge MOSFET; an upper bridge sensing circuit for sensing a gate-source voltage of the upper bridge MOSFET and generating a lower bridge enable signal according to the gate-source voltage of the upper bridge MOSFET to indicate a non-conductive state of the upper bridge MOSFET, wherein the lower bridge enable signal enables the lower bridge driver to switch the lower bridge MOSFET according to the PWM signal; and a lower bridge sensing circuit for sensing a gate-source voltage of the lower bridge MOSFET and generating an upper bridge enable signal according to the gate-source voltage of the lower bridge MOSFET to indicate a non-conductive state of the lower bridge MOSFET, wherein the upper bridge enable signal enables the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

In a preferred embodiment, the under bridge sense circuit includes a under bridge sense MOSFET having the same conductivity type as the under bridge MOSFET, and the gate of the under bridge sense MOSFET is coupled to the gate of the under bridge MOSFET and the source of the under bridge sense MOSFET is coupled to the source of the under bridge MOSFET such that the under bridge sense MOSFET generates the upper bridge enable signal at the drain of the under bridge sense MOSFET in accordance with the gate-source voltage of the under bridge MOSFET.

In a preferred embodiment, the lower bridge sense circuit further includes a current source coupled between the upper bridge enable signal and a bootstrap voltage (bootstrap) voltage of the upper bridge driver, so as to shift multiple logic levels of the upper bridge enable signal to a start voltage range (bootstrap voltage domain), wherein the upper bridge driver includes an enable logic circuit for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

In a preferred embodiment, the lower bridge sensing circuit further includes a current source coupled between the upper bridge enable signal and a dc voltage for generating a bootstrap voltage of the upper bridge driver, wherein the upper bridge driver includes an enable logic circuit and a level shift circuit coupled to each other for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

In a preferred embodiment, the lower bridge sensing circuit includes a lower bridge comparator for comparing the gate-source voltage of the lower bridge MOSFET with a lower bridge reference voltage to generate the upper bridge enable signal, wherein the upper bridge driver includes an enable logic circuit and a level shift circuit coupled to each other for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

In a preferred embodiment, an absolute value of a turn-on threshold voltage of an upper bridge sense MOSFET of the upper bridge sense circuit is lower than or equal to an absolute value of a turn-on threshold voltage of the upper bridge MOSFET, and an absolute value of a turn-on threshold voltage of the lower bridge sense MOSFET is lower than or equal to an absolute value of a turn-on threshold voltage of the lower bridge MOSFET.

In a preferred embodiment, the upper bridge sense circuit includes an upper bridge sense MOSFET having a conductivity type complementary to the upper bridge MOSFET, and the gate of the upper bridge sense MOSFET is coupled to the source of the upper bridge MOSFET and the source of the upper bridge sense MOSFET is coupled to the gate of the upper bridge MOSFET such that the upper bridge sense MOSFET generates the lower bridge enable signal at the drain of the upper bridge sense MOSFET in accordance with the gate-source voltage of the upper bridge MOSFET.

In a preferred embodiment, the upper bridge sensing circuit comprises: an upper bridge sense MOSFET having the same conductivity type as the upper bridge MOSFET; and an upper bridge clamp MOSFET of a conductivity type complementary to the upper bridge MOSFET, the upper bridge clamp MOSFET and the upper bridge sense MOSFET coupled in series to a bootstrap voltage of the upper bridge driver; the gate and the source of the upper bridge MOSFET are respectively coupled to the gate of the upper bridge sense MOSFET and the gate of the upper bridge clamp MOSFET, so that the upper bridge clamp MOSFET generates the lower bridge enable signal at the drain of the upper bridge clamp MOSFET according to the gate-source voltage of the upper bridge MOSFET.

In a preferred embodiment, the upper bridge sensing circuit comprises: an upper bridge sense MOSFET having a conductivity type complementary to the upper bridge MOSFET; and an upper bridge clamp MOSFET of a conductivity type complementary to the upper bridge MOSFET, the upper bridge clamp MOSFET and the upper bridge sense MOSFET coupled in series to a bootstrap voltage of the upper bridge driver; the gate and the source of the upper bridge MOSFET are respectively and correspondingly coupled to the gate of the upper bridge sense MOSFET and the gate of the upper bridge clamp MOSFET, so that the upper bridge clamp MOSFET generates the lower bridge enable signal at the drain of the upper bridge clamp MOSFET according to the gate-source voltage of the upper bridge MOSFET.

In a preferred embodiment, the upper bridge sensing circuit comprises: an upper bridge sense MOSFET, wherein the absolute value of the turn-on threshold voltage of the upper bridge sense MOSFET is lower than or equal to the absolute value of the turn-on threshold voltage of the upper bridge MOSFET, and the lower bridge sense circuit comprises a lower bridge sense MOSFET, wherein the absolute value of the turn-on threshold voltage of the lower bridge sense MOSFET is lower than or equal to the absolute value of the turn-on threshold voltage of the lower bridge MOSFET.

In a preferred embodiment, the upper bridge MOSFET has the same conductivity type as the lower bridge MOSFET.

The purpose, technical content, features and effects of the present invention will be more readily understood through the detailed description of the specific embodiments.

Drawings

Fig. 1A shows a schematic diagram of a prior art switching converter circuit 10.

Fig. 1B shows a circuit diagram of a driving circuit 11 of the prior art.

Fig. 2 shows a schematic diagram of a switched-mode converter circuit 20 according to the present invention.

Fig. 3 shows an embodiment of the driver circuit 21 according to the invention.

Fig. 4 shows an embodiment of the driving circuit 31 according to the invention.

Fig. 5 shows an embodiment of the driving circuit 41 according to the invention.

Fig. 6 shows an embodiment of the driving circuit 51 according to the invention.

Description of the symbols in the drawings

10, 20: switching converter circuit

11, 21, 31, 41, 51: driving circuit

12: power stage circuit

23: load circuit

111, 112: latch circuit

113: level shift circuit

114: inverter with a capacitor having a capacitor connected to a capacitor

115, 116: delay circuit

121: upper bridge switch

122: lower bridge switch

123: inductance

211, 311, 411, 511: upper bridge driver

212, 312, 412, 512: bridge sense circuit

213, 313, 413, 513: lower bridge driver

214, 314, 414, 514: lower bridge sensing circuit

221: upper bridge MOSFET

222: under bridge MOSFET

223: inductance

315, 415, 515, 516: level shift circuit

514: lower bridge comparator

2121, 3121, 4121: upper bridge sensing MOSFET

2122, 2142, 3122, 3142, 4122, 4142: current source

2141, 3141, 4141: lower bridge sensing MOSFET

3111, 3131, 4111, 4131, 5111, 5131: enable logic circuit

3123, 4123: upper bridge clamp MOSFET

5121: upper bridge comparator

BOOT: bootstrap voltage

ENH: upper bridge enable signal

ENL: lower bridge enable signal

GND: ground potential

IL: inductive current

LD: parasitic diode

LG: lower bridge signal

LX: phase node

P1: PWM signal

SH: upper bridge PWM signal

SL: lower bridge PWM signal

VCC: direct voltage

Vin: input voltage

Vout: output voltage

Vref 1: upper bridge reference voltage

Vref 2: lower bridge reference voltage

UG: go up bridge signal

Detailed Description

The drawings in the present disclosure are schematic and are intended to show the coupling relationship between circuits and the relationship between signal waveforms, and the circuits, signal waveforms and frequencies are not drawn to scale.

Fig. 2 shows a schematic diagram of a switched-mode converter circuit 20 according to the present invention. The switching converter circuit 20 is configured to switch a first terminal (in the embodiment, a terminal electrically connected to the phase node LX) of the inductor 223 between a first voltage (in the embodiment, the input voltage Vin) and a second voltage (in the embodiment, the ground potential GND) according to a Pulse Width Modulation (PWM) signal P1, so as to convert the input voltage Vin into the output voltage Vout and provide power to the load circuit 23. The switching converter circuit 20 includes: an upper bridge Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 221, a lower bridge MOSFET222, and a driving circuit 21.

In the present embodiment, the upper bridge MOSFET is coupled between the input voltage Vin and the phase node LX (the first end of the inductor). The lower bridge MOSFET is coupled between the ground potential GND and the phase node LX (the first end of the inductor). It should be noted that, in addition to the buck power stage circuit, the present invention can also be applied to the boost power stage circuit and the buck-boost power stage circuit, and as long as the power stage circuit has an upper bridge MOSFET and a lower bridge MOSFET, the present invention can be applied to improve the conversion efficiency and reduce the reverse recovery charge loss, only the contact point coupled to the first end of the inductor that is changed correspondingly is needed, and the contact point coupled to the upper bridge MOSFET and the lower bridge MOSFET that is changed is: input voltage, ground potential, phase node and output voltage.

The driving circuit 21 is configured to generate the up-bridge driving signal UG and the down-bridge driving signal LG according to the PWM signal P1 related to the feedback signal of the output voltage Vout, and correspondingly operate the up-bridge MOSFET221 and the down-bridge MOSFET222 to switch the first terminal of the inductor 223 between the first voltage (the input voltage Vin) and the second voltage (the ground potential GND). The drive circuit 21 includes: an upper bridge driver 211, a lower bridge driver 213, an upper bridge sense circuit 212, and a lower bridge sense circuit 214.

The upper bridge driver 211 is used for generating an upper bridge driving signal UG according to the PWM signal P1 to drive the upper bridge MOSFET 221. The under-bridge driver 213 is used for generating an under-bridge driving signal LG according to the PWM signal P1 to drive the under-bridge MOSFET 222. The upper bridge sensing circuit 212 is used for sensing the gate-source voltage of the upper bridge MOSFET221 and generating the lower bridge enable signal ENL to indicate the non-conductive state of the upper bridge MOSFET 221. The lower bridge enable signal ENL enables the lower bridge driver 213 to switch the lower bridge MOSFET222 according to the PWM signal P1. The lower bridge sensing circuit 214 is used for sensing the gate-source voltage of the lower bridge MOSFET222 to generate the upper bridge enable signal ENH to indicate the non-conductive state of the lower bridge MOSFET 222. Wherein the upper bridge enable signal ENH enables the upper bridge driver 211 to switch the upper bridge MOSFET221 according to the PWM signal P1.

Specifically, in the embodiment shown in fig. 2, the upper bridge MOSFET221 is, for example, an N-type MOSFET, the upper bridge sensing circuit 212 senses the gate-source voltage of the upper bridge MOSFET221, and when the absolute value of the gate-source voltage of the upper bridge MOSFET221 is higher than a first threshold voltage, that is, when the upper bridge MOSFET221 is turned on or close to being turned on, the upper bridge sensing circuit 212 changes the lower bridge enable signal ENL to the disable level, for example, to disable the lower bridge MOSFET222 from being turned on. In a preferred embodiment, the first threshold voltage is, for example, a positive value and is lower than or equal to the turn-on threshold voltage of the upper bridge MOSFET221, so as to ensure that the enable signal ENL changes to the disable level when the upper bridge MOSFET221 is turned on. Thus, it is ensured that the bottom bridge MOSFET222 is not turned on when the top bridge MOSFET221 is turned on. The turn-on threshold voltage of the upper bridge MOSFET221 is, for example, a positive value.

On the other hand, when the gate-source voltage of the upper bridge MOSFET221 is lower than the first threshold voltage, i.e. the upper bridge MOSFET221 is turned off, the upper bridge sensing circuit 212 changes the lower bridge enable signal ENL to the enable level, for example, to enable the lower bridge driver 213, and switches the lower bridge MOSFET222 according to the PWM signal P1.

Similarly, when the upper bridge MOSFET221 is a P-type MOSFET, the upper bridge sensing circuit 212 senses, for example, the gate-source voltage of the upper bridge MOSFET221, and when the absolute value of the gate-source voltage of the upper bridge MOSFET221 is higher than the first threshold voltage, i.e., when the upper bridge MOSFET221 is turned on or nearly turned on, the upper bridge sensing circuit 212 changes the lower bridge enable signal ENL to the high-potential-prohibition level to prohibit the lower bridge MOSFET222 from being turned on. Thus, it is ensured that the bottom bridge MOSFET222 is not conducted when the top bridge MOSFET221 is conducted. The upper bridge MOSFET221 is, for example, a P-type MOSFET, and the turn-on threshold voltage thereof is, for example, a negative value, and the first threshold voltage is equal to or less than the absolute value of the turn-on threshold voltage of the upper bridge MOSFET 221.

On the other hand, when the absolute value of the gate-source voltage of the upper bridge MOSFET221 is lower than the first threshold voltage, i.e. when the upper bridge MOSFET221 is turned off, the upper bridge sensing circuit 212 changes the lower bridge enable signal ENL to the enable level, for example, so as to enable the lower bridge driver 213 to switch the lower bridge MOSFET222 according to the PWM signal P1.

Referring to fig. 2, as shown in fig. 2, the lower bridge MOSFET222 is, for example, an N-type MOSFET, and the lower bridge sensing circuit 214 senses the gate-source voltage of the lower bridge MOSFET222, and when the absolute value of the gate-source voltage of the lower bridge MOSFET222 is higher than the second threshold voltage, i.e., the lower bridge MOSFET222 is turned on, the lower bridge sensing circuit 214 changes the upper bridge enable signal ENH to a high level, for example. In a preferred embodiment, the second threshold voltage is, for example, a positive value and is lower than or equal to the turn-on threshold voltage of the lower bridge MOSFET222, so as to ensure that the enable signal ENH changes to the disable level when the lower bridge MOSFET222 is turned on. Thus, it is ensured that the up-bridge MOSFET221 is not turned on when the down-bridge MOSFET222 is turned on. The turn-on threshold voltage of the lower bridge MOSFET222 is, for example, a positive value. In a preferred embodiment, the upper bridge MOSFET221 has the same conductivity type as the lower bridge MOSFET222, e.g., both N-type MOSFETs in FIG. 2.

On the other hand, when the gate-source voltage of the bottom bridge MOSFET222 is lower than the second threshold voltage, i.e. the bottom bridge MOSFET222 is not conductive, the bottom bridge sensing circuit 214 changes the top bridge enable signal ENH to the enable level, for example, to enable the top bridge driver 211 to switch the top bridge MOSFET221 according to the PWM signal P1. Similarly, when the bottom bridge MOSFET222 is a P-type MOSFET, the bottom bridge sensing circuit 214 senses, for example, the gate-source voltage of the bottom bridge MOSFET222, and when the absolute value of the gate-source voltage of the bottom bridge MOSFET222 is higher than the second threshold voltage, the bottom bridge sensing circuit 214 changes the top bridge enable signal ENH to the signal disable level. Thus, it is ensured that the upper bridge MOSFET221 is not turned on when the lower bridge MOSFET222 is turned on. The lower bridge MOSFET222 is, for example, a P-type MOSFET, and the turn-on threshold voltage thereof is, for example, a negative value, and the second threshold voltage is equal to or less than the absolute value of the turn-on threshold voltage of the lower bridge MOSFET 222. The actual levels of the enable level and the disable level may be configured according to the requirements of a specific circuit, as described in detail below.

In summary, the upper bridge sensing circuit 212 and the lower bridge sensing circuit 214 respectively sense the gate-source voltage of the upper bridge MOSFET221 and the gate-source voltage of the lower bridge MOSFET222, so as to enable the lower bridge driver 213 to switch the lower bridge MOSFET222 according to the PWM signal P1 and enable the upper bridge driver 211 to switch the upper bridge MOSFET221 according to the PWM signal P1 in real time when the upper bridge MOSFET221 and the lower bridge MOSFET222 are determined to be non-conductive. Thus, the switching converter circuit 10 in the prior art is not required to fix the upper bridge delay time and the lower bridge delay time too long to separate the conduction time of the upper bridge switch 121 and the lower bridge switch 122. Compared with the prior art, the invention can reduce the electric energy and time loss of reverse recovery charge and can also improve the conversion efficiency.

Fig. 3 shows an embodiment of the driving circuit 21 according to the invention. As shown in fig. 3, the drive circuit 21 includes: an upper bridge driver 211, an upper bridge sense circuit 212, a lower bridge driver 213, and a lower bridge sense circuit 214. The upper bridge sensing circuit 212 includes, for example, an upper bridge sensing MOSFET2121 and a current source 2122; the bottom bridge sensing circuit 214 includes a bottom bridge sensing MOSFET2141 and a current source 2142. The PWM signal P1 generates an upper bridge PWM signal SH through the buffer, wherein the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates the lower bridge PWM signal SL through an inverter, wherein the PWM signal P1 is inverted from the lower bridge PWM signal SL.

As shown in fig. 3, the lower bridge sense MOSFET2141 has the same conductivity type as the lower bridge MOSFET 222; the bottom bridge sense MOSFET2141 and the bottom bridge MOSFET222 are, for example, N-type MOSFETs. The gate of the bottom bridge sense MOSFET2141 is coupled to the gate of the bottom bridge MOSFET222, and the source of the bottom bridge sense MOSFET2141 is coupled to the source of the bottom bridge MOSFET 222. As shown in FIG. 3, the source of the bottom bridge sense MOSFET2141 and the source of the bottom bridge MOSFET222 are both electrically connected to the ground potential GND. In this way, the bottom bridge sense MOSFET2141 generates the top bridge enable signal ENH at the drain of the bottom bridge sense MOSFET2141 according to the gate-source voltage of the bottom bridge MOSFET 222.

Referring to fig. 3, the lower bridge sensing circuit 214 further includes a current source 2142 coupled between the upper bridge enable signal ENH and a bootstrap voltage BOOT of the upper bridge driver 21, so that the plurality of logic levels of the upper bridge enable signal ENH are shifted (level shift) to a start voltage range (BOOT voltage domain), so that the upper bridge driver 211 can determine whether the lower bridge MOSFET222 is turned off according to the upper bridge enable signal ENH. The upper bridge driver 211 comprises an enable logic circuit (e.g. a level-shift inverter formed by a P-type MOSFET and a current source, another inverter coupled thereto, and a nand gate shown in fig. 3) for receiving an upper bridge enable signal ENH to enable the upper bridge driver 211 to switch the upper bridge MOSFET221 according to the PWM signal P1.

As shown in fig. 3, the upper bridge driver 211 includes, for example, a P-type MOSFET, a nand gate as an enable logic circuit, a current source, and 2 inverters. The lower bridge driver 213 includes, for example, a nand gate and 2 inverters as an enable logic circuit.

For example, as shown in fig. 3, the turn-on threshold voltage of the lower bridge sense MOSFET2141 is equal to the second threshold voltage and lower than or equal to the turn-on threshold voltage of the lower bridge MOSFET 222. The bottom bridge sense MOSFET2141 is conductive, indicating that the bottom bridge MOSFET222 is conductive or nearly conductive, also indicating that the top bridge MOSFET221 should not be conductive. In this case, the lower bridge sense circuit 214 changes the upper bridge enable signal ENH to a disable level (low level in this embodiment) to disable the upper bridge PWM signal SH, so as to ensure that the upper bridge MOSFET221 is not turned on. Specifically, the level-shifted upper bridge enable signal ENH is input to the gate of the P-type MOSFET in the upper bridge driver 211, so that the P-type MOSFET is turned on, and a high potential is output to the inverter, therefore, an input end of the nand gate in the upper bridge driver 211 is a low potential representing 0, at this time, no matter what the logic level of the upper bridge PWM signal SH is, the output end of the nand gate outputs a high potential representing 1, and after the high potential passes through the inverter, a low potential is output, that is, the upper bridge drive signal UG is a low potential, and the upper bridge MOSFET221 is not turned on.

The bottom bridge sense MOSFET2141 is non-conductive, indicating that the bottom bridge MOSFET222 must not be conductive, also indicating that the top bridge MOSFET221 can operate according to the top bridge PWM signal SH at this time. In this case, the lower bridge sensing circuit 214 changes the upper bridge enable signal ENH to an enable level (high level in this embodiment) to enable the upper bridge PWM signal SH. Specifically, the level-shifted upper bridge enable signal ENH is input to the gate of the P-type MOSFET in the upper bridge driver 211 to turn off the P-type MOSFET, and a low potential is output to the inverter, so that one input terminal of the nand gate in the upper bridge driver 211 is at a high potential representing 1. When the upper bridge PWM signal SH is a high potential representing 1, the output terminal of the nand gate is a low potential representing 0, and the low potential passes through the inverter to output a high potential, that is, the upper bridge driving signal UG is a high potential, and the upper bridge MOSFET221 is turned on; similarly, when the upper bridge PWM signal SH is at a low voltage level representing 0, the upper bridge driving signal UG is at a low voltage level, and the upper bridge MOSFET221 is not turned on. That is, when the lower bridge sense MOSFET2141 is non-conductive, the upper bridge enable signal ENH is high (enabled), and the upper bridge driver 211 switches the upper bridge MOSFET221 according to the PWM signal P1.

With continued reference to fig. 3, the upper bridge sense MOSFET2121 has a conductivity type complementary to that of the upper bridge MOSFET 221; the upper bridge sense MOSFET2121 is, for example, a P-type MOSFET; and the upper bridge MOSFET221 is, for example, an N-type MOSFET. And the gate of the upper bridge sense MOSFET2121 is coupled to the source of the upper bridge MOSFET221 and the source of the upper bridge sense MOSFET2121 is coupled to the gate of the upper bridge MOSFET 221. In this way, the upper bridge sense MOSFET2121 generates the lower bridge enable signal ENL at the drain of the upper bridge sense MOSFET2121 according to the gate-source voltage of the upper bridge MOSFET 221.

Referring to fig. 3, the upper bridge sensing circuit 212 further includes a current source 2122 coupled between the lower bridge enable signal ENL and the ground potential GND, so that the lower bridge driver 213 can determine whether the upper bridge MOSFET221 is turned off according to the lower bridge enable signal ENL. Wherein the lower bridge driver 213 comprises an enable logic circuit (e.g., a nand gate shown in fig. 3) for enabling the lower bridge driver 213 to switch the lower bridge MOSFET222 according to the PWM signal P1 according to the lower bridge enable signal ENL.

On the other hand, for example, as shown in fig. 3, the upper bridge sense MOSFET2121 has a turn-on threshold voltage equal to the first threshold voltage, which is lower than or equal to the turn-on threshold voltage of the upper bridge MOSFET221 in absolute value. When the upper bridge sense MOSFET2121 is conductive, the upper bridge MOSFET221 is illustratively conductive or nearly conductive, which also indicates that the lower bridge MOSFET222 should not be conductive. In this case, the upper bridge sensing circuit 212 changes the lower bridge enable signal ENL to the disable level (high level in this embodiment) to disable the lower bridge PWM signal SL, so as to ensure that the lower bridge MOSFET222 is not turned on. Specifically, the high-level lower bridge enable signal ENL is input to the inverter in the lower bridge driver 213, so that an input terminal of the nand gate in the lower bridge driver 213 is at a low level representing 0, and at this time, no matter what the logic level of the lower bridge PWM signal SL is, the output terminal of the nand gate outputs a high level representing 1, and after the high level passes through the inverter, a low level is output, that is, the lower bridge driving signal LG is at a low level, and the lower bridge MOSFET222 is not turned on.

When the upper bridge sense MOSFET2121 is non-conductive, it is indicated that the upper bridge MOSFET221 must not be conductive, which also means that the lower bridge MOSFET222 can be operated according to the lower bridge PWM signal SL at this time. In this case, the upper bridge sensing circuit 212 changes the lower bridge enable signal ENL to an enable level (low level in this embodiment) to enable the lower bridge PWM signal SL. Specifically, the low-level lower bridge enable signal ENL is input to the inverter in the lower bridge driver 213, and thus, one input of the nand gate in the lower bridge driver 213 is at a high level representing 1. When the lower bridge PWM signal SL is at a high potential representing 1, the output of the nand gate is at a low potential representing 0, and the low potential passes through the inverter to output a high potential, that is, when the lower bridge driving signal LG is at a high potential, the lower bridge MOSFET222 is turned on; similarly, when the pull-down PWM signal SL is at a low voltage level representing 0, the pull-down driving signal LG is at a low voltage level, and the pull-down MOSFET222 is not turned on. That is, when the upper bridge sense MOSFET2121 is non-conductive and the lower bridge enable signal ENL is low (enabled), the lower bridge driver 213 switches the lower bridge MOSFET222 according to the lower bridge PWM signal SL, i.e., the inverse of the PWM signal P1.

Fig. 4 shows an embodiment of the driver circuit 31 according to the invention. As shown in fig. 4, the drive circuit 31 includes: an upper bridge driver 311, an upper bridge sense circuit 312, a lower bridge driver 313, and a lower bridge sense circuit 314. Upper bridge sensing circuit 312 includes, for example, an upper bridge sensing MOSFET3121, a current source 3122, and an upper bridge clamp MOSFET 3123; the lower bridge sense circuit 314 includes, for example, a lower bridge sense MOSFET3141 and a current source 3142. The PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates the lower bridge PWM signal SL through an inverter, wherein the PWM signal P1 is inverted from the lower bridge PWM signal SL.

As shown in fig. 4, the lower bridge sense MOSFET3141 has the same conductivity type as the lower bridge MOSFET 222; the bottom bridge sense MOSFET3141 and the bottom bridge MOSFET222 are, for example, N-type MOSFETs. And the gate of the under bridge sense MOSFET3141 is coupled to the gate of the under bridge MOSFET222 and the source of the under bridge sense MOSFET3141 is coupled to the source of the under bridge MOSFET 222. as shown in fig. 4, the source of the under bridge sense MOSFET3141 and the source of the under bridge MOSFET222 are both electrically connected to the ground potential GND. In this way, the bottom bridge sense MOSFET3141 generates the top bridge enable signal ENH at the drain of the bottom bridge sense MOSFET3141 according to the gate-source voltage of the bottom bridge MOSFET 222.

Referring to fig. 4, the lower bridge sensing circuit 314 further includes a current source 3142 coupled between the upper bridge enable signal ENH and a dc voltage VCC for generating the bootstrap voltage BOOT of the upper bridge driver 311. The upper bridge driver 311 includes an enable logic circuit 3111 and a level shift circuit 315 coupled to each other. The level shift circuit 315 is used to shift the output signal of the enable logic circuit 3111 to a start voltage range (boot voltage domain) so that the upper bridge driver 311 can determine whether the lower bridge MOSFET222 is turned off according to the upper bridge enable signal ENH. The enable logic circuit 3111 is configured to receive the upper bridge enable signal ENH to enable the upper bridge driver 311 to switch the upper bridge MOSFET221 according to the PWM signal P1.

For example, as shown in fig. 4, the turn-on threshold voltage of lower bridge sense MOSFET3141 is lower than or equal to the turn-on threshold voltage of lower bridge MOSFET 222. The lower bridge sense MOSFET3141 is conductive, indicating that the lower bridge MOSFET222 is conductive or nearly conductive, also indicating that the upper bridge MOSFET221 should not be conductive. In this case, the lower bridge sense circuit 314 changes the upper bridge enable signal ENH to a disable level (low level in this embodiment) to disable the upper bridge PWM signal SH, so as to ensure that the upper bridge MOSFET221 is not turned on.

Specifically, the upper bridge enable signal ENH of a low potential is input to the inverter in the upper bridge driver 311, and a high potential is output to the enable logic circuit 3111. The enable logic circuit 3111 is, for example, a nand latch circuit as shown in fig. 4. Therefore, an input terminal of the enable logic circuit 3111, for example, a reset pin of the nand gate latch circuit, receives the upper bridge PWM signal SH; the other end is, for example, a set pin of the nand gate latch circuit, and receives the inverted upper bridge enable signal ENH.

When the upper bridge PWM signal SH is a low potential representing 0, the enable logic circuit 3111 outputs a high potential representing 1, and the high potential passes through the level shift circuit 315 and then passes through 3 inverters, so that the generated upper bridge driving signal UG is a low potential and the upper bridge MOSFET221 is turned off.

When the upper bridge PWM signal SH is changed from the low level representing 0 to the high level representing 1, the logic level of the upper bridge enable signal ENH is the low level representing 0, the inverted signal thereof is the high level representing 1, the enable logic circuit 3111 outputs the high level representing 1, the upper bridge driving signal UG is the low level, and the upper bridge MOSFET221 is also turned off. That is, when the upper bridge enable signal ENH is at a low level (which is disabled in this embodiment), the upper bridge driving signal UG is at a low level and the upper bridge MOSFET221 is not turned on regardless of the logic level of the upper bridge PWM signal SH.

On the other hand, when the bottom bridge sense MOSFET2141 is not conductive, it indicates that the bottom bridge MOSFET222 is not conductive, which also means that the top bridge MOSFET221 can operate according to the top bridge PWM signal SH. In this case, the lower bridge sense circuit 314 changes the upper bridge enable signal ENH to an enable level (high level in this embodiment) to enable the upper bridge PWM signal SH. Specifically, the inverted signal of the upper bridge enable signal ENH is a low potential representing 0, and is input to the setting pin of the nand latch circuit. The output signal of the nand gate latch circuit is a signal with the inverse phase of the upper bridge PWM signal SH, and the signal passes through the level shift circuit 315 and then passes through 3 inverters (forming a stepped buffer circuit), so that the upper bridge driving signal UG and the upper bridge PWM signal SH are in the same phase. That is, when the bottom bridge sense MOSFET3141 is not conductive, indicating that the bottom bridge MOSFET222 is determined not to be conductive, the top bridge enable signal ENH is high (enabled), and the top bridge driver 311 switches the top bridge MOSFET221 according to the top bridge PWM signal SH which is the same as the PWM signal P1.

With continued reference to fig. 4, upper bridge sense circuit 312 includes upper bridge sense MOSFET3121, current source 3122, and upper bridge clamp MOSFET 3123. Upper bridge sense MOSFET3121 has the same conductivity type as upper bridge MOSFET 221; upper bridge clamp MOSFET3123, which has a complementary conductivity type to the upper bridge MOSFET, is coupled in series with upper bridge sense MOSFET3121 to a bootstrap (bootstrap) voltage BOOT of upper bridge driver 311. The upper bridge sense MOSFET3121 and the upper bridge MOSFET221 are, for example, N-type MOSFETs. The upper bridge clamp MOSFET3123 is, for example, a P-type MOSFET. The gate and source of the upper bridge MOSFET221 are respectively coupled to the gate of the upper bridge sensing MOSFET3121 and the gate of the upper bridge clamp MOSFET3123, so that the upper bridge sensing MOSFET3121 and the upper bridge clamp 3123 generate the lower bridge enable signal ENL at the drain of the upper bridge clamp 3123 according to the gate-source voltage of the upper bridge MOSFET 221.

Referring to fig. 4, the current source 3122 of the upper bridge sensing circuit 312 is coupled between the lower bridge enable signal ENL and the ground potential GND, so that the lower bridge driver 313 can determine whether the upper bridge MOSFET221 is turned off according to the lower bridge enable signal ENL. Wherein the lower bridge driver 313 includes an enable logic 3131 for receiving a lower bridge enable signal ENL to enable the lower bridge driver 313 to switch the lower bridge MOSFET222 according to a lower bridge PWM signal SL that is in anti-phase with the PWM signal P1.

For example, as shown in fig. 4, when the upper bridge sensing MOSFET3121 is turned on, the upper bridge MOSFET221 is shown as being turned on or nearly turned on, which also means that the lower bridge MOSFET222 should not be turned on. In this case, the upper bridge sense circuit 312 changes the lower bridge enable signal ENL to the disable level (high level in this embodiment) to disable the lower bridge PWM signal SL, so as to ensure that the lower bridge MOSFET222 is not turned on.

Specifically, the lower bridge enable signal ENL of a high potential is input to the enable logic circuit 3131. The enable logic 3131 is, for example, a nand gate latch circuit as shown in fig. 4. Therefore, an input terminal of the enable logic circuit 3131, such as the reset pin of the nand latch circuit, receives the down bridge PWM signal SL; the other end is, for example, a set pin of the nand gate latch circuit, and receives the lower bridge enable signal ENL.

When the pull-down PWM signal SL is at a low voltage level representing 0, the enable logic circuit 3131 outputs a high voltage level representing 1, and the pull-down driving signal LG generated by the high voltage level passing through the 3 inverters is at a low voltage level, such that the pull-down MOSFET222 is turned off.

When the lower bridge PWM signal SL is changed from the low level representing 0 to the high level representing 1, the logic level of the lower bridge enable signal ENL is the high level representing 1, the enable logic circuit 3131 outputs the high level representing 1, the lower bridge driving signal LG is the low level, and the lower bridge MOSFET222 is not turned on. That is, when the bridge enable signal ENL is high (disabled), the bridge driving signal LG is low regardless of the logic level of the bridge PWM signal SL, and the bridge MOSFET222 is not turned on.

On the other hand, when the upper bridge sensing MOSFET3121 is non-conductive, the upper bridge MOSFET221 is not necessarily conductive, which also means that the lower bridge MOSFET222 can be operated according to the lower bridge PWM signal SL at this time. In this case, the upper bridge sense circuit 312 changes the lower bridge enable signal ENL to an enable level (low potential in this embodiment) to enable the lower bridge PWM signal SL. Specifically, the low-potential drop-bridge enable signal ENL is input to a setting pin of the nand gate latch circuit, an output signal of the nand gate latch circuit is a signal having an opposite phase to the drop-bridge PWM signal SL, and the signal passes through 3 inverters, so that the drop-bridge drive signal LG and the drop-bridge PWM signal SL are in the same phase. That is, when upper bridge sense MOSFET3121 is non-conductive, indicating that upper bridge MOSFET221 is non-conductive, lower bridge enable signal ENL is low (enabled), lower bridge driver 313 switches lower bridge MOSFET222 according to lower bridge PWM signal SL that is in anti-phase with PWM signal P1.

Fig. 5 shows an embodiment of the driver circuit 41 according to the invention. As shown in fig. 5, the drive circuit 41 includes: an upper bridge driver 411, an upper bridge sense circuit 412, a lower bridge driver 413, and a lower bridge sense circuit 414. The upper bridge sensing circuit 412 includes, for example, an upper bridge sensing MOSFET4121, a current source 4122, and an upper bridge clamp MOSFET 4123; the bottom bridge sense circuit 414 includes a bottom bridge sense MOSFET4141 and a current source 4142, for example. The upper bridge driver 411 includes, for example, an enable logic circuit 4111, a level shift circuit 415, and 4 inverters coupled to each other. The lower bridge driver 413 includes, for example, an enable logic circuit 4131 and 4 inverters. The PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates the lower bridge PWM signal SL through an inverter, which indicates that the PWM signal P1 is inverted from the lower bridge PWM signal SL.

This embodiment differs from the embodiment shown in fig. 4 in that in this embodiment, the upper bridge sense MOSFET4121 has a conductivity type complementary to that of the upper bridge MOSFET221, and the upper bridge sense MOSFET4121 is, for example, a P-type MOSFET. The upper bridge MOSFET221 is, for example, an N-type MOSFET. Therefore, the lower bridge enable signal ENL of the present embodiment and the lower bridge enable signal ENL of the embodiment shown in fig. 4 are inverted with respect to each other. In the present embodiment, the lower bridge enable signal ENL generates the same signal as the lower bridge enable signal ENL of the embodiment shown in fig. 4 after passing through the inverter. Otherwise, the rest of this embodiment is the same as the embodiment shown in fig. 4, please refer to the description of fig. 4.

Fig. 6 shows an embodiment of the driving circuit 51 according to the invention. As shown in fig. 6, the drive circuit 51 includes: an upper bridge driver 511, an upper bridge sense circuit 512, a lower bridge driver 513, and a lower bridge sense circuit 514. The upper bridge sensing circuit 512 includes an upper bridge comparator 5121 and a level shift circuit 516; the lower bridge sense circuit includes, for example, a lower bridge comparator 514. The upper bridge driver 511 comprises, for example, an enable logic circuit 5111, a level shift circuit 515 and 3 inverters coupled to each other. The lower bridge driver 513 includes, for example, an enable logic circuit 5131 and 3 inverters. The PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH; the PWM signal P1 generates the lower bridge PWM signal SL through an inverter, wherein the PWM signal P1 is inverted from the lower bridge PWM signal SL.

As shown in fig. 6, the lower bridge comparator 514 is used for comparing the gate-source voltage of the lower bridge MOSFET222 with the lower bridge reference voltage Vref2 to generate the upper bridge enable signal ENH. In a preferred embodiment, the lower bridge reference voltage Vref2 is less than or equal to the turn-on threshold voltage of lower bridge MOSFET 222. In this way, the lower bridge comparator 514 generates the upper bridge enable signal ENH at the output terminal of the lower bridge comparator 514 according to the gate-source voltage of the lower bridge MOSFET 222.

Referring to fig. 6, the enable logic 5111 of the upper bridge driver 511 is configured to receive the upper bridge enable signal ENH to enable the upper bridge driver 511 to switch the upper bridge MOSFET221 according to the PWM signal P1.

For example, as shown in fig. 6, when the lower bridge MOSFET222 is conducting or nearly conducting, it indicates that the upper bridge MOSFET221 should not be conducting. In this case, the lower bridge comparator 514 changes the upper bridge enable signal ENH to a disable level (high level in this embodiment) according to the lower bridge driving signal LG being higher than the lower bridge reference voltage Vref2 to disable the upper bridge PWM signal SH and ensure that the upper bridge MOSFET221 is not turned on

Specifically, the high upper bridge enable signal ENH is input to the enable logic circuit 5111, and the enable logic circuit 5111 is, for example, a nand latch circuit as shown in fig. 6. Therefore, an input terminal of the enable logic circuit 5111, for example, a reset pin of the nand gate latch circuit, receives the upper bridge PWM signal SH; the other end is, for example, a set pin of the nand gate latch circuit, and receives the upper bridge enable signal ENH.

When the upper bridge PWM signal SH is a low voltage representing 0, the enable logic circuit 5111 outputs a high voltage representing 1, and the high voltage passes through the level shift circuit 515 and then through 3 inverters, so that the generated upper bridge driving signal UG is a low voltage, and the upper bridge MOSFET221 is turned off.

When the upper bridge PWM signal SH is changed from the low potential representing 0 to the high potential representing 1, the logic level of the upper bridge enable signal ENH is the high potential representing 1, the enable logic circuit 5111 outputs the high potential representing 1, the upper bridge driving signal UG is the low potential, and the upper bridge MOSFET221 is not turned on. That is, when the upper bridge enable signal ENH is high (disabled), the upper bridge driving signal UG is low regardless of the logic level of the upper bridge PWM signal SH, and the upper bridge MOSFET221 is not turned on.

On the other hand, when the lower bridge MOSFET222 is not conductive and the gate-source voltage of the lower bridge MOSFET222 is lower than the lower bridge reference voltage Vref2, it means that the upper bridge MOSFET221 can operate according to the upper bridge PWM signal SH at this time. In this case, the lower bridge comparator 514 changes the upper bridge enable signal ENH to an enable level (low level in this embodiment) to enable the upper bridge PWM signal SH. Specifically, the upper bridge enable signal ENH of a low potential is input to a set pin of the nand latch circuit in the enable logic circuit 5111. The output signal of the nand gate latch circuit is the inverted signal of the upper bridge PWM signal SH, and the upper bridge driving signal UG and the upper bridge PWM signal SH are in the same phase through 3 inverters after passing through the level shift circuit 515. That is, when the lower bridge comparator 514 changes the upper bridge enable signal ENH to a low potential representing 0, indicating that the lower bridge MOSFET222 is determined to be non-conductive, the upper bridge enable signal ENH is a low potential (enable), and the upper bridge driver 511 switches the upper bridge MOSFET221 according to the upper bridge PWM signal SH which is the same as the PWM signal P1.

Referring to fig. 6, the upper bridge comparator 5121 and the level shift circuit 516 of the upper bridge sensing circuit 512 are used to determine whether the upper bridge MOSFET221 is turned off according to the gate-source voltage of the upper bridge MOSFET221 and the upper bridge reference voltage Vref1, so that the lower bridge driver 513 can determine whether the upper bridge MOSFET221 is turned off according to the lower bridge enable signal ENL. In a preferred embodiment, the upper bridge reference voltage Vref1 is less than or equal to the turn-on threshold voltage of the upper bridge MOSFET 221. Wherein the lower bridge driver 513 includes an enable logic circuit 5131 for enabling the lower bridge driver 513 to switch the lower bridge MOSFET222 according to the lower bridge enable signal ENL and the lower bridge PWM signal SL that is inverse to the PWM signal P1.

For example, as shown in FIG. 6, when the upper bridge MOSFET221 is conductive or nearly conductive, it also means that the lower bridge MOSFET222 should not be conductive. In this case, the upper bridge comparator 5121 changes the lower bridge enable signal ENL to the disable level (high level in this embodiment) according to the upper bridge driving signal UG being higher than the upper bridge reference voltage Vref1, so as to disable the lower bridge PWM signal SL and ensure that the lower bridge MOSFET222 is not turned on. Specifically, the lower bridge enable signal ENL of a high potential is input to the enable logic circuit 3131. The level shift circuit 516 shifts the level of the output signal of the upper bridge comparator 5121 downward, and then inputs the enable logic circuit 5131, so that the enable logic circuit 5131 can determine whether to enable the lower bridge driver 513 to operate the lower bridge MOSFET222 according to the PWM signal P1 according to the lower bridge enable signal ENL.

The enable logic circuit 5131 is, for example, a nand gate latch circuit as shown in fig. 6. Therefore, an input terminal of the enable logic circuit 5131, for example, a reset pin of the nand gate latch circuit, receives the bridge PWM signal SL; the other end is, for example, a setting pin of the nand gate latch circuit, and receives the level-shifted lower bridge enable signal ENL.

When the lower bridge PWM signal SL is at a low potential representing 0, the enable logic circuit 5131 outputs a high potential representing 1, and the high potential passes through 3 inverters, and the generated lower bridge driving signal LG is at a low potential, and the lower bridge MOSFET222 is not turned on.

When the lower bridge PWM signal SL is changed from the low potential representing 0 to the high potential representing 1, the logic level of the lower bridge enable signal ENL is the high potential representing 1, the enable logic circuit 5131 outputs the high potential representing 1, the lower bridge driving signal LG is the low potential, and the lower bridge MOSFET222 is not turned on. That is, when the bridge enable signal ENL is high (disabled), the bridge driving signal LG is low regardless of the logic level of the bridge PWM signal SL, and the bridge MOSFET222 is not turned on.

On the other hand, when the upper bridge MOSFET221 is not conductive and the gate-source voltage of the upper bridge MOSFET221 is lower than the upper bridge reference voltage Vref1, it also indicates that the lower bridge MOSFET222 can operate according to the lower bridge PWM signal SL. In this case, the upper bridge comparator 5121 changes the lower bridge enable signal ENL to an enable level (low potential in this embodiment) to enable the lower bridge PWM signal SL according to the upper bridge driving signal UG being lower than the upper bridge reference voltage Vref 1. Specifically, the level of the output signal of the upper bridge comparator 5121 is shifted down by the level shift circuit 516, and then the level is inputted to the set pin of the nand latch circuit of the enable logic circuit 5131. The output signal of the nand gate latch circuit is a signal with the inverse phase of the pull-down bridge PWM signal SL, and the pull-down bridge driving signal LG and the pull-down bridge PWM signal SL are in the same phase through 3 inverters. That is, when the upper bridge comparator 5121 changes the lower bridge enable signal ENL to represent a low potential of 0 (enable), indicating that the upper bridge MOSFET221 is determined to be non-conductive, the lower bridge driver 513 switches the lower bridge MOSFET222 according to the lower bridge PWM signal SL that is inverted from the PWM signal P1.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of facilitating the understanding of the present invention by those skilled in the art, and is not intended to limit the scope of the present invention. The various embodiments described are not limited to individual applications, but may also be used in combination, for example, two or more embodiments may be combined, and some components in one embodiment may be substituted for corresponding components in another embodiment. Further, equivalent variations and combinations are contemplated by those skilled in the art within the spirit of the present invention, and the term "processing or computing or generating an output result based on a signal" is not limited to the signal itself, and includes, if necessary, performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling on the signal, and then processing or computing the converted signal to generate an output result. It is understood that equivalent variations and combinations, not necessarily all illustrated, will occur to those of skill in the art, which combinations are not necessarily intended to be limiting. Therefore, the scope of the present invention should be construed to include all such and other equivalent variations.

Claims

1. A switching converter circuit for switching a first terminal of an inductor between a first voltage and a second voltage according to a PWM signal to convert an input voltage to an output voltage, the switching converter circuit comprising:

an upper bridge MOSFET coupled between the first voltage and the first end of the inductor;

a lower bridge MOSFET coupled between the second voltage and the first end of the inductor; and

a driver circuit, comprising:

an upper bridge driver for generating an upper bridge driving signal according to the PWM signal to drive the upper bridge MOSFET;

a lower bridge driver for generating a lower bridge driving signal according to the pulse width modulation signal to drive the lower bridge MOSFET;

an upper bridge sensing circuit for sensing a gate-source voltage of the upper bridge mosfet and generating a lower bridge enable signal according to the gate-source voltage of the upper bridge mosfet to indicate a non-conductive state of the upper bridge mosfet, wherein the lower bridge enable signal enables the lower bridge driver to switch the lower bridge mosfet according to the pwm signal; and

and a lower bridge sensing circuit for sensing a gate-source voltage of the lower bridge mosfet and generating an upper bridge enable signal according to the gate-source voltage of the lower bridge mosfet to indicate a non-conductive state of the lower bridge mosfet, wherein the upper bridge enable signal enables the upper bridge driver to switch the upper bridge mosfet according to the pulse width modulation signal.

2. The switched converter circuit of claim 1, wherein the bottom bridge sensing circuit comprises a bottom bridge sensing mosfet having the same conductivity type as the bottom bridge mosfet, and a gate of the bottom bridge sensing mosfet is coupled to a gate of the bottom bridge mosfet, and a source of the bottom bridge sensing mosfet is coupled to a source of the bottom bridge mosfet, such that the bottom bridge sensing mosfet generates the top bridge enable signal at a drain of the bottom bridge sensing mosfet according to a gate-source voltage of the bottom bridge mosfet.

3. The switched converter circuit of claim 2, wherein the lower bridge sense circuit further comprises a current source coupled between the upper bridge enable signal and a bootstrap voltage of the upper bridge driver to shift a plurality of logic levels of the upper bridge enable signal to an enable voltage range, wherein the upper bridge driver comprises an enable logic circuit for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge mosfet according to the pwm signal.

4. The switched converter circuit of claim 2, wherein said lower bridge sense circuit further comprises a current source coupled between said upper bridge enable signal and a dc voltage for generating a bootstrap voltage of said upper bridge driver, wherein said upper bridge driver comprises an enable logic circuit and a level shift circuit coupled to each other for receiving said upper bridge enable signal to enable said upper bridge driver to switch said upper bridge mosfet according to said pwm signal.

5. The switched converter circuit of claim 1, wherein the lower bridge sensing circuit comprises a lower bridge comparator for comparing the gate-source voltage of the lower bridge mosfet with a lower bridge reference voltage to generate the upper bridge enable signal, wherein the upper bridge driver comprises an enable logic circuit and a level shift circuit coupled to each other for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge mosfet according to the pwm signal.

6. The switched converter circuit of claim 2, wherein an absolute value of a turn-on threshold voltage of an upper bridge sense mosfet of the upper bridge sense circuit is lower than or equal to an absolute value of a turn-on threshold voltage of the upper bridge mosfet, and an absolute value of a turn-on threshold voltage of the lower bridge sense mosfet is lower than or equal to an absolute value of a turn-on threshold voltage of the lower bridge mosfet.

7. The switched converter circuit of claim 1, wherein the upper bridge sense circuit comprises an upper bridge sense mosfet having a conductivity type complementary to the upper bridge mosfet, and the gate of the upper bridge sense mosfet is coupled to the source of the upper bridge mosfet, and the source of the upper bridge sense mosfet is coupled to the gate of the upper bridge mosfet, such that the upper bridge sense mosfet generates the lower bridge enable signal at the drain of the upper bridge sense mosfet according to the gate-source voltage of the upper bridge mosfet.

8. The switched-mode converter circuit of claim 1, wherein the upper bridge sensing circuit comprises:

an upper bridge sensing MOSFET having the same conductivity type as the upper bridge MOSFET; and

an upper bridge clamp mosfet having a conductivity type complementary to the upper bridge mosfet, the upper bridge clamp mosfet and the upper bridge sense mosfet coupled in series to a bootstrap voltage of the upper bridge driver;

the gate and the source of the upper bridge MOSFET are respectively coupled to the gate of the upper bridge sense MOSFET and the gate of the upper bridge clamp MOSFET, so that the upper bridge MOSFET generates the lower bridge enable signal at the drain of the upper bridge MOSFET according to the gate-source voltage of the upper bridge MOSFET.

9. The switched-mode converter circuit of claim 1, wherein the upper bridge sensing circuit comprises:

an upper bridge sensing MOSFET having a conductivity type complementary to the upper bridge MOSFET; and

the gate and the source of the upper bridge metal oxide semiconductor field effect transistor are respectively and correspondingly coupled to the gate of the upper bridge sensing metal oxide semiconductor field effect transistor and the gate of the upper bridge clamping metal oxide semiconductor field effect transistor, so that the upper bridge clamping metal oxide semiconductor field effect transistor generates the lower bridge enabling signal at the drain of the upper bridge clamping metal oxide semiconductor field effect transistor according to the gate-source voltage of the upper bridge metal oxide semiconductor field effect transistor.

10. The switched-mode converter circuit of claim 1, wherein the upper bridge sensing circuit comprises:

an upper bridge comparator for comparing a gate-source voltage of the upper bridge mosfet with an upper bridge reference voltage and generating the lower bridge enable signal according to a voltage of the first end of the inductor; and

a level shift circuit for shifting a level of the lower bridge enable signal downward;

the lower bridge driver comprises an enabling logic circuit for receiving the lower bridge enabling signal with the level shifted downwards so as to enable the lower bridge driver to switch the lower bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal.

11. The switched mode converter circuit of claim 1, wherein said upper bridge mosfet has the same conductivity type as said lower bridge mosfet.

12. A driving circuit of a switching converter circuit, comprising:

an upper bridge driver for generating an upper bridge driving signal according to a pulse width modulation signal to drive an upper bridge MOSFET;

a lower bridge driver for generating a lower bridge driving signal according to the pulse width modulation signal to drive a lower bridge MOSFET;

an upper bridge sensing circuit for sensing a gate-source voltage of the upper bridge mosfet and generating a lower bridge enable signal according to the gate-source voltage of the upper bridge mosfet to indicate a non-conductive state of the upper bridge mosfet, wherein the lower bridge enable signal enables the lower bridge driver to switch the lower bridge mosfet according to the pulse width modulation signal; and

13. The driving circuit of claim 12, wherein the bottom bridge sensing circuit comprises a bottom bridge sensing mosfet having the same conductivity type as the bottom bridge mosfet, and the gate of the bottom bridge sensing mosfet is coupled to the gate of the bottom bridge mosfet, and the source of the bottom bridge sensing mosfet is coupled to the source of the bottom bridge mosfet, such that the bottom bridge sensing mosfet generates the top bridge enable signal at the drain of the bottom bridge sensing mosfet according to the gate-source voltage of the bottom bridge mosfet.

14. The driving circuit of claim 13, wherein the lower bridge sense circuit further comprises a current source coupled between the upper bridge enable signal and a bootstrap voltage of the upper bridge driver for level shifting multiple logic levels of the upper bridge enable signal to an enable voltage range, wherein the upper bridge driver comprises an enable logic circuit for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge mosfet according to the pwm signal.

15. The driving circuit of claim 13, wherein the lower bridge sensing circuit further comprises a current source coupled between the upper bridge enable signal and a dc voltage for generating a bootstrap voltage of the upper bridge driver, wherein the upper bridge driver comprises an enable logic circuit and a level shift circuit coupled to each other for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge mosfet according to the pwm signal.

16. The driving circuit of claim 12, wherein the lower bridge sensing circuit comprises a lower bridge comparator for comparing the gate-source voltage of the lower bridge mosfet with a lower bridge reference voltage to generate the upper bridge enable signal, wherein the upper bridge driver comprises an enable logic circuit and a level shift circuit coupled to each other for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge mosfet according to the pwm signal.

17. The driving circuit of claim 13, wherein an absolute value of a turn-on threshold voltage of an upper bridge sense mosfet of the upper bridge sensing circuit is lower than or equal to an absolute value of a turn-on threshold voltage of the upper bridge mosfet, and an absolute value of a turn-on threshold voltage of the lower bridge sense mosfet is lower than or equal to an absolute value of a turn-on threshold voltage of the lower bridge mosfet.

18. The driving circuit of claim 12, wherein the upper bridge sensing circuit comprises an upper bridge sensing mosfet having a conductivity type complementary to the upper bridge mosfet, and the gate of the upper bridge sensing mosfet is coupled to the source of the upper bridge mosfet, and the source of the upper bridge sensing mosfet is coupled to the gate of the upper bridge mosfet, such that the upper bridge sensing mosfet generates the lower bridge enable signal at the drain of the upper bridge sensing mosfet according to the gate-source voltage of the upper bridge mosfet.

19. The driving circuit of claim 12, wherein the upper bridge sensing circuit comprises:

20. The driving circuit of claim 12, wherein the upper bridge sensing circuit comprises:

a top bridge clamp mosfet having a conductivity type complementary to the top bridge mosfet, the top bridge clamp mosfet and the top bridge sense mosfet coupled in series to a bootstrap voltage of the top bridge driver;

21. The driving circuit of claim 12, wherein the upper bridge sensing circuit comprises:

a level shift circuit for shifting the level of the lower bridge enable signal downward;

22. The driving circuit of claim 12, wherein the upper bridge mosfet driven by the driving circuit has the same conductivity type as the lower bridge mosfet driven by the driving circuit.