CN114783871A - Etching method of grid electrode - Google Patents

Etching method of grid electrode Download PDF

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Publication number
CN114783871A
CN114783871A CN202210250430.3A CN202210250430A CN114783871A CN 114783871 A CN114783871 A CN 114783871A CN 202210250430 A CN202210250430 A CN 202210250430A CN 114783871 A CN114783871 A CN 114783871A
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China
Prior art keywords
region
containing gas
etching
type
polycrystalline silicon
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Pending
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CN202210250430.3A
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Chinese (zh)
Inventor
张振兴
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202210250430.3A priority Critical patent/CN114783871A/en
Publication of CN114783871A publication Critical patent/CN114783871A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The application discloses a grid etching method, which comprises the following steps: providing a substrate, wherein a first area and a second area are distributed on the substrate, the first area is used for forming a first type of MOS device, the second area is used for forming a second type of MOS device, a gate dielectric layer is formed on the substrate, a polycrystalline silicon layer is formed on the gate dielectric layer, and a doping layer is formed in the polycrystalline silicon layer of the second area; performing first etching until the doped layer of the target region is removed, wherein in the first etching process, the introduced reaction gas comprises fluorine-containing gas; and performing second etching until the polycrystalline silicon layer of the target region is removed, wherein the polycrystalline silicon layer remaining in the first region forms a grid electrode of the first type of MOS device, the doping layer remaining in the second region and the polycrystalline silicon layer form a grid electrode of the second type of MOS device, and in the second etching process, reducing fluorine-containing gas in reaction gas and increasing chlorine-containing gas in the reaction gas.

Description

Etching method of grid
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a grid etching method.
Background
Referring to fig. 1, a schematic cross-sectional view of a logic device etched by a gate etching method provided in the related art is shown. As shown in fig. 1, a first region 101 and a second region 102 are distributed on a substrate 110 for an integrated logic device, the first region 101 is used to form a metal-oxide-semiconductor field-effect transistor (MOSFET, referred to as "MOS" in this application) device of a first type, the second region 102 is used to form a MOS device of a second type, after gate etching, a gate 131 of the MOS device of the first type is formed on the first region 101, a gate 132 of the MOS device of the second type is formed on the second region 102, and a gate dielectric layer 120 is formed between the gate and the substrate 110.
Since the doped layer 133 is formed in the gate 132 of the second type MOS device, during the gate etching process, polysilicon layers of different materials (doped layers and undoped polysilicon layers) have different morphologies, so that the edge uniformity of the gate formed by etching is poor (as shown by a dotted line in fig. 1), and the reliability and yield of the device are reduced.
Disclosure of Invention
The application provides a grid etching method which can solve the problem that the grid etching method provided in the related art causes poor uniformity of the edge of a grid, and the method comprises the following steps:
providing a substrate, wherein a first region and a second region are distributed on the substrate, the first region is used for forming a first type of MOS device, the second region is used for forming a second type of MOS device, a gate dielectric layer is formed on the substrate, a polycrystalline silicon layer is formed on the gate dielectric layer, and a doped layer is formed in the polycrystalline silicon layer of the second region;
carrying out first etching until the doped layer of the target region is removed, wherein in the first etching process, the introduced reaction gas comprises fluorine-containing gas;
and performing second etching until the polycrystalline silicon layer of the target region is removed, wherein the polycrystalline silicon layer remaining in the first region forms the grid electrode of the first type of MOS device, the doping layer remaining in the second region and the polycrystalline silicon layer form the grid electrode of the second type of MOS device, and in the second etching process, fluorine-containing gas in reaction gas is reduced, and chlorine-containing gas in the reaction gas is increased.
In some embodiments, an etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is greater than 1 during the first etching.
In some embodiments, an etching ratio of the fluorine-containing gas and the chlorine-containing gas in the reaction gas is reduced from more than 1 to less than 0.5 during the second etching.
In some embodiments, the fluorine-containing gas comprises at least one of carbon tetrafluoride, trifluoromethane, difluoromethane, octafluorocyclobutane, and nitrogen trifluoride.
In some embodiments, the chlorine-containing gas comprises chlorine gas.
In some embodiments, the first type of MOS device is a PMOS device and the second type of MOS device is an NMOS device.
The technical scheme at least comprises the following advantages:
in the manufacturing process of the logic device, when the grid electrode is etched, the reaction gas containing the fluorine-containing gas is used for etching the doped layer in the polycrystalline silicon layer, when the undoped polycrystalline silicon layer is etched, the fluorine-containing gas in the reaction gas is gradually reduced, the chlorine-containing gas is added, the uniformity of the appearance of the two sides of the grid electrode is improved, and the reliability and the yield of the device are further improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view of a logic device etched by a gate etching method provided in the related art;
FIG. 2 is a flow chart of a method for etching a gate according to an exemplary embodiment of the present application;
fig. 3 is a schematic cross-sectional view of a logic device etched by a gate etching method according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, which shows a flowchart of a method for etching a gate according to an exemplary embodiment of the present application, as shown in fig. 2, the method includes:
step S1, providing a substrate, where a first region and a second region are distributed on the substrate, the first region is used to form a first type of MOS device, the second region is used to form a second type of MOS device, a gate dielectric layer is formed on the substrate, a polysilicon layer is formed on the gate dielectric layer, and a doped layer is formed in the polysilicon layer of the second region.
Step S2, performing a first etching until the doped layer in the target region is removed, wherein the introduced reaction gas includes a fluorine-containing gas during the first etching.
Wherein the fluorine-containing gas comprises carbon tetrafluoride (CF)4) Trifluoromethane (CHF)3) Difluoromethane (CH)2F2) Octafluorocyclobutane (C)4F8) And nitrogen trifluoride (NF)3) At least one of; in the first etching process, the etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is greater than 1.
And step S3, performing second etching until the polycrystalline silicon layer of the target area is removed, wherein the residual polycrystalline silicon layer of the first area forms a grid electrode of the first type of MOS device, the residual doping layer and the polycrystalline silicon layer of the second area form a grid electrode of the second type of MOS device, and in the second etching process, reducing fluorine-containing gas in reaction gas and increasing chlorine-containing gas in the reaction gas.
Wherein the chlorine-containing gas comprises chlorine gas (Cl)2) (ii) a In the second etching process, the etching ratio of the fluorine-containing gas and the chlorine-containing gas in the reaction gas is reduced from more than 1 to less than 0.5. As shown in fig. 3, a first region 301 and a second region 302 are distributed on a substrate 310, the first region 301 is used to form a first type MOS device, the second region 302 is used to form a second type MOS device, the first type MOS device may be a PMOS device, the second type MOS device may be an NMOS device, after the second etching, a gate 331 of the PMOS device is formed in the first region 301, a gate 332 of the NMOS device is formed in the second region 302, and a gate dielectric layer 320 is arranged between the gate and the substrate 310. The gate (the gate 331 of the PMOS device and the gate 332 of the NMOS device) formed by the gate etching method provided by the embodiment of the application has better uniformity of shapes of two sides (as shown by dotted lines in fig. 3).
In summary, in the embodiment of the present application, in the manufacturing process of the logic device, when the gate is etched, the reaction gas including the fluorine-containing gas is used to etch the doped layer in the polysilicon layer, and when the undoped polysilicon layer is etched, the fluorine-containing gas in the reaction gas is gradually reduced and the chlorine-containing gas is increased, so that the uniformity of the shapes of the two sides of the gate is improved, and further, the reliability and yield of the device are improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of the invention are intended to be covered by the present invention.

Claims (6)

1. A method for etching a gate electrode is characterized by comprising the following steps:
providing a substrate, wherein a first region and a second region are distributed on the substrate, the first region is used for forming a first type of MOS device, the second region is used for forming a second type of MOS device, a gate dielectric layer is formed on the substrate, a polycrystalline silicon layer is formed on the gate dielectric layer, and a doping layer is formed in the polycrystalline silicon layer of the second region;
performing first etching until the doped layer of the target region is removed, wherein in the first etching process, the introduced reaction gas comprises fluorine-containing gas;
and performing second etching until the polycrystalline silicon layer of the target region is removed, wherein the residual polycrystalline silicon layer of the first region forms the grid electrode of the first type of MOS device, the residual doping layer and the polycrystalline silicon layer of the second region form the grid electrode of the second type of MOS device, and in the second etching process, reducing fluorine-containing gas in reaction gas and increasing chlorine-containing gas in the reaction gas.
2. The method according to claim 1, wherein an etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas during the first etching is greater than 1.
3. The method according to claim 2, wherein an etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is reduced from more than 1 to less than 0.5 during the second etching.
4. The method of claim 3, wherein the fluorine-containing gas comprises at least one of carbon tetrafluoride, trifluoromethane, difluoromethane, octafluorocyclobutane, and nitrogen trifluoride.
5. The method of claim 4, wherein the chlorine-containing gas comprises chlorine gas.
6. The method of any of claims 1 to 5, wherein the MOS devices of the first type are PMOS devices and the MOS devices of the second type are NMOS devices.
CN202210250430.3A 2022-03-15 2022-03-15 Etching method of grid electrode Pending CN114783871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210250430.3A CN114783871A (en) 2022-03-15 2022-03-15 Etching method of grid electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210250430.3A CN114783871A (en) 2022-03-15 2022-03-15 Etching method of grid electrode

Publications (1)

Publication Number Publication Date
CN114783871A true CN114783871A (en) 2022-07-22

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