CN114762107A - Skip level vias in metallization layers for integrated circuit devices - Google Patents

Skip level vias in metallization layers for integrated circuit devices Download PDF

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Publication number
CN114762107A
CN114762107A CN202080082394.3A CN202080082394A CN114762107A CN 114762107 A CN114762107 A CN 114762107A CN 202080082394 A CN202080082394 A CN 202080082394A CN 114762107 A CN114762107 A CN 114762107A
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China
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level
dielectric material
layer
power
integrated circuit
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CN202080082394.3A
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Chinese (zh)
Inventor
A·埃尔谢尔比尼
M·科布林斯基
S·利夫
J·斯旺
G·帕斯达斯特
S·N·蒂亚戈劳伊
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Intel Corp
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Intel Corp
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Publication of CN114762107A publication Critical patent/CN114762107A/en
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

An integrated circuit device can be formed that includes an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes: a first level comprising a first layer of dielectric material; a second level on the first level, wherein the second level comprises a second layer of dielectric material; a third level on the second level, wherein the third level comprises a third layer of dielectric material; at least one power/ground structure in a second tier; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

Description

Skip level vias in metallization layers for integrated circuit devices
Priority declaration
This application claims priority to U.S. patent application serial No.16/727,747 entitled "SKIP LEVEL VIAS IN metal formation LAYERS FOR INTEGRATED CIRCUIT DEVICES," filed on 26.12.2019, which is incorporated by reference in its entirety.
Technical Field
Embodiments of the present description relate generally to the field of integrated circuit device fabrication, and more particularly, to the fabrication of metallization structures within integrated circuit devices.
Background
The integrated circuit industry is continually striving to produce faster, smaller, and thinner integrated circuit devices for use in a variety of electronic products, including but not limited to computer servers and portable products such as portable computers, electronic tablets, cellular telephones, digital cameras, and the like.
As these goals are achieved, the metallization structures for the signal and power connections of integrated circuit devices have become smaller, i.e., the pitch has become smaller. As will be appreciated by those skilled in the art, thick metallization structures achieve uniform power distribution due to their low resistance and additional thermal diffusion. However, the thickness of the metallization structure also limits its minimum feature size (i.e., critical dimension "CD"). Thus, if the pitch in the metallization structure becomes smaller to achieve the industrial goals, the power transfer and thermal diffusion performance becomes worse. Accordingly, efforts are underway to develop metallization structures that reduce critical dimensions without degrading power transfer and thermal diffusion performance.
Drawings
The subject matter regarded as the disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is appreciated that the drawings depict only several embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope. The present disclosure will be described with additional specificity and detail through the use of the accompanying drawings in which:
fig. 1 is a side cross-sectional view of an integrated circuit device.
Fig. 2 is a side cross-sectional view of an integrated circuit device having skip level vias in its metallization structure, according to one embodiment of the present description.
Fig. 3-9 are side cross-sectional views of a process of forming a skip level via in a metallization structure of an integrated circuit device, according to one embodiment of the present description.
Fig. 10-12 are top views of configurations of skip level vias in metallization structures of integrated circuit devices in accordance with embodiments of the present description.
Figure 13 is a side cross-sectional view of a stacked device package according to one embodiment of the present description.
Figure 14 is a side cross-sectional view of a stacked device package according to another embodiment of the present description.
Fig. 15 is a top view of a configuration of multiple hop-level vias per pad or trace in accordance with an embodiment of the present description.
Fig. 16 is a flow diagram of a process of fabricating an integrated circuit device according to an embodiment of the present description.
FIG. 17 is an electronic system according to one embodiment of the present description.
Detailed Description
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation included within the specification. Thus, usage of the phrases "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar elements or functions throughout the several views, and the elements shown therein are not necessarily drawn to scale with each other, but may be enlarged or reduced to more easily understand the elements in the context of the present specification.
As used herein, the terms "over …," "to," "between …," and "over …" may refer to the relative position of one layer with respect to other layers. One layer "over" or "on" or bonded to another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer "between" layers may be directly in contact with the layers or may have one or more intervening layers.
The term "package" generally refers to a self-contained carrier of one or more dies, wherein the dies are attached to a package substrate and encapsulated for protection, with integrated or wirebonded interconnections between the dies and leads, pins, or bumps located on an external portion of the package substrate. The package may contain a single die or multiple dies to provide a particular function. The packages are typically mounted on a printed circuit board for interconnection with the integrated circuits and discrete components of other packages to form a larger circuit.
Here, the term "cored" generally refers to a substrate of an integrated circuit package built on a board, card, or wafer comprising a non-flexible rigid material. Typically, a small printed circuit board is used as a core, on which the integrated circuit devices and discrete passive components can be soldered. Typically, the core has vias extending from one side to the other, allowing the circuitry on one side of the core to be directly coupled to the circuitry on the opposite side of the core. The core may also serve as a platform for building up layers of conductor and dielectric materials.
Here, the term "coreless" generally refers to a substrate of an integrated circuit package that does not have a core. The lack of a core allows for a higher density packaging architecture due to the relatively large size and spacing of the vias compared to high density interconnects.
Here, the term "land side" if used herein generally refers to the side of the substrate of an integrated circuit package that is closest to the plane of attachment to a printed circuit board, motherboard, or other package. This is in contrast to the term "die side," which is the side of the substrate of the integrated circuit package to which one or more dies are attached.
Here, the term "dielectric" generally refers to any number of non-conductive materials that make up the structure of the package substrate. For purposes of this disclosure, the dielectric material may be incorporated into the integrated circuit package as a laminated film layer or as a resin molded over an integrated circuit die mounted on a substrate.
Here, the term "metallization" generally refers to a metal layer formed over and through a dielectric material of a package substrate. The metal layer is typically patterned to form metal structures such as traces and bond pads. The metallization of the package substrate may be limited to a single layer or multiple layers separated by dielectric layers.
Here, the term "bond pad" generally refers to a metallization structure that terminates integrated traces and vias in integrated circuit packages and dies. The term "solder pad" may sometimes replace "bond pad" and has the same meaning.
Here, the term "solder bump" generally refers to a solder layer formed on a bond pad. The solder layer typically has a circular shape and is therefore referred to by the term "solder bump".
Here, the term "substrate" generally refers to a planar platform that includes dielectric and metallization structures. The substrate mechanically supports and electrically couples one or more IC dies on a single platform, wherein the one or more IC dies are encapsulated by a moldable dielectric material. The substrate typically includes solder bumps on both sides as bonding interconnects. One side of the substrate, often referred to as the "die side," includes solder bumps for chip or die bonding. The opposite side of the substrate, commonly referred to as the "land side," includes solder bumps for bonding the package to a printed circuit board.
Herein, the term "component" generally refers to the grouping of components into a single functional unit. These components may be separate and mechanically assembled into a functional unit, wherein the components may be removable. In another example, the components may be permanently joined together. In some instances, these components are integrated together.
Throughout the specification and claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between the things that are connected, without any intervening devices.
The term "coupled" means directly or indirectly connected, such as through a direct electrical, mechanical, magnetic, or fluid connection between the things that are connected, or through an indirect connection via one or more passive or active intermediary devices.
The term "circuit" or "module" may refer to one or more passive and/or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a" and "the" includes plural references. The meaning of "in …" includes "in …" and "on …".
The vertical orientation is in the z-direction, and it should be understood that references to "top", "bottom", "above" and "below" refer to relative positions in the z-dimension in the usual sense. It should be understood, however, that the embodiments are not necessarily limited to the orientations or configurations shown in the figures.
The terms "substantially", "close", "approximately", "near" and "about" generally refer to within +/-10% of a target value (unless specifically indicated). Unless otherwise specified the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
For the purposes of this disclosure, the phrases "a and/or B" and "a or B" mean (a), (B), or (a and B). For the purposes of this disclosure, the phrase "A, B and/or C" denotes (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C).
The views labeled "section", "contour", and "plane" correspond to orthogonal planes within a cartesian coordinate system. Thus, the cross-section and profile views are taken in the x-z plane, and the plan views are taken in the x-y plane. Typically, the profile in the x-z plane is a cross-sectional view. Where appropriate, reference numerals have axes to indicate the orientation of the figures.
Embodiments of the present description include an integrated circuit device comprising an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure comprises: a first level comprising a first layer of dielectric material; a second level on the first level, wherein the second level comprises a second layer of dielectric material; a third level on the second level, wherein the third level comprises a third layer of dielectric material; at least one power/ground structure in a second tier; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
Fig. 1 shows an integrated circuit device 100 including an electronic substrate 110 having a metallization structure 120 formed thereon. At least one transistor 150 may be formed in or on the electronic substrate 110. The structure and circuitry of the at least one transistor 150 is well known in the art and is illustrated as a block (i.e., element 150) only for purposes of clarity and conciseness. In one embodiment, the electronic substrate 110 may be a bulk substrate composed of a single crystalline material, which may include, but is not limited to, silicon, germanium, silicon germanium, or a III-V compound semiconductor material. In other embodiments, the electronic substrate 110 may comprise a silicon-on-insulator (SOI) substrate, wherein an upper insulator layer comprised of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride is disposed on the bulk substrate. Alternatively, the electronic substrate 110 may be formed directly from a bulk substrate and local oxidation used to form the electrically insulating portion in place of the upper insulator layer described above. The electronic substrate 110 may also be other types of substrates such as germanium, gallium arsenide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and the like, any of which may be combined with silicon. The integrated circuit device 100 may be any suitable device including, but not limited to, a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit device, a field programmable gate array device, a chiplet, a combination thereof, a stack thereof, and the like. The electronic substrate 110 may also include through-substrate vias (not shown) that may allow the integrated circuit device 100 to be stacked to other devices or electronic packages.
As will be understood by those skilled in the art, the metallization structure 120 may include a plurality of layers or levels, shown as level 1221To 1225. In the embodiment shown in figure 1 of the drawings,each level of metallization structure 120 (e.g., level 122)1-1225) May each include a layer of dielectric material 1321-1325Wherein at least a portion of the conductive path 140 passes through the dielectric material layer 1321-1325At least one of (a). In one embodiment, shown in fig. 1, at least one conductive path 140 may include a plurality of electrically coupled path segments (shown as elements 142)1、1422、1423And 1424). Path segment 1421、1422、1423And 1424May include a dielectric material layer 132 formed on each of the first and second substrates1-1325A conductive pad or trace 144 in or on at least one of1、1442、1443And 144 and4wherein at least one conductive via 1461、1462、1463And 1464From its corresponding conductive trace 1441、1442、1443And 144 and4through the dielectric material layer 1321-1325At least one of which extends. In other embodiments, the electrical path may be formed by capacitive coupling between two coplanar or stacked pads, such as is the case with a capacitively coupled interconnect.
Dielectric material layer 1321-1325One or more layers of dielectric material may be included, which may be composed of suitable dielectric materials including, but not limited to, silicon oxide, silicon nitride, carbon doped dielectrics, fluorine doped dielectrics, porous dielectrics, organic polymer dielectrics, and the like.
At least one conductive trace 1441-1444And at least one conductive via 1461-1464May be made of any suitable conductive material including, but not limited to, metals such as copper, silver, nickel, gold, and aluminum, alloys thereof, and the like. It should be understood that a barrier layer (not shown) may be used if the conductive material is susceptible to migration. Conductive vias 1461-1464May be formed by any suitable process known in the art including, but not limited to, a single or dual damascene process, photolithographyDefined vias, zero-misalignment vias, self-aligned vias, and the like. In one embodiment, conductive path 140 may be a signal or I/O (input/output) path that is electrically connected to transistor 150 and possibly other devices, such as electrostatic protection circuits, voltage clamping circuits, passive devices, such as inductors, capacitors, resistors, and the like. This is shown only as a conductive path 140 that abuts transistor 150, as the interconnection of conductive path 140 and transistor 150 involves processes and structures well known in the art, and the interconnection of conductive path 140 and transistor 150 will not be shown or discussed herein for purposes of clarity and brevity.
As shown in fig. 1, at least one level (e.g., level 122)4) There may be at least one power/ground structure illustrated as power structure Vcc and ground structure Vss for operation of at least one transistor 150. As with conductive path 140, the interconnection of power supply structure Vcc and ground structure Vss with transistor 150 involves processes and structures well known in the art, and for the purposes of clarity and brevity, the interconnection of power supply structure Vcc and ground structure Vss with transistor 150 will not be shown or discussed herein. In one embodiment, tier 122 includes power structures Vcc and ground structures Vss4May be thicker than other levels, such as level 122 of metallization structure 1201-1223And 1225. Power supply structure Vcc and ground structure Vss may be made of any suitable conductive material including, but not limited to, metals such as copper, silver, nickel, gold, and aluminum, alloys thereof, and the like.
The process of forming metallization structure 120 entails forming level 122 containing power supply structure Vcc and ground structure Vss4In which conductive pads or traces 144 are formed for the conductive paths 1403Conductive pads or traces occupy level 1224Of the hollow space. Thus, resulting in the hierarchy 1224The aspect ratio constraint of the large critical dimension within requires that power structures Vcc and ground structures Vss be made smaller to support conductive pads or traces 144 therebetween3The pad or trace size CDp and the spacing CD. As will be understood by those skilled in the art, when each of power supply structure Vcc and ground structure VssWhen the magnitude of (b) is reduced, the voltage drop (or IR drop) at the same load current may be larger, the current carrying capacity of each structure may be reduced, and the heat dissipation performance may be deteriorated.
In one embodiment of the present description, a tier 122 comprising power supply structures Vcc and ground structures Vss as shown in FIG. 14Conductive pads or traces 144 of conductive paths 140 in (a)3The "hierarchy" or level 122 may be traversed or "skipped" as shown in FIG. 24Instead of conductive vias 146s (referred to as "skip level vias" 146 s). As shown in fig. 2, conductive vias or "skip level" vias 146s may pass through level 1223Dielectric material layer 1323Across the hierarchy 1224Of dielectric material layer 1324And through level 1225Dielectric material layer 1325At least a portion of which extends. The skip level via 146s is a continuous structure. For the purposes of this specification, the term "continuous" is defined to mean that there are no layers or breaks in the continuity of the conductive material used to form the skip level vias 146s, such as would result from a single deposition of the conductive material. Depending on the device design and power, there may be a similarity of 1224More than one thick layer, and in this case the vias may pass through all thick layers in order to avoid affecting the performance of the power structure or plane.
The formation of the skip level vias 146s requires a unique formation process as shown in fig. 3-9. As shown in FIG. 3, a level 122 may be formed on the electronic substrate 110 in the manner previously discussed1-1225Without the need to be at level 1224Forming conductive traces 1443(see fig. 1) and without the associated conductive vias 1463And 1464(see FIG. 1). As shown in fig. 4, a photoresist material 172 may be deposited at level 122, as is known in the art5And is patterned by exposure to form at least one opening 174 therein. As will be appreciated by those skilled in the art, the exposure of photoresist material 172 for openings 174 of skip level vias 146s (see fig. 2) may be aligned relative to power supply structures Vcc and ground structures Vss, which may help reduce intersection inhibitionA keep-out zon TKOZ, as will be discussed, or may be relative to trace 1442Alignment, which can help reduce its size and allow more area for routing. The choice will depend on the specific process, alignment capabilities, and design requirements.
As shown in fig. 5, an etchant (as indicated by arrows 176) may be introduced to form through dielectric material layer 1325Through the dielectric material layer 1324And through dielectric material layer 1323To expose conductive trace 144, at least a portion of the layer-skipping via opening 1822At least a portion of (a). The photoresist material 172 may have an opening 174 that is also in the dielectric material layer 1325 Via openings 184 are formed therein to expose at least a portion of power structures Vcc and ground structures Vss. The etching process may use multiple etchants and/or multiple steps (e.g., to remove different types of dielectrics that may be used in different layers).
As shown in fig. 6, the photolithographic mask 172 (see fig. 5) may be removed and the dielectric material layer 132 at each via opening 182 and 1845In which a pad/trace recess 186 is formed as shown in fig. 7 (e.g., by another photolithography and etching step). As shown in fig. 8, a conductive material 188 may be formed on the dielectric material layer 1325Over and substantially filling the openings 182, 184 and the recess 186 (shown in fig. 7), such as by seed deposition and plating as is well known in the art. As shown in fig. 9, any excess portions of conductive material 188 may be removed, such as by polishing, to form path segments 142s including skip level vias 146s and conductive traces 144s, and at least one conductive trace 144s for each of power supply structure Vcc and ground structure Vss5And at least one conductive via 1465The contact structure 190. Conductive trace 1445And 144s may have any suitable shape, such as circular, rectangular, square, hexagonal, etc.
The method shown and described with respect to fig. 3-9 uses a single masking process to create opening 182 for hop-level vias 146s and openings 184 for power structures Vcc and ground structures Vss. Such a process may be preferred in that,as it does not substantially cause misalignment. However, if small misalignments are tolerable, such as pads or traces 144 larger than for skip level vias 146s for power and ground structures Vcc and Vss2Multiple process steps and masks may be used. Alternatively, multicolor lithography techniques may be used, as will be understood by those skilled in the art.
As will be appreciated by those skilled in the art, embodiments of the present description may achieve a higher density of conductive paths 140 (see fig. 9) with an IR drop comparable to known configurations, or a substantially lower IR drop of conductive paths 140 (see fig. 9) with substantially the same density as known configurations. Embodiments of the present description may be implemented with a minimum of additional processing steps. In addition, tier 122 having power supply structures Vcc and ground structures Vss is removed4Conductive trace 144 in3(see fig. 1) may be reduced to its parasitic capacitance and to a capacitor (not shown) that may be formed within the metallization structure 120. This may allow for the use of smaller drivers with lower power, and may allow for operation at higher data rates, as will be appreciated by those skilled in the art. Furthermore, since larger power supply structures Vcc and ground structures Vss (as previously discussed) may be fabricated, inductive/resistive noise coupling may be reduced, which in turn may improve data rates and/or signal transmission power.
Although shown in fig. 2-9, embodiments of the present description illustrate only extending completely through one dielectric material layer (i.e., dielectric material layer 132)4) And extends at least partially through the overlying dielectric material layer (i.e., dielectric material layer 132)5) And an underlying dielectric layer (i.e., dielectric material layer 132)3) Although embodiments of the present description are not limited thereto, as skip level vias may extend partially and/or fully through any number of levels (e.g., 122)1-1225) This may reduce the resistance, particularly when it is desired to utilize a barrier layer (not shown) as previously described, since there will be less resistance in the current path, as will be appreciated by those skilled in the art. It should be understood that it can be extendedThe number of dielectric layers that extend through will depend on the process limitations and thermo-mechanical considerations of the integrated circuit device 100 as well as its maximum current carrying capacity.
Skip level vias 146SMay be in any suitable location and configuration. However, the basic structure of embodiments of the present description may use a through dielectric material layer 1324As close as possible to the critical dimension CD to minimize the resistance of the power delivery network (not shown), where power supply structure Vcc and ground structure Vss are part of the power delivery network (referred to as "through keep out" or "TKOZ"). It should be understood, however, that because the skip level vias 146s are created at a different step and level than the metallization, they are not limited by the standard lithographic critical dimensions (e.g., minimum allowable photoresist width) associated therewith. In one embodiment, as shown in fig. 10 (a view along line 10-10 of fig. 2), skip level vias 146s may be located in the space between power structures Vcc and ground structures Vss (i.e., critical dimension CD), such that keep-out region TKOZ will be substantially equal to critical dimension CD. In another embodiment, as shown in fig. 11, if there is a possibility of excessive misalignment of the jumper level vias 146s, or if there is a concern about diffusion or drift of the conductive material used to form the jumper level vias 146s, the penetration of the keep-out region TKOZ may be extended by forming notches 192 in the power supply structure Vcc and/or the ground structure Vss (see fig. 10). In yet another embodiment, as shown in fig. 12, power supply structure Vcc and/or ground structure Vss may have at least one opening 194 formed therethrough, wherein a portion of dielectric material layer 1324 is within at least one opening 194. Skip level vias 146s may extend through at least one opening 194 and be separated from power supply structures Vcc and ground structures Vss by a portion of dielectric material layer 1324 therein. A perimeter (not specifically labeled) of the at least one opening 194 may define a through keep out region TKOZ.
Although the embodiments of fig. 2-12 contemplate using skip level vias 146s for signal or I/O (input/output) routing purposes, the subject matter of this specification is not so limited. In another embodiment of the present description, in the stacked device package 200, a layer skip is performedThe holes may be used to deliver power through the first integrated circuit device 210 to the second integrated circuit device 310. As shown in fig. 13, the first integrated circuit device 210 may include a first electronic substrate 220 having a metallization structure 230 formed thereon, wherein the metallization structure 230 may include a plurality of levels, shown as level 2321To 2326. As further shown in fig. 13, the integrated circuit device 310 may include a first electronic substrate 320 having a metallization structure 330 formed thereon, wherein the metallization structure 330 may include a plurality of levels, shown as level 3321To 3323。
In one embodiment, the first integrated circuit device 210 may be electrically attached to the second integrated circuit device 310 by a hybrid bonding technique to form an electrical connection therebetween. Using hybrid bonding techniques, the level 232 of the metallization layer 230 of the first integrated circuit device 2106And a layer of dielectric material (not labeled) and a level 332 of metallization layer 330 of the second integrated circuit device 3103The dielectric material layer (not labeled) of (a) forms a chemical bond (e.g., a covalent bond) at room temperature (e.g., about 25 degrees celsius). Level 232 of metallization layer 230 of first integrated circuit device 2106May be in contact with a level 332 of the metallization layer 330 of the second integrated circuit device 3103Is aligned with at least one conductive trace or pad (not labeled). Heat is then applied, which is at level 232 of the metallization layer 230 of the first integrated circuit device 2106And a layer of dielectric material (not labeled) and a level 332 of metallization layer 330 of the second integrated circuit device 3103A stronger bond is formed between the layers of dielectric material (not labeled). The heat also simultaneously causes the level 232 of the metallization layer 230 of the first integrated circuit device 2106With at least one conductive trace or pad (not labeled) of the second integrated circuit device 310 and a level 332 of the metallization layer 330 of the second integrated circuit device 3103Expands and fuses to form a permanent bond.
As shown in fig. 13, the first through silicon via 2241And a fifth through silicon via 2245The first supply voltage Vcc1 may be delivered to the metallization layer 230 for use in a first integrated circuit deviceAnd (6) preparing 210. Third through silicon via 2243May be part of the conductive path 260 to provide a ground path Vss for the first integrated circuit device 210 within the metallization layer 230, wherein the conductive path 260 also extends within the metallization layer 330 to provide a ground path for the second integrated circuit device 310. Second through silicon via 2242May be a conductive path 2501And a fourth through silicon via 224, and4may be a conductive path 2502Both paths carry the second supply voltage Vcc2 to the metallization layer 330 for the second integrated circuit device 310. As shown in FIG. 13, the conductive path 2501And a conductive path 2502Each including a via for passing through a level 232 within a metallization layer 2304Contains power and ground structures for the first integrated circuit device 210 in the manner discussed in fig. 2-12. The embodiment shown in fig. 12 may alleviate two challenges with device stacking, which are metal layer pad/trace consumption of the top device (i.e., integrated circuit device 310), and through metallization structures 220 and 320 to through silicon via 2241-2245The resistance of (2). As will be understood by those skilled in the art, when the first integrated circuit device 210 and the second integrated circuit device 310 operate at the same voltage, the voltages at the transmitter and receiver circuits (not shown) of the first integrated circuit device 210 and the second integrated circuit device 310 may be different due to noise levels and IR drops, which requires the addition of a large guard band in the design. With embodiments of the present description, inductive and resistive voltage drops are significantly reduced, which may result in reduced guard bands and improved performance.
As further shown in fig. 13, the stacked device package 200 may be attached to an electronic interposer, organic package, or board 350 by a plurality of package-to-board interconnects 352 (e.g., reflowable solder bumps or balls) in a configuration commonly referred to as a flip-chip or controlled collapse chip connection ("C4") configuration. The package-to-board interconnects 352 may be at the through-silicon vias 224 of the stacked device package 2001-2245And corresponding bond pads 352 on or in the electronic board 350 to form electrical connections therebetween. The electronic board 350 may be stackedConductive paths 358 are provided between the stacked device package 200 and external components (not shown).
Package-to-board interconnect 352 may be any suitable conductive material or structure including, but not limited to, solder balls, metal bumps or pillars, metal-filled epoxy, or combinations thereof. In one embodiment, the package-to-board interconnects 352 may be solder balls formed from tin, lead/tin alloys (e.g., 63% tin/37% lead solder), and high tin content alloys (e.g., 90% or more tin-such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and the like). In another embodiment, the package-to-board interconnects 352 may be copper bumps or pillars. In another embodiment, the package-to-board interconnects 352 may be metal bumps or pillars coated with a solder material.
The embodiment shown in fig. 13 illustrates an integrated circuit package 200 in which through-silicon vias 224 are formed through the electronic substrate 220 prior to forming the metallization structures 230 of the first integrated circuit device 2101-2245. However, the embodiments of the present specification are not limited thereto. In another embodiment illustrated in fig. 14, a through-silicon via 224 may be formed through the electronic substrate 220 after forming the metallization structure 210 of the first integrated circuit device 2101-2245. This will allow for through substrate vias 2241-2245Extends into the metallization layer 230 and reduces the number of traces/pads and vias that need to be formed therein.
For power delivery embodiments, such as shown in fig. 13 and 14, it may be advantageous to have more than one skip level via electrically connected to a single trace or pad rather than a single relatively thick skip level via. As shown in FIG. 15, a plurality of skip level vias (labeled SLV1-SLV4) may extend between or alongside ground structure Vss and first power supply structure Vcc1 to contact second power supply structure Vcc 2. The relevant dielectric material layers are not shown for clarity and simplicity. This configuration may help reduce resistance and may help reduce thermomechanical stresses near skip level vias SLV1-SLV4 as compared to a single thick skip level via, such as skip level via 142s of fig. 2.
Fig. 16 is a flow diagram of a process 400 of fabricating an integrated circuit package, according to an embodiment of the present description. As described in block 410, a first level including a first layer of dielectric material may be formed. A second level may be formed on the first level, wherein the second level includes a second layer of dielectric material, as described in block 420. A third level may be formed on the second level, wherein the third level includes a third layer of dielectric material, as described in block 430. At least one power/ground structure may be formed in the second tier, as described in block 440. As set forth in block 450, at least one opening may be formed to extend at least partially through a first level of a first layer of dielectric material, through a second level of a second layer of dielectric material, and at least partially through a third level of a third layer of dielectric material. As set forth in block 460, a continuous conductive material may be disposed within the opening to form a skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level.
FIG. 17 illustrates an electronic system or computing device 500 in accordance with one implementation of the present description. The computing device 500 may include a housing 501 having a board 502 disposed therein. Computing device 500 may include a plurality of integrated circuit components including, but not limited to, a processor 504, at least one communication chip 506A, 506B, volatile memory 508 (e.g., DRAM), non-volatile memory 510 (e.g., ROM), flash memory 512, a graphics processor or CPU 514, a digital signal processor (not shown), a cryptographic processor (not shown), a chipset 516, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power Amplifier (AMP), a Global Positioning System (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a mass storage device (not shown) (e.g., hard disk drive, Compact Disc (CD), Digital Versatile Disc (DVD), etc.). Any integrated circuit component may be physically and electrically coupled to board 502. In some implementations, at least one of the integrated circuit components can be part of the processor 504.
The communication chip enables wireless communication for transferring data to and from the computing device. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip or device may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and above. The computing device may include a plurality of communication chips. For example, a first communication chip may be dedicated for shorter range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated for longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and the like.
The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
At least one of the integrated circuit components may comprise an integrated circuit device comprising an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure comprises: a first level comprising a first layer of dielectric material; a second level on the first level, wherein the second level comprises a second layer of dielectric material; a third level on the second level, wherein the third level comprises a third layer of dielectric material; at least one power/ground structure in a second level; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further embodiments, the computing device may be any other electronic device that processes data.
It should be understood that the subject matter of this specification is not necessarily limited to the particular applications illustrated in fig. 1-17. As will be appreciated by those skilled in the art, the present subject matter may be applied to other integrated circuit devices and component applications, as well as any suitable electronic application.
The following examples relate to further embodiments, and the details in the examples may be used anywhere in one or more embodiments, where example 1 is an integrated circuit structure, including: a first level comprising a first layer of dielectric material; a second level on the first level, wherein the second level comprises a second layer of dielectric material; a third level on the second level, wherein the third level comprises a third layer of dielectric material; at least one power/ground structure in a second tier; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
In example 2, the subject matter of example 1 can optionally include: the at least one power/ground structure includes a power structure and a ground structure, and wherein the at least one skip level via extends through the second level of the second dielectric material layer between the power structure and the ground structure.
In example 3, the subject matter of example 2 can optionally include: at least one of the power and ground structures has a notch adjacent to the at least one skip level via.
In example 4, the subject matter of example 1 can optionally include: the at least one power/ground structure includes at least one opening extending through the at least one power/ground structure, wherein a portion of the second layer of dielectric material is disposed within the at least one opening, and wherein the at least one skip level via extends within the portion of the second layer of dielectric material through the at least one opening.
Example 5 is an integrated circuit device comprising an electronic substrate and a metallization structure on the electronic substrate, the metallization structure comprising: a first level comprising a first layer of dielectric material; a second level on the first level, wherein the second level comprises a second layer of dielectric material; a third level on the second level, wherein the third level comprises a third layer of dielectric material; at least one power/ground structure in a second tier; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
In example 6, the subject matter of example 5 can optionally include: the at least one power/ground structure includes a power structure and a ground structure, and wherein the at least one skip level via extends through the second level of the second dielectric material layer between the power structure and the ground structure.
In example 7, the subject matter of example 6 can optionally include: at least one of the power and ground structures has a notch adjacent to the at least one skip level via.
In example 8, the subject matter of example 5 can optionally include: the at least one power/ground structure includes at least one opening extending through the at least one power/ground structure, wherein a portion of the second layer of dielectric material is disposed within the at least one opening, and wherein the at least one skip level via extends within the portion of the second layer of dielectric material through the at least one opening.
Example 9 is an electronic system comprising a board and an integrated circuit device electrically attached to the board, wherein the integrated circuit device comprises an electronic substrate and a metallization structure on the electronic substrate, the metallization structure comprising: a first level comprising a first layer of dielectric material; a second level on the first level, wherein the second level comprises a second layer of dielectric material; a third level on the second level, wherein the third level comprises a third layer of dielectric material; at least one power/ground structure in a second tier; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
In example 10, the subject matter of example 9 can optionally include: the at least one power/ground structure includes a power structure and a ground structure, and wherein the at least one skip level via extends through the second level of the second dielectric material layer between the power structure and the ground structure.
In example 11, the subject matter of example 10 can optionally include: at least one of the power and ground structures has a notch adjacent to the at least one skip level via.
In example 12, the subject matter of example 9 can optionally include: the at least one power/ground structure includes at least one opening extending through the at least one power/ground structure, wherein a portion of the second layer of dielectric material is disposed within the at least one opening, and wherein the at least one skip level via extends within the portion of the second layer of dielectric material through the at least one opening.
Example 13 is a method of fabricating an integrated circuit structure, comprising: forming a first level comprising a first layer of dielectric material; forming a second level on the first level, wherein the second level comprises a second layer of dielectric material; forming a third level on the second level, wherein the third level comprises a third layer of dielectric material; forming at least one power/ground structure in a second level; forming at least one opening extending at least partially through the first level of the first layer of dielectric material, through the second level of the second layer of dielectric material, and at least partially through the third level of the third layer of dielectric material; and providing a continuous conductive material within the opening to form a skip level via, the skip level extending through the first layer of dielectric material at least partially through the first level, through the second layer of dielectric material, and at least partially through the third layer of dielectric material.
In example 14, the subject matter of example 13 can optionally include: the at least one power/ground structure includes a power structure and a ground structure, and wherein the at least one skip level via extends through the second level of the second dielectric material layer between the power structure and the ground structure.
In example 15, the subject matter of example 14 can optionally include: at least one of the power and ground structures has a notch adjacent to the at least one skip level via.
In example 16, the subject matter of example 13 can optionally include: the at least one power/ground structure includes at least one opening extending through the at least one power/ground structure, wherein a portion of the second layer of dielectric material is disposed within the at least one opening, and wherein the at least one skip level via extends within the portion of the second layer of dielectric material through the at least one opening.
In example 17, the subject matter of example 13 can optionally include: an integrated circuit device is formed by forming an electronic substrate and forming a metallization layer on the electronic substrate, wherein the metallization layer includes a first level, a second level, a third level, at least one power/ground structure in the second level, and at least one skip level via.
In example 18, the subject matter of example 17 can optionally include: forming the electronic substrate includes forming a transistor therein and electrically connecting the transistor to the skip level via.
In example 19, the subject matter of example 17 or 18 can optionally include: an electronic board is formed and an electronic substrate is electrically attached to the electronic board.
In example 20, the subject matter of any of examples 17 to 19 may optionally include: the second integrated circuit device is electrically attached to the metallization layer of the first integrated circuit device.
Having thus described in detail embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims (20)

1. An integrated circuit structure, comprising:
a first level comprising a first layer of dielectric material;
a second level on the first level, wherein the second level comprises a second layer of dielectric material;
a third level on the second level, wherein the third level comprises a third layer of dielectric material;
at least one power/ground structure in the second tier; and
at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
2. The integrated circuit structure of claim 1, wherein the at least one power/ground structure comprises a power structure and a ground structure, and wherein the at least one skip level via extends through the second dielectric material layer of the second level between the power structure and the ground structure.
3. The integrated circuit structure of claim 2, wherein at least one of the power structure and the ground structure has a notch adjacent to the at least one skip level via.
4. The integrated circuit structure of claim 1, wherein the at least one power/ground structure comprises at least one opening extending therethrough, wherein a portion of the second layer of dielectric material is disposed within the at least one opening, and wherein the at least one skip level via extends within the portion of the second layer of dielectric material through the at least one opening.
5. An integrated circuit device, comprising:
an electronic substrate; and
a metallization structure on the electronic substrate, wherein the metallization structure comprises: a first level comprising a first layer of dielectric material; a second level on the first level, wherein the second level comprises a second layer of dielectric material; a third level on the second level, wherein the third level comprises a third layer of dielectric material; at least one power/ground structure in the second level; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
6. The integrated circuit device of claim 5, wherein the at least one power/ground structure comprises a power structure and a ground structure, and wherein the at least one skip level via extends through the second dielectric material layer of the second level between the power structure and the ground structure.
7. The integrated circuit device of claim 6, wherein at least one of the power structure and the ground structure has a notch adjacent to the at least one hop-level via.
8. The integrated circuit device of claim 5, wherein the at least one power/ground structure comprises at least one opening extending therethrough, wherein a portion of the second layer of dielectric material is disposed within the at least one opening, and wherein the at least one skip level via extends within the portion of the second layer of dielectric material through the at least one opening.
9. An electronic system, comprising:
a plate; and
an integrated circuit device electrically attached to the board, wherein the integrated circuit device comprises:
an electronic substrate; and
a metallization structure on the electronic substrate, wherein the metallization structure comprises: a first level comprising a first layer of dielectric material; a second level on the first level, wherein the second level comprises a second layer of dielectric material; a third level on the second level, wherein the third level comprises a third layer of dielectric material; at least one power/ground structure in the second tier; and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
10. The electronic system of claim 9, wherein the at least one power/ground structure comprises a power structure and a ground structure, and wherein the at least one skip level via extends through the second dielectric material layer of the second level between the power structure and the ground structure.
11. The electronic system of claim 10, wherein at least one of the power structure and the ground structure has a notch adjacent to the at least one jump level via.
12. The electronic system of claim 9, wherein the at least one power/ground structure comprises at least one opening extending therethrough, wherein a portion of the second dielectric material layer is disposed within the at least one opening, and wherein the at least one jump-level via extends within the portion of the second dielectric material layer through the at least one opening.
13. A method of forming an integrated circuit structure, comprising:
forming a first level comprising a first layer of dielectric material;
forming a second level on the first level, wherein the second level comprises a second layer of dielectric material;
forming a third level on the second level, wherein the third level comprises a third layer of dielectric material;
forming at least one power/ground structure in the second level;
forming at least one opening extending at least partially through the first layer of dielectric material of the first level, through the second layer of dielectric material of the second level, and at least partially through the third layer of dielectric material of the third level; and
providing a continuous conductive material within the opening to form a skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric material layer of the second level, and at least partially through the third dielectric material layer of the third level.
14. The method of claim 13, wherein forming the at least one power/ground structure comprises: forming a power structure and forming a ground structure, and wherein forming the at least one skip level via comprises: forming the at least one skip level via to extend through the second layer of dielectric material of the second level between the power supply structure and the ground structure.
15. The method of claim 14, further comprising: forming a notch in at least one of the power structure and the ground structure, wherein the notch is adjacent to the at least one skip level via.
16. The method of claim 13, wherein forming the at least one power/ground structure comprises: forming at least one opening extending through the at least one power/ground structure, wherein a portion of the second dielectric material layer is disposed within the at least one opening, and wherein the at least one skip level via extends within the portion of the second dielectric material layer through the at least one opening.
17. The method of any of claims 13-16, further comprising forming an integrated circuit device by forming an electronic substrate and forming a metallization layer on the electronic substrate, wherein the metallization layer comprises at least one power/ground structure in the first level, the second level, the third level, the second level, and at least one skip level via.
18. The method of claim 17, wherein the electronic substrate comprises a transistor, and wherein the transistor is electrically connected to the skip level via.
19. The method of claim 17, further comprising forming an electronic board and electrically attaching the electronic substrate to the electronic board.
20. The method of claim 17, further comprising electrically attaching a second integrated circuit device to the metallization layer of the first integrated circuit device.
CN202080082394.3A 2019-12-26 2020-08-11 Skip level vias in metallization layers for integrated circuit devices Pending CN114762107A (en)

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