CN114759092A - High voltage element, high voltage control element and manufacturing method thereof - Google Patents

High voltage element, high voltage control element and manufacturing method thereof Download PDF

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Publication number
CN114759092A
CN114759092A CN202111508737.0A CN202111508737A CN114759092A CN 114759092 A CN114759092 A CN 114759092A CN 202111508737 A CN202111508737 A CN 202111508737A CN 114759092 A CN114759092 A CN 114759092A
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region
drift
channel
semiconductor layer
gate
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张钧隆
熊志文
游焜煌
邱国卿
翁武得
邱建维
杨大勇
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Richtek Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

The invention provides a high-voltage element, a high-voltage control element and a manufacturing method thereof. The high-voltage element includes: the drift oxidation region is arranged on the drift region, the shallow trench isolation region is arranged below the drift oxidation region, part of the drift oxidation region is arranged right above part of the shallow trench isolation region and is connected with the shallow trench isolation region, and the shallow trench isolation region is arranged between the drain electrode and the body region.

Description

High voltage element, high voltage control element and manufacturing method thereof
Technical Field
The present invention relates to a high voltage device, a high voltage control device and a method for manufacturing the same, and more particularly, to a high voltage device, a high voltage control device and a method for manufacturing the same capable of increasing breakdown protection voltage and reducing on-resistance.
Background
Fig. 1A and 1B show a cross-sectional view and a top view of a conventional high voltage device 100, respectively. The high voltage device is a semiconductor device in which a voltage applied to a drain is higher than 3.3V during a normal operation. In general, taking the high voltage device 100 shown in fig. 1A and 1B as an example, a drift region 12a (indicated by a dotted line in fig. 1A) is disposed between the drain 19 and the body region 16 of the high voltage device 100 to separate the drain 19 from the body region 16, and the lateral length of the drift region 12a is adjusted according to an operating voltage required to be sustained during normal operation. As shown in fig. 1A and 1B, the high voltage device 100 includes: well region 12, insulating structure 13, drift oxide region 14, body region 16, gate 17, source 18, and drain 19. The well 12 has an N-type conductivity and is formed on the substrate 11, and the insulating structure 13 is a local oxidation of silicon (LOCOS) structure to define an operation region 13a as a main active region of the high voltage device 100 during operation. The range of the operation region 13a is indicated by a thick black dashed box in fig. 1B. As shown in fig. 1A, a portion of the gate 17 is over the drift region 12a, covering a portion of the drift oxide region 14. In general, the thickness of the drift oxide region 14 is about 2,500 a to about
Figure BDA0003404432210000015
And the thickness of the gate oxide layer in the gate 17 is about
Figure BDA0003404432210000014
To is that
Figure BDA0003404432210000016
In the meantime. The thickness of the drift oxide region 14 is much greater than the thickness of the gate oxide layer by a factor of at least 5. By using the thicker drift oxide region 14, when the high voltage device 100 is in the off state, the high voltage is blocked, so that the relatively higher electric field falls in the thicker drift oxide region 14, thereby increasing the off breakdown protection voltage of the high voltage device 100. However, although the thicker drift oxide region 14 increases the breakdown voltage (off breakdown voltage) of the high voltage device 100 (increases the off breakdown voltage), the on-resistance and the gate-drain capacitance of the high voltage device 100 are relatively increased, which results in a decrease in the operation speed and a decrease in the device performance.
In view of the above, the present invention provides a high voltage device, a high voltage control device and a method for manufacturing the same, which can improve the operation speed, reduce the on-resistance and increase the breakdown protection voltage without affecting the thickness of the drift oxide region.
Disclosure of Invention
In one aspect, the present invention provides a high voltage device comprising: a semiconductor layer formed on a substrate; a well region of a first conductivity type formed in the semiconductor layer; a Shallow Trench Isolation (STI) region formed in the semiconductor layer; a drift oxide region formed on the semiconductor layer, wherein the shallow trench isolation region is located under the drift oxide region, and part of the drift oxide region is located right above part of the shallow trench isolation region and connected with the shallow trench isolation region, wherein the drift oxide region is located on a drift region; a body region of a second conductivity type formed in the semiconductor layer, the body region being connected to the well region in a channel direction; a gate formed on the semiconductor layer, wherein a part of the body region is located right below the gate and connected to the gate to provide a reverse current channel for the high voltage device in a turn-on operation, and another part of the gate is located right above the drift oxide region and connected to the drift oxide region; and a source and a drain of the first conductivity type, the source and the drain being formed in the semiconductor layer and respectively located in the body region under the outside of the gate and the well region away from the body region side, and the drift region being located in the well region between the drain and the body region in the channel direction to serve as a drift current channel of the high voltage element in the turn-on operation; wherein the shallow trench isolation region is between the drain and the body region.
In another aspect, the present invention provides a method for manufacturing a high voltage device, including: forming a semiconductor layer on a substrate; forming a well region in the semiconductor layer, the well region having a first conductivity type; forming at least one Shallow Trench Isolation (STI) region in the semiconductor layer; forming a drift oxide region on the semiconductor layer, wherein the shallow trench isolation region is located below the drift oxide region, and part of the drift oxide region is located right above part of the shallow trench isolation region and connected with the shallow trench isolation region, and the drift oxide region is located on a drift region; forming a body region in the semiconductor layer, the body region being connected to the well region in a channel direction, the body region having a second conductivity type; forming a gate on the semiconductor layer, wherein a portion of the body region is located directly under the gate and connected to the gate to provide a reverse current path for the high voltage device during a turn-on operation, and another portion of the gate is located directly above the drift oxide region and connected to the drift oxide region; and forming a source and a drain in the semiconductor layer, wherein the source and the drain are respectively located in the body region under the outside of the gate and the well region far away from the body region side, and the drift region is located in the well region between the drain and the body region in the channel direction, so as to serve as a drift current channel of the high-voltage element in the conducting operation; wherein the shallow trench isolation region is between the drain and the body region.
In another aspect, the present invention provides a high voltage control device comprising: a semiconductor layer formed on a substrate; a drift well region of a first conductivity type formed in the semiconductor layer; a channel well region of a second conductivity type formed in the semiconductor layer, the drift well region being connected to the channel well region in a channel direction; a Shallow Trench Isolation (STI) region formed in the semiconductor layer; a drift oxide region formed on the semiconductor layer, wherein the shallow trench isolation region is located under the drift oxide region, and a part of the drift oxide region is located right above a part of the shallow trench isolation region and connected with the shallow trench isolation region, wherein the drift oxide region is located on a drift region; a gate formed on the semiconductor layer, wherein a part of the channel well region is located right below the gate and connected to the gate to provide an inversion current channel for the high voltage control element in a turn-on operation, and another part of the gate is located right above the drift oxide region and connected to the drift oxide region; a source and a drain of the first conductivity type, the source and the drain being formed in the semiconductor layer, and the source and the drain being respectively located in the channel well region under the outside of the gate and in the drift well region away from the channel well region side, and the drift region being located in the drift well region between the drain and the channel well region in the channel direction for serving as a drift current channel of the high voltage control element in the on operation; a channel well region contact electrode of the second conductivity type formed in the channel well region for serving as an electrical contact of the channel well region, the channel well region contact electrode being formed under and connected to an upper surface of the semiconductor layer in a vertical direction; and a channel isolation region formed in the semiconductor layer and located between the source electrode and the channel well region contact electrode, the channel isolation region being formed below and connected to the upper surface; wherein the shallow trench isolation region is between the drain and the channel well region.
In another aspect, the present invention provides a method for manufacturing a high voltage control device, comprising: forming a semiconductor layer on a substrate; forming a drift well region in the semiconductor layer, the drift well region having a first conductivity type; forming a channel well region in the semiconductor layer, the channel well region having a second conductivity type, the drift well region being connected to the channel well region in a channel direction; forming at least one Shallow Trench Isolation (STI) region in the semiconductor layer and a channel isolation region in the semiconductor layer, the channel isolation region being formed below and connected to an upper surface of the semiconductor layer; forming a drift oxide region on the semiconductor layer, wherein the shallow trench isolation region is located below the drift oxide region, and part of the drift oxide region is located right above part of the shallow trench isolation region and connected with the shallow trench isolation region, and the drift oxide region is located on a drift region; forming a gate on the semiconductor layer, wherein a part of the channel well region is located right below the gate and connected to the gate to provide an inversion current channel of the high voltage control element in a turn-on operation, and another part of the gate is located right above the drift oxide region and connected to the drift oxide region; and forming a source electrode and a drain electrode in the semiconductor layer, wherein the source electrode and the drain electrode are respectively positioned in the channel well region under the outer part of the grid electrode and the drift well region far away from the channel well region side, and in the channel direction, the drift region is positioned in the drift well region between the drain electrode and the channel well region and is used as a drift current channel of the high-voltage control element in the conducting operation; and forming a channel well region contact electrode in the channel well region, the channel well region contact electrode having the second conductivity type and serving as an electrical contact of the channel well region, the channel well region contact electrode being formed under and connected to the upper surface in a vertical direction; the shallow groove isolation region is arranged between the drain electrode and the channel well region, and the channel isolation region is arranged between the source electrode and the contact electrode of the channel well region.
In one embodiment, the drift oxide region includes a local oxidation of silicon (LOCOS) structure or a Chemical Vapor Deposition (CVD) oxide region.
In one embodiment, the shallow trench isolation region is connected to the drain in the channel direction.
In one embodiment, the semiconductor layer is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm.
In one embodiment, the drift oxide region comprises the CVD oxide region, and the CVD oxide region has a thickness
Figure BDA0003404432210000051
In one embodiment, the high voltage device is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having a gate drive voltage of 3.3V and a gate oxide thickness
Figure BDA0003404432210000052
In one embodiment, a low voltage device is formed on the substrate, and the channel length of the low voltage device is 0.18 μm.
In one embodiment, the body region is formed by a self-aligned process step, wherein the self-aligned process step comprises: etching a polysilicon layer to form a conductive layer of the gate; and forming the body region by an ion implantation process step with the conductive layer as a mask.
The invention has the advantages that the invention can reduce the on-resistance of the high-voltage element and increase the breakdown protection voltage of the high-voltage element.
Another advantage of the present invention is that it can be manufactured using standard high voltage device processing steps without the need for additional lithography processing steps, and therefore the manufacturing cost is the same as that of the prior art.
The purpose, technical content, features and effects of the present invention will be more readily understood by the following detailed description of specific embodiments.
Drawings
Fig. 1A and 1B show a schematic cross-sectional view and a schematic top view of a conventional high voltage device, respectively.
Fig. 2A and 2B show a cross-sectional view and a top view of a high voltage device according to an embodiment of the invention.
Fig. 3A and 3B show a cross-sectional view and a top view of a high voltage device according to another embodiment of the invention.
Fig. 4A and 4B show a cross-sectional view and a top view of a high voltage control element according to another embodiment of the present invention.
Fig. 5A-5H are schematic diagrams illustrating a method for fabricating a high voltage device according to an embodiment of the invention.
Fig. 6A-6I are schematic diagrams illustrating a method for manufacturing a high voltage control device according to another embodiment of the present invention.
Fig. 7 shows a schematic diagram of one implementation step for forming body region 26.
Description of the symbols in the drawings
100, 200, 300, 400: high voltage element
11, 21, 31, 41: substrate
12, 22, 32, 42: well region
12a, 22a, 32a, 42 a: drift region
13: insulation structure
13 a: operating area
14, 24, 34, 44: drift oxide region
16, 26, 36, 46: body region
17, 27, 37, 47: grid electrode
18, 28, 38, 48: source electrode
19, 29, 39, 49: drain electrode
21',31',41': semiconductor layer
21a, 31a, 41 a: upper surface of
21b, 31b, 41 b: lower surface
25, 35, 45: shallow trench isolation region
261, 281, 421, 461, 461',481: shielding
271, 471: conductive layer
272, 472: spacer layer
273, 473: dielectric layer
282, 482: lightly doped region
43: channel isolation region
46': channel well region contact pole
Lch: distance between two adjacent plates
Detailed Description
The foregoing and other technical and other features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, which proceeds with reference to the accompanying drawings. The drawings in the present invention are schematic and are intended to show the process steps and the up-down order of the layers, and the shapes, thicknesses and widths are not drawn to scale.
Referring to fig. 2A and fig. 2B, a cross-sectional view and a top view of a high voltage device 200 according to an embodiment of the invention are shown. As shown in fig. 2A and 2B, the high voltage device 200 includes: semiconductor layer 21', well region 22, drift oxide region 24, shallow trench isolation region 25, body region 26, gate 27, source 28, and drain 29. A semiconductor layer 21 'is formed on the substrate 21, and the semiconductor layer 21' has an upper surface 21a and a lower surface 21b opposite to each other in a vertical direction (as indicated by a dotted arrow in fig. 2A, the same applies below). The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21 'is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 is used as the semiconductor layer 21'. The manner of forming the semiconductor layer 21' is well known to those skilled in the art and will not be described herein. In a preferred embodiment, the semiconductor layer 21' is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm. In a preferred embodiment, the high voltage device 200 is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device as shown in FIGS. 2A and 2B, and in a preferred embodiment, the high voltage device 200 has a gate driving voltage of 3.3V and a gate oxide thickness
Figure BDA0003404432210000071
With continued reference to fig. 2A and 2B, a Shallow Trench Isolation (STI) region 25 is formed in the semiconductor layer 21'. The drift oxide region 24 is formed on the semiconductor layer 21' and is located on the drift region 22A (as indicated by the dashed box in fig. 2A). The shallow trench isolation region 25 is located under the drift oxide region 24, and a portion of the drift oxide region 24 is located right above a portion of the shallow trench isolation region 25 and connected to the shallow trench isolation region 25. In one embodiment, the drift oxide region 24, such as but not limited to a local oxidation of silicon (LOCOS) structure as shown in fig. 2A, may also be a chemical vapor deposition (chemical vapor deposition,CVD) oxidation zone. In a preferred embodiment, drift oxide region 24 is a CVD oxide region and has a thickness
Figure BDA0003404432210000081
The well 22 of the first conductivity type is formed in the semiconductor layer 21', and the well 22 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. The well 22 is formed by at least one ion implantation process, for example. The body region 26 of the second conductivity type is formed in the well 22, and the body region 26 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. The gate 27 is formed on the upper surface 21a of the semiconductor layer 21', the gate 27 is substantially rectangular in shape extending along a width direction (as indicated by a solid arrow in fig. 2B, the same applies below) in a top view, and a portion of the body region 26 is located right below the gate 27 and connected to the gate 27 in a vertical direction to provide a reverse current path for the high voltage device 200 in an on operation. The conductive layer 271 of the gate 27 has a first conductive type impurity doping, and is a first conductive type, such as but not limited to a polysilicon structure having the first conductive type impurity doping. In one embodiment, the body region 26 is formed by a self-aligned process including: etching a polysilicon layer to form a conductive layer 271 of the gate 27; and forming the body region 26 by an ion implantation process using the conductive layer 271 as a mask.
The source 28 and the drain 29 have the first conductivity type, in the vertical direction, the source 28 and the drain 29 are formed under the upper surface 21a and connected to the upper surface 21a, and the source 28 and the drain 29 are respectively located in the body region 26 below the gate 27 outside the channel direction (as indicated by the dashed arrow in fig. 2B, the same below) and in the well region 22 away from the body region 26, and in the channel direction, the drift region 22A is located between the drain 29 and the body region 26 and separates the drain 29 from the body region 26 and is located in the well region 22 close to the upper surface 21a for serving as a drift current channel of the high voltage device 200 in the on operation, and as seen in the cross-sectional view of fig. 2A, and in the vertical direction, the source 28 and the drain 29 are located under the upper surface 21a and connected to the upper surface 21 a. In one embodiment, the sti region 25 is between the drain 29 and the body region 26. As shown in fig. 2A, the sti region 25 and the drain 29 are connected in the channel direction.
In one embodiment, a low voltage device is formed on the substrate 21, and the channel length of the low voltage device is 0.18 μm. In one embodiment, the metal process step of the low voltage device is also a 0.18 μm process step, i.e., the minimum metal line (plug) width dimension of the low voltage device is 0.18 μm.
Compared with the prior art, in the high voltage device and the high voltage control device according to the present invention, the insulation structure between the body region 26 and the drain 29 has more shallow trench isolation regions besides the drift oxide region, and at least a portion of the shallow trench isolation regions overlaps the drift oxide region in the vertical projection. As a result, the total oxide region thickness over part of the drift region is increased; when the conduction current of the high-voltage element/the high-voltage control element flows through the drift region, the conduction current needs to downwards pass through the bottom of the shallow trench isolation region, and the length of the conduction current path is increased; in addition, the electric field when the high voltage element/high voltage control element operates can be prevented from concentrating on the surface near the drain electrode, and the electric field distribution can be expanded; both of these factors can increase the breakdown protection voltage. In addition, according to the high-voltage device and the high-voltage control device of the invention, due to the relatively high breakdown protection voltage, under the same electrical specification, the high-voltage device/the high-voltage control device can be reduced in size, so that the on-resistance is reduced.
It should be noted that the inversion current channel refers to a region where an inversion layer (inversion layer) is formed below the gate 27 to pass an on current due to a voltage applied to the gate 27 during the on operation of the high voltage device 200, which is well known to those skilled in the art and will not be described herein.
It should be noted that the drift current path refers to a region through which the on current passes in a drift manner during the on operation of the high voltage device 200, which is well known to those skilled in the art and will not be described herein.
Note that the upper surface 21a does not mean a completely flat plane, but means a surface of the semiconductor layer 21'. In the present embodiment, for example, the portion of the upper surface 21a where the drift oxide region 24 contacts the upper surface 21a has a depressed portion.
It should be noted that the gate 27 includes a conductive layer 271 having conductivity, a dielectric layer 273 connected to the upper surface, and a spacer layer 272 having electrical insulation property, wherein the dielectric layer 273 is formed on the body region 26 and connected to the body region 26. The conductive layer 271, which serves as an electrical contact for the gate 27, is formed over all of the dielectric layers 273 and connected to the dielectric layers 273. Spacer layers 272 are formed on both sides of conductive layer 271 to serve as electrical insulation layers on both sides of gate 27. This is well known to those skilled in the art and will not be described in detail herein.
The above-mentioned "first conductivity type" and "second conductivity type" refer to that in the high voltage device, impurities with different conductivity types are doped in the semiconductor composition region (such as, but not limited to, the well region, the body region, the source and the drain) so that the semiconductor composition region becomes the first or the second conductivity type (such as, but not limited to, the first conductivity type is N type, and the second conductivity type is P type, or vice versa), wherein the first conductivity type and the second conductivity type are electrically opposite to each other.
It should be noted that the high voltage device means that the voltage applied to the drain is higher than a specific voltage, for example, 3.3V, and the channel direction distance (length of the drift region 22 a) between the body region 26 and the drain 29 is adjusted according to the operation voltage applied during normal operation, so that the high voltage device can operate at the higher specific voltage. This is well known to those skilled in the art and will not be described in detail herein.
It should be noted that the term "low voltage device" means that the voltage applied to the drain is lower than a specific voltage, for example, 3.3V, during normal operation.
Fig. 3A and 3B show a cross-sectional view and a top view of a high voltage device 300 according to another embodiment of the invention. The difference between this embodiment and the embodiment of fig. 2A and 2B is that the drift oxide region 34 of this embodiment is a Chemical Vapor Deposition (CVD) oxide region. The substrate 31, the semiconductor layer 31 ', the well region 32, the shallow trench isolation region 35, the body region 36, the gate 37, the source 38, and the drain 39 of the present embodiment are similar to the substrate 21, the semiconductor layer 21', the well region 22, the shallow trench isolation region 25, the body region 26, the gate 27, the source 28, and the drain 29 of fig. 2A and 2B, and thus detailed descriptions thereof are omitted.
Fig. 4A and 4B show a schematic cross-sectional view and a schematic top view of a high voltage control element 400 according to another embodiment of the present invention. As shown in fig. 4A and 4B, the high voltage control device 400 includes: semiconductor layer 41 ', drift well region 42, channel isolation region 43, drift oxide region 44, shallow trench isolation region 45, channel well region 46, channel well region contact 46', gate 47, source 48, and drain 49. A semiconductor layer 41 'is formed on the substrate 41, and the semiconductor layer 41' has an upper surface 41a and a lower surface 41b opposite to each other in a vertical direction (as indicated by a dotted arrow in fig. 4A, the same applies hereinafter). The substrate 41 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 41 'is formed on the substrate 41, for example, by an epitaxial process, or a portion of the substrate 41 is used as the semiconductor layer 41'. The manner of forming the semiconductor layer 41' is well known to those skilled in the art and will not be described herein. In a preferred embodiment, the semiconductor layer 41' is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm. In a preferred embodiment, the high voltage device 400 is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device as shown in FIGS. 4A and 4B, and in a preferred embodiment, the high voltage device 400 has a gate driving voltage of 3.3V and a gate oxide thickness
Figure BDA0003404432210000111
With continued reference to fig. 4A and 4B, STI regions 45 are formed in the semiconductor layer 41'. The drift oxide region 44 is formed on the semiconductor layer 41' and is located on the drift region 42a (as indicated by the dashed box in fig. 4A). Shallow trench isolation region 45 is located under drift oxide region 44, and partial drift oxide region 44 is located right above partial shallow trench isolation region 45 and connected to the shallow trenchA slot exclusion zone 45. In one embodiment, the drift oxide region 44 is, for example, but not limited to, a Chemical Vapor Deposition (CVD) oxide region as shown in fig. 4A, and may also be a local oxidation of silicon (LOCOS) structure. In a preferred embodiment, drift oxide region 44 is a CVD oxide region and has a thickness
Figure BDA0003404432210000112
The drift well region 42 has a first conductivity type, is formed in the semiconductor layer 41', and in the vertical direction, the drift well region 42 is located under the upper surface 41a and connected to the upper surface 41 a. The drift well region 42 is formed, for example, by at least one ion implantation process step. The channel well region 46 having the second conductivity type is formed in the semiconductor layer 41', and the channel well region 46 is located under the upper surface 41a and connected to the upper surface 41a in the vertical direction. The channel well region 46 is formed, for example, by at least one ion implantation process step. Drift well regions 42 are connected to channel well regions 46 in the channel direction (as indicated by the dashed arrow in fig. 4A, the same applies below). The gate 47 is formed on the upper surface 41a of the semiconductor layer 41', the gate 47 is substantially rectangular in shape extending along a width direction (as indicated by a solid arrow in fig. 4B, the same applies below) in a top view, and a portion of the channel well 46 is located right below the gate 47 and connected to the gate 47 in a vertical direction to provide an inversion current path for the high voltage control device 400 during a turn-on operation. The conductive layer 471 of the gate 47 has a first conductive type impurity doping, and is a first conductive type, such as but not limited to a polysilicon structure having the first conductive type impurity doping.
The source 48 and the drain 49 have a first conductive type, in a vertical direction, the source 48 and the drain 49 are formed under the upper surface 41a and connected to the upper surface 41a, and the source 48 and the drain 49 are respectively located in the channel well region 46 under the gate 47 outside the channel direction and in the drift well region 42 away from the channel well region 46, and in the channel direction, the drift region 42a is located between the drain 49 and the channel well region 46 and separates the drain 49 and the channel well region 46, and is located in the drift well region 42 close to the upper surface 41a for serving as a drift current channel of the high voltage control element 400 in an on operation, and as seen in a cross-sectional view of fig. 4A, in the vertical direction, the source 48 and the drain 49 are located under the upper surface 41a and connected to the upper surface 41 a. In one embodiment, the sti region 45 is between the drain 49 and the channel well 46. As shown in fig. 4A, the sti region 45 is connected to the drain 49 in the channel direction. In one embodiment, the distance Lch from the contact between the channel well region 46 and the drift well region 42 to the edge of the source 48 can be adjusted, as shown in fig. 4A.
Referring to fig. 4A, a channel well contact 46' of the second conductivity type is formed in the channel well 46 to serve as an electrical contact for the channel well 46. In the vertical direction, a channel well contact 46 'is formed under the upper surface 41a of the semiconductor layer 41' and connected to the upper surface 41 a. Channel isolation region 43 is formed in channel well 46 between source 48 and channel well contact 46', and channel isolation region 43 is formed under upper surface 41a and connected to upper surface 41 a. In one embodiment, the channel isolation region 43 is, for example, a Shallow Trench Isolation (STI) structure.
In one embodiment, a low voltage device is formed on the substrate 41, and the channel length of the low voltage device is 0.18 μm. In one embodiment, the metal process step of the low voltage device is also a 0.18 μm process step, i.e., the minimum metal line (plug) width dimension of the low voltage device is 0.18 μm.
It should be noted that the inversion current channel refers to a region where an inversion layer (inversion layer) is formed below the gate 47 to pass an on current due to a voltage applied to the gate 47 during the on operation of the high voltage control device 400, which is well known to those skilled in the art and will not be described herein.
It should be noted that the drift current channel refers to a region through which the on current passes in a drift manner during the on operation of the high voltage control device 400, which is well known to those skilled in the art and will not be described herein.
Note that the upper surface 41a does not mean a completely flat plane, but means a surface of the semiconductor layer 41'. In another embodiment, if the drift oxide region 44 is a local oxidation of silicon (LOCOS) structure, the portion of the top surface 41a that contacts the top surface 41a has a depressed portion.
It should be noted that the gate 47 includes a conductive layer 471 having conductivity, a dielectric layer 473 connected to the upper surface, and a spacer 472 having electrical insulation property, wherein the dielectric layer 473 is formed on the channel well region 46 and connected to the channel well region 46. The conductive layer 471 is used as an electrical contact for the gate 47, and is formed on all the dielectric layers 473 and connected to the dielectric layers 473. Spacers 472 are formed on both sides of the conductive layer 471 to serve as electrical insulation layers on both sides of the gate 47. This is well known to those skilled in the art and will not be described in detail herein.
It should be noted that the above-mentioned "first conductivity type" and "second conductivity type" refer to that impurities with different conductivity types are doped in the semiconductor composition region (such as, but not limited to, the above-mentioned drift well region, channel well region, source and drain regions, etc.) in the high voltage control element, so that the semiconductor composition region becomes the first or second conductivity type (such as, but not limited to, the first conductivity type is N type, and the second conductivity type is P type, or vice versa), wherein the first conductivity type and the second conductivity type are electrically opposite to each other.
It should be noted that the high voltage control device means that the voltage applied to the drain is higher than a specific voltage, for example, 3.3V, and the channel direction distance (the length of the drift region 42 a) between the channel well 46 and the drain 49 is adjusted according to the operation voltage applied during normal operation, so that the high voltage control device can operate at the higher specific voltage. This is well known to those skilled in the art and will not be described in detail herein.
It should be noted that the term "low voltage device" means that the voltage applied to the drain is lower than a specific voltage, for example, 3.3V, during normal operation.
Please refer to fig. 5A-5H, which are schematic diagrams illustrating a method for manufacturing the high voltage device 200 according to an embodiment of the invention. As shown in fig. 5A, a semiconductor layer 21' is first formed on a substrate 21. The semiconductor layer 21' is formed on the substrate 21, for example, in an epitaxial stepOr a portion of the substrate 21 is used as the semiconductor layer 21'. The semiconductor layer 21' has an upper surface 21a and a lower surface 21b opposite to each other in a vertical direction (as indicated by a dotted arrow in fig. 5A, the same applies hereinafter). The manner of forming the semiconductor layer 21' is well known to those skilled in the art and will not be described herein. The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor substrate. In a preferred embodiment, the semiconductor layer 21' is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm. In a preferred embodiment, the high voltage device 200 is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device as shown in fig. 2A and 2B, and in a preferred embodiment, the high voltage device 200 has a gate driving voltage of 3.3V and a gate oxide thickness
Figure BDA0003404432210000141
Next, referring to fig. 5B, for example but not limited to, a plurality of ion implantation process steps are performed to dope the first conductive type impurities into the semiconductor layer 21' in the form of accelerated ions to form the well region 22. At this time, the drift oxide region 24 is not formed, and the upper surface 21a is not completely defined. The well 22 is formed in the semiconductor layer 21' and the well 22 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction.
Thereafter, referring to fig. 5C, a shallow trench isolation region 25 is formed in the semiconductor layer 21'. In one embodiment, the shallow trench isolation region 25 is, for example, a Shallow Trench Isolation (STI) structure. Referring to fig. 2A, the sti region 25 is between the drain 29 and the body region 26, and the sti region 25 and the drain 29 are connected in a channel direction (as indicated by the arrow of the horizontal dotted line in fig. 5C, the same applies below).
Next, referring to fig. 5D, a drift oxide region 24 is formed on the upper surface 21a and connected to the upper surface 21 a. The drift oxide region 24 is electrically insulating and is not limited to a local oxidation of silicon (LOCOS) structure as shown in fig. 5D, but may be a Chemical Vapor Deposition (CVD) oxide region. A drift oxidation region 24 is located in the driftThe drift region 22A is connected to the drift region 22A (see fig. 5D and fig. 2A). The shallow trench isolation region 25 is located under the drift oxide region 24, and a portion of the drift oxide region 24 is located right above a portion of the shallow trench isolation region 25 and connected to the shallow trench isolation region 25. In a preferred embodiment, drift oxide region 24 is a CVD oxide region and has a thickness
Figure BDA0003404432210000151
Next, referring to fig. 5E, a body region 26 is formed in the well 22, and the body region 26 is located under the upper surface 21a and connected to the upper surface 21a in the vertical direction. Body region 26 has a second conductivity type and the step of forming body region 26, such as but not limited to, using photoresist layer 261 formed by a photolithography process step as a mask, dopants of the second conductivity type into well region 22 to form body region 26. The present embodiment utilizes, for example but not limited to, an ion implantation process step to implant second conductivity type impurities in the form of accelerated ions into the well region 22, as indicated by the straight dashed arrows in fig. 5E, to form the body region 26.
Next, referring to fig. 5F, a dielectric layer 273 of the gate 27 and a conductive layer 271 are respectively formed on the upper surface 21a of the semiconductor layer 21', and in a vertical direction (as indicated by the arrow of the dotted line in fig. 5F, the same below), a portion of the body region 26 is located right below the gate 27 and connected to the gate 27, so as to provide a reverse current path for the high voltage device 200 during the turn-on operation.
With reference to fig. 5G and fig. 2A, for example, after the dielectric layer 273 and the conductive layer 271 of the gate 27 are formed, the lightly doped region 282 is formed to provide a conduction channel under the spacer layer 272 when the high voltage device 200 is conducted; this is because the body region 26 under the spacer 272 cannot form an inversion current channel when the high voltage device 200 is in the on-state operation. The lightly doped region 282 may be formed by, for example, doping the body region 26 with a first conductivity type dopant to form the lightly doped region 282. In this embodiment, for example, but not limited to, an ion implantation process step may be used to implant the first conductive type impurity into the body region 26 in the form of accelerated ions, as indicated by the vertical dashed arrow in fig. 5G, to form the lightly doped region 282. Since the first conductivity type impurity concentration of the lightly doped region 282 is much lower than that of the source 28, the lightly doped region 282 is omitted in the region where the lightly doped region 282 overlaps the source 28, and thus will be omitted in the subsequent drawings.
Please continue to refer to fig. 5G. As shown in fig. 5G, in the vertical direction, the source 28 and the drain 29 are formed under the upper surface 21a and connected to the upper surface 21a, and the source 28 and the drain 29 are respectively located in the body region 26 under the outside of the gate 27 in the channel direction and in the well region 22 away from the body region 26, and in the channel direction, the drift region 22a is located between the drain 29 and the body region 26 in the well region 22 close to the upper surface 21a for serving as a drift current channel of the high voltage device 200 in the on operation. The source 28 and drain 29 have a first conductivity type, and the source 28 and drain 29 are formed by, for example, but not limited to, using a photoresist layer 281 formed by a photolithography process as a mask to dope the first conductivity type impurities into the body region 26 and the well region 22, respectively, to form the source 28 and drain 29. In this embodiment, for example, but not limited to, an ion implantation process step may be used to implant the first conductive type impurities into the body region 26 and the well region 22 in the form of accelerated ions, as indicated by the vertical dashed arrows in fig. 5G, to form the source 28 and the drain 29.
Then, as shown in fig. 5H, spacers 272 are formed on the outside of the conductive layer 271 to form the gate 27 and thus the high voltage device 200.
Referring to fig. 6A-6I, a method for fabricating a high voltage control device 400 according to another embodiment of the invention is shown. As shown in fig. 6A, a semiconductor layer 41' is first formed on a substrate 41. The semiconductor layer 41 'is formed on the substrate 41, for example, by an epitaxial process, or a portion of the substrate 41 is used as the semiconductor layer 41'. The semiconductor layer 41' has an upper surface 41a and a lower surface 41b opposite to each other in a vertical direction (as indicated by a dotted arrow in fig. 6A, the same applies hereinafter). The manner of forming the semiconductor layer 41' is well known to those skilled in the art and will not be described herein. The substrate 41 is, for example, but not limited to, a P-type or N-type semiconductor substrate. In a preferred embodiment, the semiconductorThe bulk layer 41' is a P-type epitaxial silicon layer and has a resistivity of 45 Ohm-cm. In a preferred embodiment, the high voltage device 400 is a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device as shown in FIGS. 4A and 4B, and in a preferred embodiment, the high voltage device 400 has a gate driving voltage of 3.3V and a gate oxide thickness
Figure BDA0003404432210000171
Next, referring to fig. 6B, for example, but not limited to, by using the photoresist layer 421 formed by the photolithography process as a mask, for example, but not limited to, by using a plurality of ion implantation process steps, the first conductive type impurity is doped into the semiconductor layer 41' in the form of accelerated ions to form the drift well region 42. The drift well region 42 is formed in the semiconductor layer 41', and in the vertical direction, the drift well region 42 is located under the upper surface 41a and connected to the upper surface 41 a.
Referring to fig. 6C, for example, but not limited to, a photoresist layer 461 is formed as a mask by photolithography process steps, and for example, but not limited to, a plurality of ion implantation process steps are used to dope the second conductive type impurity into the semiconductor layer 41' in the form of accelerated ions, so as to form the channel well region 46. The drift oxide region 44 is not yet formed and the upper surface 41a is not yet fully defined. The channel well region 46 is formed in the semiconductor layer 41', and the channel well region 46 is located under the upper surface 41a and connected to the upper surface 41a in the vertical direction. Drift well regions 42 are connected to channel well regions 46 in the channel direction (as indicated by the direction of the lateral dashed arrows in fig. 6C, the same applies below).
Thereafter, referring to fig. 6D, at least one sti region 45 and a channel isolation region 43 are formed in the semiconductor layer 41'. In one embodiment, the shallow trench isolation region 45 is, for example, a Shallow Trench Isolation (STI) structure. In one embodiment, the channel isolation region 43 is, for example, a Shallow Trench Isolation (STI) structure. Referring to fig. 4A, the shallow trench isolation region 45 is between the drain 49 and the channel well 46, and the shallow trench isolation region 45 is connected to the drain 49 in the channel direction. Channel isolation region 43 is between source 48 and channel well contact 46'.
Next, referring to fig. 6E, a drift oxide region 44 is formed on the upper surface 41a and connected to the upper surface 41 a. The drift oxide region 44 is electrically insulating and is not limited to a Chemical Vapor Deposition (CVD) oxide region as shown in fig. 6E, but may be a local oxidation of silicon (LOCOS) structure. The drift oxide region 44 is located on the drift region 42a and connected to the drift region 42a (see fig. 6E and 4A). Shallow trench isolation region 45 is located under drift oxide region 44, and part of drift oxide region 44 is located directly above part of shallow trench isolation region 45 and connected to shallow trench isolation region 45. In a preferred embodiment, drift oxide region 44 is a CVD oxide region and has a thickness
Figure BDA0003404432210000181
Next, referring to fig. 6F, a dielectric layer 473 and a conductive layer 471 of the gate 47 are respectively formed on the upper surface 41a of the semiconductor layer 41', and in a vertical direction (as indicated by the arrow of the dotted line in fig. 6F, the same below), a portion of the channel well 46 is located right below the gate 47 and connected to the gate 47, so as to provide a reverse current path for the high voltage control element 400 during the on operation.
With reference to fig. 6G and fig. 4A, for example, after forming the dielectric layer 473 and the conductive layer 471 of the gate 47, a lightly doped region 482 is formed to provide a conduction channel under the spacer layer 472 during the conduction operation of the high voltage control device 400; this is because the channel well 46 under the spacer layer 472 cannot form an inversion current channel during the on operation of the high voltage control device 400. The lightly doped region 482 is formed by, for example, doping impurities of the first conductivity type into the channel well region 46 to form the lightly doped region 482. In this embodiment, for example, but not limited to, an ion implantation process step may be used to implant the first conductive type impurity into the channel well region 46 in the form of accelerated ions, as indicated by the vertical dashed arrow in fig. 6G, so as to form the lightly doped region 482. Since the first conductivity type impurity concentration of the lightly doped region 482 is much lower than the first conductivity type impurity concentration of the source 48 and the second conductivity type impurity concentration of the channel well contact 46 ', the lightly doped region 482 can be omitted in the region where the lightly doped region 482 overlaps the source 48 and the channel well contact 46', and thus will be omitted in the subsequent drawings.
Please continue to refer to fig. 6G. As shown in fig. 6G, a source 48 and a drain 49 are formed under the upper surface 41a and connected to the upper surface 41a in the vertical direction, and the source 48 and the drain 49 are respectively located in the channel well region 46 under the gate 47 at the outer portion of the channel direction and in the drift well region 42 at the side far from the channel well region 46, and in the channel direction, the drift region 42a is located between the drain 49 and the channel well region 46 in the drift well region 42 near the upper surface 41a for serving as a drift current channel of the high voltage control element 400 in the on operation. The source 48 and drain 49 have a first conductivity type, and the source 48 and drain 49 are formed by, for example, but not limited to, doping impurities of the first conductivity type into the channel well 46 and the drift well 42, respectively, using a photoresist layer 481 formed by a photolithography process step as a mask, to form the source 48 and drain 49. In this embodiment, for example, but not limited to, an ion implantation process may be performed to implant the first conductive type impurity in the channel well region 46 and the drift well region 42 in the form of accelerated ions, as indicated by the vertical dashed arrows in fig. 6G, to form the source 48 and the drain 49.
Next, as shown in fig. 6H, a channel well contact 46' is formed in the channel well 46 to serve as an electrical contact for the channel well 46. In the vertical direction, a channel well contact 46' is located below the upper surface 41a and connected to the upper surface 41 a. The channel well contact 46 'has the second conductivity type, and the step of forming the channel well contact 46' such as, but not limited to, masking by the photoresist layer 461 'formed by the photolithography process step, dopants of the second conductivity type into the channel well 46 respectively to form the channel well contact 46'. In this embodiment, for example, but not limited to, an ion implantation process may be performed to implant the second conductive type impurity into the channel well 46 in the form of accelerated ions, as indicated by the vertical dashed arrows in fig. 6H, to form the channel well contact 46'.
Next, as shown in fig. 6I, spacers 472 are formed on the sides of the conductive layer 471 to form the gate 47, and thus the high voltage control device 400 is formed.
Fig. 7 is a schematic diagram illustrating an implementation step of forming the body region 26 in a method of manufacturing the high voltage device 200 according to an embodiment of the invention. In the present embodiment, other steps of the method for manufacturing the high voltage device 200 can be seen in fig. 5A to 5D and fig. 5F to 5H.
The present embodiment differs from fig. 5A-5H in that in the present embodiment, the body region 26 is formed by a self-aligned process step, wherein the self-aligned process step includes: etching a polysilicon layer to form a conductive layer 271 of the gate 27; and forming the body region 26 by an ion implantation process using the conductive layer 271 as a mask.
As shown in fig. 7, a dielectric layer 273 and a conductive layer 271 of the gate 27 are formed. The dielectric layer 273 and the conductive layer 271 are formed by, for example, etching a silicon dioxide layer and a polysilicon layer, respectively, to form the dielectric layer 273 and the conductive layer 271. The conductive layer 271 is used as a mask, and as shown in fig. 7, a photoresist layer 261 is added as a mask to dope the second conductive type impurities into the well 22, so as to form the body region 26. The present embodiment utilizes, for example but not limited to, an ion implantation process step to implant second conductivity type impurities in the form of accelerated ions into well region 22, as indicated by the diagonal dashed arrows in fig. 7, to form body region 26. Note that, in order to form part of the body region 26 under the gate 27, the accelerated ion incident direction needs to be inclined at a predetermined angle with respect to the normal of the well region 22, so that part of the second conductive type impurity is implanted under the gate 27.
It is noted that one of the technical features of the present invention over the prior art is that: according to the present invention, taking the embodiment shown in fig. 2A and fig. 2B as an example, by disposing the shallow trench isolation region 25 in the drift region 22A of the high voltage device 200 on the drain 29 side and matching with the drift oxide region 24 above the shallow trench isolation region 25, the on-resistance of the high voltage device 200 can be reduced and the breakdown protection voltage of the high voltage device 200 can be increased. In addition, the high voltage device 200 of the present invention can be manufactured by standard high voltage device process steps without additional photolithography process steps, and thus the manufacturing cost is the same as that of the prior art.
The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as deep well regions, may be added without affecting the primary characteristics of the device; for example, the lithography technique is not limited to the mask technique, but may include electron beam lithography. All of which can be analogized to the teachings of the present invention. In addition, the embodiments described are not limited to a single application, and may be combined, for example, but not limited to, a combination of both embodiments. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above. Furthermore, it is not necessary for any embodiment of the invention to achieve all of the objects or advantages, and thus, any one of the claims should not be limited thereby.

Claims (30)

1. A high voltage device, comprising:
a semiconductor layer formed on a substrate;
a well region of a first conductivity type formed in the semiconductor layer;
a shallow trench isolation region formed in the semiconductor layer;
a drift oxide region formed on the semiconductor layer, wherein the shallow trench isolation region is located under the drift oxide region, and a part of the drift oxide region is located right above a part of the shallow trench isolation region and connected with the shallow trench isolation region, wherein the drift oxide region is located on a drift region;
a body region of a second conductivity type formed in the semiconductor layer, the body region being connected to the well region in a channel direction;
a gate formed on the semiconductor layer, wherein a part of the body region is located right below the gate and connected to the gate to provide a reverse current channel for the high voltage device in a turn-on operation, and another part of the gate is located right above the drift oxide region and connected to the drift oxide region; and
a source and a drain of the first conductivity type, the source and the drain being formed in the semiconductor layer and located in the body region under the outside of the gate and the well region away from the body region side, respectively, and the drift region being located in the well region between the drain and the body region in the channel direction for serving as a drift current channel of the high voltage device in the turn-on operation;
wherein the shallow trench isolation region is between the drain and the body region.
2. The high voltage device of claim 1, wherein the drift oxide region comprises a local oxide structure or a CVD oxide region.
3. The high voltage device of claim 1, wherein the STI region is connected to the drain in the channel direction.
4. The high voltage device of claim 1, wherein the semiconductor layer is a P-type epitaxial silicon layer and has an ohmic resistance of 45 Ohm-cm.
5. The high voltage device of claim 2, wherein the drift oxide region comprises the CVD oxide region, and the CVD oxide region has a thickness
Figure FDA0003404432200000021
6. The high-voltage device as claimed in claim 1, wherein the high-voltage device is a LDMOS device having a gate driving voltage of 3.3V and a gate oxide thickness
Figure FDA0003404432200000022
7. The high-voltage device as claimed in claim 6, wherein a low-voltage device is formed on the substrate, and the channel length of the low-voltage device is 0.18 μm.
8. The high voltage device of claim 1, wherein the body region is formed by a self-aligned process step, wherein the self-aligned process step comprises: etching a polysilicon layer to form a conductive layer of the gate; and forming the body region by an ion implantation process step with the conductive layer as a mask.
9. A method for fabricating a high voltage device, comprising:
forming a semiconductor layer on a substrate;
forming a well region in the semiconductor layer, the well region having a first conductivity type;
forming at least one shallow trench isolation region in the semiconductor layer;
forming a drift oxide region on the semiconductor layer, wherein the shallow trench isolation region is located below the drift oxide region, and part of the drift oxide region is located right above part of the shallow trench isolation region and connected with the shallow trench isolation region, and the drift oxide region is located on a drift region;
forming a body region in the semiconductor layer, the body region being connected to the well region in a channel direction, the body region having a second conductivity type;
forming a gate on the semiconductor layer, wherein a portion of the body region is located directly under the gate and connected to the gate to provide a reverse current path for the high voltage device during a turn-on operation, and another portion of the gate is located directly above the drift oxide region and connected to the drift oxide region; and
forming a source electrode and a drain electrode in the semiconductor layer, wherein the source electrode and the drain electrode are respectively positioned in the body region below the outer part of the grid electrode and the well region far away from the body region side, and in the channel direction, the drift region is positioned in the well region between the drain electrode and the body region and is used as a drift current channel of the high-voltage element in the conducting operation;
wherein the shallow trench isolation region is between the drain and the body region.
10. The method of claim 9, wherein the drift oxide region comprises a local oxide structure or a CVD oxide region.
11. The method of claim 9, wherein the STI region is connected to the drain in the channel direction.
12. The method of claim 9, wherein the semiconductor layer is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm.
13. The method of claim 10, wherein the drift oxide region comprises the CVD oxide region having a thickness
Figure FDA0003404432200000031
Figure FDA0003404432200000032
14. The method of claim 9, wherein the high voltage device is a LDMOS device having a gate drive voltage of 3.3V and a gate oxide thickness
Figure FDA0003404432200000033
15. The method of claim 14, wherein a low voltage device is formed on the substrate, and the channel length of the low voltage device is 0.18 μm.
16. The method of claim 9, wherein the body region is formed by a self-aligned process, wherein the self-aligned process comprises: etching a polysilicon layer to form a conductive layer of the gate; and forming the body region by an ion implantation process step with the conductive layer as a mask.
17. A high voltage control device, comprising:
a semiconductor layer formed on a substrate;
a drift well region of a first conductivity type formed in the semiconductor layer;
a channel well region of a second conductivity type formed in the semiconductor layer, the drift well region being connected to the channel well region in a channel direction;
a shallow trench isolation region formed in the semiconductor layer;
a drift oxide region formed on the semiconductor layer, wherein the shallow trench isolation region is located under the drift oxide region, and a part of the drift oxide region is located right above a part of the shallow trench isolation region and connected with the shallow trench isolation region, wherein the drift oxide region is located on a drift region;
a gate formed on the semiconductor layer, wherein a part of the channel well region is located right below the gate and connected to the gate to provide an inversion current channel of the high voltage control element in a turn-on operation, and another part of the gate is located right above the drift oxide region and connected to the drift oxide region;
a source electrode and a drain electrode of the first conductivity type, the source electrode and the drain electrode being formed in the semiconductor layer, and the source electrode and the drain electrode being respectively located in the channel well region under the outside of the gate electrode and in the drift well region away from the channel well region side, and in the channel direction, the drift region being located in the drift well region between the drain electrode and the channel well region to serve as a drift current channel of the high voltage control element in the turn-on operation;
a channel well region contact electrode of the second conductivity type formed in the channel well region for serving as an electrical contact of the channel well region, the channel well region contact electrode being formed under and connected to an upper surface of the semiconductor layer in a vertical direction; and
a channel isolation region formed in the semiconductor layer and located between the source electrode and the channel well region contact electrode, the channel isolation region being formed below and connected to the upper surface;
wherein the shallow trench isolation region is between the drain and the channel well region.
18. The device of claim 17, wherein the drift oxide region comprises a local oxide structure or a cvd oxide region.
19. The device of claim 17, wherein the STI region is connected to the drain in the channel direction.
20. The device of claim 17, wherein said semiconductor layer is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm.
21. The high voltage control element of claim 18, wherein the drift oxide region comprises the cvd oxide region and the cvd oxide region has a thickness
Figure FDA0003404432200000051
Figure FDA0003404432200000052
22. The device of claim 17, wherein the high voltage device is a LDMOS device having a gate drive voltage of 3.3V and a gate oxide thickness
Figure FDA0003404432200000053
23. The high voltage control device of claim 22, wherein a low voltage device is formed on the substrate, and the channel length of the low voltage device is 0.18 μm.
24. A method for manufacturing a high voltage control device, comprising:
forming a semiconductor layer on a substrate;
forming a drift well region in the semiconductor layer, the drift well region having a first conductivity type;
forming a channel well region in the semiconductor layer, the channel well region having a second conductivity type, the drift well region being connected to the channel well region in a channel direction;
forming at least one shallow trench isolation region in the semiconductor layer and a channel isolation region in the semiconductor layer, the channel isolation region being formed below and connected to an upper surface of the semiconductor layer;
forming a drift oxide region on the semiconductor layer, wherein the shallow trench isolation region is located below the drift oxide region, and part of the drift oxide region is located right above part of the shallow trench isolation region and connected with the shallow trench isolation region, and the drift oxide region is located on a drift region;
forming a gate on the semiconductor layer, wherein a part of the channel well region is located right below the gate and connected to the gate to provide an inversion current channel of the high voltage control element in a turn-on operation, and another part of the gate is located right above the drift oxide region and connected to the drift oxide region; and
forming a source electrode and a drain electrode in the semiconductor layer, wherein the source electrode and the drain electrode are respectively positioned in the channel well region under the outer part of the grid electrode and the drift well region far away from the channel well region side, and in the channel direction, the drift region is positioned in the drift well region between the drain electrode and the channel well region and is used as a drift current channel of the high-voltage control element in the conducting operation; and
forming a channel well region contact electrode in the channel well region, the channel well region contact electrode having the second conductivity type and serving as an electrical contact of the channel well region, the channel well region contact electrode being formed under and connected to the upper surface in a vertical direction;
the shallow groove isolation region is arranged between the drain electrode and the channel well region, and the channel isolation region is arranged between the source electrode and the contact electrode of the channel well region.
25. The method of claim 24, wherein the drift oxide region comprises a local oxide structure or a CVD oxide region.
26. The method of claim 24, wherein the STI region is connected to the drain in the channel direction.
27. The method of claim 24, wherein the semiconductor layer is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm.
28. The method of claim 25, wherein the drift oxide region comprises the CVD oxide region having a thickness
Figure FDA0003404432200000061
29. The method of claim 24, wherein the high voltage device is a LDMOS device having a gate drive voltage of 3.3V and a gate oxide thickness
Figure FDA0003404432200000062
30. The method of claim 29, wherein a low voltage device is formed on the substrate, and the channel length of the low voltage device is 0.18 μm.
CN202111508737.0A 2021-01-08 2021-12-10 High voltage element, high voltage control element and manufacturing method thereof Pending CN114759092A (en)

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