CN114758625B

CN114758625B - Display substrate and display device

Info

Publication number: CN114758625B
Application number: CN202210429772.1A
Authority: CN
Inventors: 郭永林
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-04-22
Filing date: 2022-04-22
Publication date: 2024-03-12
Anticipated expiration: 2042-04-22
Also published as: CN114758625A

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a plurality of rows and columns of pixel circuits arranged in a display area of the substrate, wherein the pixel circuits comprise a light-emitting element, a driving circuit, a compensation control circuit, a first initialization circuit and a regulating circuit; the compensation control circuit is used for controlling the communication between the control end of the driving circuit and the first end of the driving circuit under the control of the compensation control signal; the first initialization circuit controls writing of a first initial voltage into a control end of the driving circuit under the control of a reset control signal; the adjusting circuit is electrically connected with the compensation control circuit and/or the first initializing circuit; the adjusting circuit is also electrically connected with the control end of the driving circuit and used for adjusting the electric potential of the control end of the driving circuit. The invention can solve the problem of flicker in low-frequency display.

Description

Display substrate and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display substrate and a display device.

Background

In the related art, the organic light emitting diode (Organic Light Emitting Diode, OLED) display has the advantages of self-luminescence, light weight, low power consumption, fast response speed, wide viewing angle and the like while having good flexibility, so that the organic light emitting diode (Organic Light Emitting Diode, OLED) display is widely applied to various fields and has wide development prospect.

Disclosure of Invention

The invention mainly aims to provide a display substrate and a display device, which solve the problem of low-frequency display flicker.

The embodiment of the invention provides a display substrate, which comprises a plurality of rows and columns of pixel circuits arranged in a display area of a substrate, wherein the pixel circuits comprise a light-emitting element, a driving circuit, a compensation control circuit, a first initialization circuit and an adjusting circuit;

the compensation control circuit is respectively and electrically connected with the compensation control line, the control end of the driving circuit and the first end of the driving circuit and is used for controlling the communication between the control end of the driving circuit and the first end of the driving circuit under the control of the compensation control signal provided by the compensation control line;

the first end of the driving circuit is electrically connected with the first pole of the light-emitting element, and the driving circuit is used for generating driving current for driving the light-emitting element under the control of the potential of the control end of the driving circuit;

the first initialization circuit is respectively and electrically connected with the reset control line, the first initial voltage line and the control end of the driving circuit and is used for controlling the first initial voltage provided by the first initial voltage line to be written into the control end of the driving circuit under the control of the reset control signal provided by the reset control line;

The adjusting circuit is electrically connected with the compensation control circuit, and/or the adjusting circuit is electrically connected with the first initializing circuit;

the adjusting circuit is also electrically connected with the control end of the driving circuit and used for adjusting the electric potential of the control end of the driving circuit.

Optionally, the transistor included in the compensation control circuit is a double-gate transistor, and the adjusting circuit includes a first adjusting circuit; the first end of the first regulating circuit is electrically connected with the middle node of the transistor included in the compensation control circuit, the second end of the first regulating circuit is electrically connected with the control end of the driving circuit, and the first regulating circuit is used for regulating the potential of the control end of the driving circuit according to the potential of the middle node of the transistor included in the compensation control circuit; and/or the number of the groups of groups,

the transistor that first initialization circuit included is the double-gate transistor, regulating circuit still includes second regulating circuit, second regulating circuit's first end with the intermediate node electricity of the transistor that first initialization circuit included is connected, second regulating circuit's second end with driving circuit's control end electricity is connected, second regulating circuit is used for according to the potential of the intermediate node of the transistor that first initialization circuit included, adjusts driving circuit's control end.

Optionally, the compensation control circuit includes a first transistor, and the first adjusting circuit includes a first capacitor; the first transistor is a double-gate transistor;

the first grid electrode of the first transistor and the second grid electrode of the first transistor are electrically connected with the compensation control line, the first electrode of the first transistor is electrically connected with the control end of the driving circuit, and the second electrode of the first transistor is electrically connected with the first end of the driving circuit;

the first polar plate of the first capacitor is electrically connected with the middle node of the first transistor, and the second polar plate of the first capacitor is electrically connected with the control end of the driving circuit.

Optionally, the display substrate includes a semiconductor layer, a first gate metal layer, and a source drain metal layer sequentially stacked along a direction away from the substrate; the first transistor comprises a first grid electrode, a second grid electrode and an active layer; the active layer of the first transistor comprises a first electrode, a second electrode, a first channel region, a second channel region and an intermediate active layer pattern arranged between the first channel region and the second channel region;

the intermediate active layer pattern of the first transistor, the first channel region of the first transistor, and the second channel region of the first transistor are all included in the semiconductor layer;

The first gate electrode of the first transistor and the second gate electrode of the first transistor are both included in the first gate metal layer, and the first electrode of the first transistor and the second electrode of the first transistor are both included in the semiconductor layer;

the middle active layer graph of the first transistor is multiplexed into a first polar plate of the first capacitor, a second polar plate of the first capacitor is contained in the source drain metal layer, and the first polar plate of the first capacitor and the second polar plate of the first capacitor are oppositely arranged.

Optionally, the display substrate includes a semiconductor layer, a first gate metal layer, and a source drain metal layer sequentially stacked along a direction away from the substrate; the first transistor comprises a first grid electrode, a second grid electrode and an active layer; the active layer of the first transistor comprises a first channel region, a second channel region and an intermediate active layer pattern arranged between the first channel region and the second channel region;

The middle active layer graph of the first transistor is multiplexed into a first polar plate of the first capacitor, a second polar plate of the first capacitor is contained in the first grid metal layer, and the first polar plate of the first capacitor and the second polar plate of the first capacitor are oppositely arranged.

Optionally, the first initializing circuit includes a second transistor, and the second adjusting circuit includes a second capacitor; the second transistor is a double-gate transistor;

the first grid electrode of the second transistor and the second grid electrode of the second transistor are electrically connected with the reset control line, the first electrode of the second transistor is electrically connected with the first initial voltage line, and the second electrode of the second transistor is electrically connected with the control end of the driving circuit;

the first polar plate of the second capacitor is electrically connected with the middle node of the second transistor, and the second polar plate of the second capacitor is electrically connected with the control end of the driving circuit.

Optionally, the display substrate includes a semiconductor layer, a first gate metal layer, and a source drain metal layer sequentially stacked along a direction away from the substrate; the second transistor includes a first gate electrode, a second gate electrode, and an active layer; the active layer of the second transistor comprises a first channel region, a second channel region and an intermediate active layer pattern arranged between the first channel region and the second channel region;

The middle active layer pattern of the second transistor, the first channel region of the second transistor and the second channel region of the second transistor are all included in the semiconductor layer;

the first gate electrode of the second transistor and the second gate electrode of the second transistor are both included in the first gate metal layer, and the first electrode of the second transistor and the second electrode of the second transistor are both included in the semiconductor layer;

the middle active layer graph of the second transistor is multiplexed into a first polar plate of the second capacitor, the second polar plate of the first capacitor is contained in the source drain metal layer, and the first polar plate of the second capacitor and the second polar plate of the second capacitor are oppositely arranged.

the middle active layer graph of the second transistor is multiplexed into a first polar plate of the second capacitor, the second polar plate of the second capacitor is contained in the first grid metal layer, and the first polar plate of the second capacitor and the second polar plate of the second capacitor are oppositely arranged.

Optionally, the pixel circuit further includes an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, and a data writing circuit;

the first end of the energy storage circuit is electrically connected with the control end of the driving circuit, the second end of the energy storage circuit is electrically connected with a first voltage line, and the energy storage circuit is used for storing electric energy;

the first light emitting control circuit is respectively and electrically connected with the light emitting control line, the first voltage line and the second end of the driving circuit and is used for controlling the communication between the first voltage line and the second end of the driving circuit under the control of the light emitting control signal provided by the light emitting control line;

The second light-emitting control circuit is respectively and electrically connected with the light-emitting control line, the first end of the driving circuit and the first electrode of the light-emitting element and is used for controlling the first end of the driving circuit to be communicated with the first electrode of the light-emitting element under the control of the light-emitting control signal; a second electrode of the light emitting element is electrically connected to a second voltage line;

the data writing circuit is electrically connected with the writing control line, the data line and the second end of the driving circuit respectively and is used for controlling the data voltage provided by the data line to be written into the second end of the driving circuit under the control of the writing control signal provided by the writing control line.

Optionally, the pixel circuit further includes a second initialization circuit;

the second initialization circuit is electrically connected with the initial control line, the second initial voltage line and the first electrode of the light emitting element respectively, and is used for writing the second initial voltage provided by the second initial voltage line into the first electrode of the light emitting element under the control of the initial control signal provided by the initial control line.

Optionally, the compensation control line, the write control line and the initial control line access the same control signal.

Optionally, the first light emitting control circuit includes a third transistor, the second light emitting control circuit includes a fourth transistor, the data writing circuit includes a fifth transistor, the second initializing circuit includes a sixth transistor, the driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;

the gate of the driving transistor is a control end of the driving circuit, the first electrode of the driving transistor is a first end of the driving circuit, and the second electrode of the driving transistor is a second end of the driving circuit;

a gate electrode of the third transistor is electrically connected to the light emission control line, a first electrode of the third transistor is electrically connected to the first voltage line, and a second electrode of the third transistor is electrically connected to the second electrode of the driving transistor;

a gate electrode of the fourth transistor is electrically connected to the light emission control line, a first electrode of the fourth transistor is electrically connected to the first electrode of the driving transistor, and a second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element;

a gate electrode of the fifth transistor is electrically connected with the write control line, a first electrode of the fifth transistor is electrically connected with the data line, and a second electrode of the fifth transistor is electrically connected with a second electrode of the driving transistor;

A gate of the sixth transistor is electrically connected to the initial control line, a first electrode of the sixth transistor is electrically connected to the second initial voltage line, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element;

the first polar plate of the storage capacitor is electrically connected with the grid electrode of the driving transistor, and the second polar plate of the storage capacitor is electrically connected with the first voltage line.

Optionally, the display substrate includes a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source drain metal layer that are sequentially stacked along a direction away from the substrate;

the first polar plate of the storage capacitor is contained in the first grid metal layer and is multiplexed to be the grid electrode of the driving transistor; the second plate of the storage capacitor is contained in the second grid metal layer;

the gate electrode of the driving transistor, the gate electrode of the third transistor, the gate electrode of the fourth transistor, the gate electrode of the fifth transistor and the gate electrode of the sixth transistor are all included in the first gate metal layer;

the channel region of the driving transistor, the first electrode of the driving transistor, the second electrode of the driving transistor, the channel region of the third transistor, the first electrode of the third transistor, the second electrode of the third transistor, the channel region of the fourth transistor, the first electrode of the fourth transistor, the second electrode of the fourth transistor, the channel region of the fifth transistor, the first electrode of the fifth transistor, the second electrode of the fifth transistor, the channel region of the sixth transistor, the first electrode of the sixth transistor, and the second electrode of the sixth transistor are all included in the semiconductor layer;

The data line and the first voltage line are included in the source drain metal layer.

Optionally, the compensation control line, the writing control line and the initial control line are all scanning lines, and the scanning lines, the reset control line and the light emitting control line are all included in the first gate metal layer;

the first initial voltage line and the second initial voltage line are the same initial voltage line, and the initial voltage line is contained in the second gate metal layer.

The embodiment of the invention also provides a display device which comprises the display substrate.

The display substrate and the display device provided by the embodiment of the invention are provided with the regulating circuit, and the regulating circuit can comprise a capacitor for regulating the potential of the control end of the driving circuit, so that the variation of the potential of the control end of the driving circuit in a light-emitting stage can be reduced, the brightness retention rate in one frame time is improved, and the display flickering phenomenon under low frequency is further improved.

Drawings

Fig. 1 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 3 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 4 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 5 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 6 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 7 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 8 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 9 is a block diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 10 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 11 is a circuit diagram of at least one embodiment of the pixel circuit of FIG. 10 in accordance with the present invention;

FIG. 12 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the invention;

FIG. 14 is a schematic diagram of an addition of a reference number to a counter electrode based on at least one embodiment of the pixel circuit shown in FIG. 10;

fig. 15 is a layout of the active layer in fig. 19;

fig. 16 is a layout view of the first gate metal layer of fig. 19;

fig. 17 is a layout view of the second gate metal layer in fig. 19;

the layout of the source drain metal layer in fig. 19 of fig. 18;

FIG. 19 is a layout of at least one embodiment of the pixel circuit shown in FIG. 14;

fig. 20 is a layout of the active layer in fig. 24;

fig. 21 is a layout view of the first gate metal layer in fig. 24;

fig. 22 is a layout of the second gate metal layer of fig. 24;

fig. 23 is a layout of the source drain metal layer in fig. 24;

FIG. 24 is a layout diagram of at least one embodiment of a pixel circuit as shown in FIG. 14.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics.

In an embodiment of the present invention, the transistor may include a gate electrode and an active layer; the active layer may include a first electrode, a second electrode, and a channel region; the overlapping portion of the active layer and the gate electrode is a channel region of a transistor, and the channel region is used for electrically connecting the first electrode and the second electrode.

In the embodiment of the present invention, the first electrode may be a source electrode, and the second electrode may be a drain electrode; alternatively, the first electrode may be a drain electrode and the second electrode may be a source electrode.

The display substrate comprises a plurality of rows and columns of pixel circuits arranged in a display area of a substrate, wherein the pixel circuits comprise a light-emitting element, a driving circuit, a compensation control circuit and an adjusting circuit;

In the display substrate according to the embodiment of the present invention, the adjusting circuit may adjust the potential of the control end of the driving circuit according to the potential of the intermediate node of the transistor included in the compensation control circuit and/or the potential of the intermediate node of the transistor included in the first initializing circuit.

In at least one embodiment of the present invention, the light emitting element may be an organic light emitting diode, and the first electrode of the light emitting element may be an anode of the organic light emitting diode, but is not limited thereto.

In at least one embodiment of the present invention, when the pixel circuit is in operation, the display period may include an initialization phase and a compensation phase that are sequentially set;

in the initialization stage, the first initialization circuit controls the writing of a first initial voltage into the control end of the driving circuit under the control of a reset control signal so that a driving transistor included in the driving circuit can be conducted when the compensation stage begins;

In the compensation stage, the compensation control circuit controls the communication between the control end of the driving circuit and the first end of the driving circuit under the control of the compensation control signal so as to compensate the threshold voltage of the driving transistor.

When an OLED (organic light emitting diode) display panel is in operation, the main reason for displaying flicker is that the potential of the control end of the driving circuit changes in a frame time, the transistors included in the compensation control circuit and the transistors included in the first initialization circuit are both double-gate transistors, the potential of the middle node of the transistor included in the compensation control circuit is subjected to voltage jump by the coupling action of the transistor in the light emitting stage, the potential of the middle node of the transistor included in the first initialization circuit is subjected to voltage jump by the coupling action of the transistor, which causes a relatively large leakage current between the transistor included in the compensation control circuit and the transistor included in the first initialization circuit, a part of leakage current paths are connected with the control end of the driving circuit, and the potential of the control end of the driving circuit is caused to have a relatively large voltage difference in a frame time, so that the flicker phenomenon is serious. Based on this, the embodiment of the invention increases the adjusting circuit, and the adjusting circuit may include a capacitor for adjusting the potential of the control end of the driving circuit, so as to reduce the variation of the potential of the control end of the driving circuit in the light emitting stage, improve the brightness retention rate in one frame time, and further improve the flicker phenomenon displayed at low frequency.

In at least one embodiment of the present invention, the transistor included in the compensation control circuit is a double-gate transistor, and the adjusting circuit includes a first adjusting circuit; the first end of the first regulating circuit is electrically connected with the middle node of the transistor included in the compensation control circuit, the second end of the first regulating circuit is electrically connected with the control end of the driving circuit, and the first regulating circuit is used for regulating the potential of the control end of the driving circuit according to the potential of the middle node of the transistor included in the compensation control circuit; and/or the number of the groups of groups,

Optionally, the first initializing circuit includes a second transistor, and the second adjusting circuit includes a second capacitor; the second transistor is a double-gate transistor; the second transistor comprises a first gate and a second gate;

As shown in fig. 1, the display substrate according to the embodiment of the present invention includes a plurality of rows and columns of pixel circuits disposed in a display area of a substrate, and at least one embodiment of the pixel circuits includes a light emitting element 10, a driving circuit 11, a compensation control circuit 12, a first initialization circuit 13, and a regulating circuit; the conditioning circuit includes a first conditioning circuit 141;

the compensation control circuit 12 is electrically connected to the compensation control line B1, the control end of the driving circuit 11, and the first end of the driving circuit 11, and is configured to control the communication between the control end of the driving circuit 11 and the first end of the driving circuit 11 under the control of the compensation control signal provided by the compensation control line B1;

a first end of the driving circuit 11 is electrically connected with a first pole of the light emitting element 10, and the driving circuit 11 is used for generating a driving current for driving the light emitting element 10 under the control of the electric potential of a control end thereof;

the first initializing circuit 13 is electrically connected to the reset control line R1, the first initial voltage line I1, and the control terminal of the driving circuit 11, and is configured to control writing of the first initial voltage Vinit1 provided by the first initial voltage line I1 into the control terminal of the driving circuit 11 under the control of the reset control signal provided by the reset control line R1;

The compensation control circuit 12 includes a first transistor T1;

the first gate of the first transistor T1 and the second gate of the first transistor T1 are electrically connected to the compensation control line B1, the drain of the first transistor T1 is electrically connected to the control terminal of the driving circuit 11, and the source of the first transistor T1 is electrically connected to the first terminal of the driving circuit;

a first end of the first adjusting circuit 141 is electrically connected to the intermediate node T1M of the first transistor T1, and a second end of the first adjusting circuit 141 is electrically connected to the control end of the driving circuit 11;

the first adjusting circuit 141 is configured to adjust the potential of the control terminal of the driving circuit 11 according to the potential of the intermediate node T1M of the first transistor T1.

In fig. 1, a first node is denoted by N1 and is electrically connected to a control terminal of the driving circuit 11.

In operation of at least one embodiment of the pixel circuit shown in fig. 1, in the light emitting stage, the potential of the compensation control signal provided by the compensation control line B1 rises from a low voltage to a high voltage, the potential of the T1M rises, when the T1 leaks, the potential of the first node N1 is pulled up, the potential of the T2M gradually decreases, the potential of the first node N1 decreases due to the effect of the first adjusting circuit 141, and the potential of the first node N1 is stabilized within one frame through the above self-feedback process, so that the flicker of the light emitting element is improved;

When the potential of the first node N1 drops due to the leakage of T1, the potential of T1M gradually rises, and the potential of the first node N1 rises due to the effect of the first adjusting circuit 141, so that the potential of the first node N1 is stabilized within one frame through the above self-feedback process, and the flicker of the light emitting element is improved.

As shown in fig. 2, the display substrate according to the embodiment of the present invention includes a plurality of rows and columns of pixel circuits disposed in a display area of a substrate, and at least one embodiment of the pixel circuits includes a light emitting element 10, a driving circuit 11, a compensation control circuit 12, a first initialization circuit 13, and a regulating circuit; the conditioning circuit includes a second conditioning circuit 142;

the driving circuit 11 is used for generating a driving current for driving the light-emitting element 10 under the control of the potential of the control end;

the first initialization circuit 13 includes a second transistor T2;

the first gate of the second transistor T2 and the second gate of the second transistor T2 are electrically connected to the compensation control line B1, the drain of the second transistor T2 is electrically connected to the first initial voltage line I1, and the source of the second transistor T2 is electrically connected to the control terminal of the driving circuit 11;

a first end of the second adjusting circuit 142 is electrically connected to the intermediate node T2M of the second transistor T2, and a second end of the second adjusting circuit 142 is electrically connected to the control end of the driving circuit 11;

the second adjusting circuit 142 is configured to adjust the potential of the control terminal of the driving circuit 11 according to the potential of the intermediate node T2M of the second transistor T2.

In fig. 2, the reference number N1 is a first node electrically connected to the control terminal of the driving circuit 11.

In operation, at least one embodiment of the pixel circuit shown in fig. 2, in the light-emitting stage, when the potential of the first node N1 decreases due to the leakage of T2, the potential of T2M gradually increases, and the potential of the first node N1 increases due to the action of the second adjusting circuit 142, so that the potential of the first node N1 is stabilized within one frame through the above self-feedback process, and the flicker of the light-emitting element is improved;

when the potential of the first node N1 rises due to the leakage of T2, the potential of T2M gradually drops, and the potential of the first node N1 drops due to the second adjusting circuit 142, so that the potential of the first node N1 is stabilized within one frame through the above self-feedback process, and the flicker of the light emitting element is improved.

As shown in fig. 3, the display substrate according to the embodiment of the present invention includes a plurality of rows and columns of pixel circuits disposed in a display area of a substrate, and at least one embodiment of the pixel circuits includes a light emitting element 10, a driving circuit 11, a compensation control circuit 12, a first initialization circuit 13, and a regulating circuit; the adjusting circuit includes a first adjusting circuit 141 and a second adjusting circuit 142;

the compensation control circuit 12 includes a first transistor T1;

The first initialization circuit 13 includes a second transistor T2;

a first end of the first adjusting circuit 141 is electrically connected to the intermediate node T1M of the first transistor T1, and a second end of the first adjusting circuit 141 is electrically connected to the control end of the driving circuit 11; the first adjusting circuit 141 is configured to adjust a potential of a control terminal of the driving circuit 11 according to a potential of an intermediate node T1M of the first transistor T1;

a first end of the second adjusting circuit 142 is electrically connected to the intermediate node T2M of the second transistor T2, and a second end of the second adjusting circuit 142 is electrically connected to the control end of the driving circuit 11; the second adjusting circuit 142 is configured to adjust the potential of the control terminal of the driving circuit 11 according to the potential of the intermediate node T2M of the second transistor T2.

In fig. 3, the reference number N1 is a first node electrically connected to the control terminal of the driving circuit 11.

In operation, at least one embodiment of the pixel circuit shown in fig. 3, in the light emitting stage, when the potential of the first node N1 decreases due to the leakage of T1 and the leakage of T2, the potential of T1M and the potential of T2M gradually increase, and the potential of the first node N1 increases due to the effects of the first adjusting circuit 141 and the second adjusting circuit 142, so that the potential of the first node N1 is stabilized within one frame through the above self-feedback process, and flicker of the light emitting element is improved;

when the potential of the first node N1 rises due to the leakage of T1 and the leakage of T2, the potential of T1M and the potential of T2M gradually drop, and the potential of the first node N1 drops due to the effects of the first and second adjusting circuits 141 and 142, the potential of the first node N1 is stabilized within one frame through the above self-feedback process, so that the flicker of the light emitting element is improved.

As shown in fig. 4, in at least one embodiment of the pixel circuit shown in fig. 1, the first adjusting circuit 141 includes a first capacitor C1;

the first electrode plate of the first capacitor C1 is electrically connected to the intermediate node T1M of the first transistor T1, and the second electrode plate of the first capacitor C1 is electrically connected to the first node N1.

In operation, at least one embodiment of the pixel circuit shown in fig. 4, in the light emitting stage, the potential of the compensation control signal provided by the compensation control line B1 rises from a low voltage to a high voltage, the potential of the T1M rises, when the T1 leaks, the potential of the first node N1 is pulled up, the potential of the T2M gradually decreases, the potential of the first node N1 decreases due to the coupling effect of the first capacitor C1, and the potential of the first node N1 is stabilized within one frame through the self-feedback process, so that the flicker of the light emitting element is improved;

when the potential of the first node N1 decreases due to the leakage of T1, the potential of T1M gradually increases, and the potential of the first node N1 increases due to the coupling action of the first capacitor C1, so that the potential of the first node N1 is stabilized within one frame through the above self-feedback process, and the flicker of the light emitting element is improved.

As shown in fig. 5, in at least one embodiment of the pixel circuit shown in fig. 2, the first adjusting circuit 142 includes a second capacitor C2;

the first electrode plate of the second capacitor C2 is electrically connected to the intermediate node T2M of the second transistor T2, and the second electrode plate of the second capacitor C1 is electrically connected to the first node N1.

In operation, at least one embodiment of the pixel circuit shown in fig. 5, in the light emitting stage, when the potential of the first node N1 decreases due to the leakage of T2, the potential of T2M gradually increases, and the potential of the first node N1 increases due to the coupling action of the second capacitor C2, so that the potential of the first node N1 is stabilized within one frame through the above self-feedback process, and the flicker of the light emitting element is improved;

when the potential of the first node N1 rises due to the leakage of T2, the potential of T2M gradually drops, and the potential of the first node N1 drops due to the coupling action of the second capacitor C2, so that the potential of the first node N1 is stabilized within one frame through the above self-feedback process, and the flicker of the light emitting element is improved.

As shown in fig. 6, in at least one embodiment of the pixel circuit shown in fig. 3, the first adjusting circuit 141 includes a first capacitor C1;

a first polar plate of the first capacitor C1 is electrically connected with the intermediate node T1M of the first transistor T1, and a second polar plate of the first capacitor C1 is electrically connected with the first node N1;

the first adjusting circuit 142 includes a second capacitor C2;

In operation, at least one embodiment of the pixel circuit shown in fig. 6, in the light emitting stage, when the potential of the first node N1 decreases due to the leakage of T1 and the leakage of T2, the potential of T1M and the potential of T2M gradually increase, and the potential of the first node N1 increases due to the coupling effect of the first capacitor C1 and the second capacitor C2, so that the potential of the first node N1 is stabilized within one frame through the above self-feedback process, and flicker of the light emitting element is improved;

when the potential of the first node N1 rises due to the leakage of T1 and the leakage of T2, the potential of the T1M and the potential of the T2M gradually decrease, and the potential of the first node N1 decreases due to the coupling effect of the first capacitor C1 and the second capacitor C2, the potential of the first node N1 is stabilized within one frame through the above self-feedback process, so that the flicker of the light emitting element is improved.

In at least one embodiment of the present invention, the display substrate includes a semiconductor layer, a first gate metal layer, and a source drain metal layer stacked in order along a direction away from the substrate; the first transistor comprises a first grid electrode, a second grid electrode and an active layer; the active layer of the first transistor comprises a first electrode, a second electrode, a first channel region, a second channel region and an intermediate active layer pattern;

The intermediate active layer pattern of the first transistor is arranged between the first channel region of the first transistor and the second channel region of the first transistor, and the intermediate active layer pattern of the first transistor, the first channel region of the first transistor and the second channel region of the first transistor are all contained in the semiconductor layer;

In a specific implementation, the middle active layer pattern of the first transistor is multiplexed into a first plate of the first capacitor, and a second plate of the first capacitor may be included in the source-drain metal layer.

In at least one embodiment of the present invention, the display substrate includes a semiconductor layer, a first gate metal layer, and a source drain metal layer stacked in order along a direction away from the substrate; the first transistor comprises a first grid electrode, a second grid electrode and an active layer; the active layer of the first transistor comprises a first channel region, a second channel region and an intermediate active layer pattern;

In a specific implementation, the middle active layer pattern of the first transistor is multiplexed into a first plate of the first capacitor, and a second plate of the first capacitor may be included in the first gate metal layer.

In at least one embodiment of the present invention, the display substrate includes a semiconductor layer, a first gate metal layer, and a source drain metal layer stacked in order along a direction away from the substrate; the second transistor includes a first gate electrode, a second gate electrode, and an active layer; the active layer of the second transistor comprises a first channel region, a second channel region and an intermediate active layer pattern;

The middle active layer pattern of the second transistor is arranged between the first channel region of the second transistor and the second channel region of the second transistor, and the middle active layer pattern of the second transistor, the first channel region of the second transistor and the second channel region of the second transistor are all contained in the semiconductor layer;

In a specific implementation, the middle active layer pattern of the second transistor is multiplexed to a first plate of the second capacitor, and the second plate of the second capacitor may be included in the source-drain metal layer.

In a specific implementation, the middle active layer pattern of the second transistor is multiplexed into the first plate of the second capacitor, and the second plate of the second capacitor may be included in the first gate metal layer.

In the display substrate according to at least one embodiment of the present invention, the pixel circuit further includes a tank circuit, a first light emitting control circuit, a second light emitting control circuit, and a data writing circuit;

In at least one embodiment of the present invention, the light emitting element may be an organic light emitting diode, the first pole of the light emitting element may be an anode of the organic light emitting diode, and the second pole of the light emitting element may be a cathode of the organic light emitting diode, but not limited thereto.

In at least one embodiment of the present invention, when the pixel circuit is in operation, the display period may include an initialization phase, a compensation phase and a light-emitting phase that are sequentially set;

in the compensation stage, the data writing circuit writes the data voltage into the second end of the driving circuit under the control of the writing control signal;

in the light emitting stage, the first light emitting control circuit controls the communication between the first voltage line and the second end of the driving circuit and controls the communication between the first end of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal, and the driving circuit drives the light emitting element to emit light.

In at least one embodiment of the present invention, the pixel circuit may further include a second initialization circuit;

in the compensation stage, the second initialization circuit writes a second initial voltage into the first electrode of the light-emitting element under the control of the initial control signal so as to control the light-emitting element not to emit light, resets the potential of the first electrode of the light-emitting element and clears the charge of the first electrode of the light-emitting element.

In the implementation, the compensation control line, the writing control line and the initial control line may be scanning lines, so as to reduce the number of control lines used, and facilitate the realization of a narrow frame.

In at least one embodiment of the present invention, the first initial voltage line and the second initial voltage line may be the same initial voltage line, so as to reduce the number of voltage lines used, which is beneficial to realizing a narrow frame.

In the embodiment of the present invention, the first voltage line may be a high voltage line, and the second voltage line may be a low voltage line, but not limited thereto.

Alternatively, the light emitting element may be an organic light emitting diode, the first electrode of the light emitting element may be an anode, and the second electrode of the light emitting element may be a cathode, but not limited thereto.

As shown in fig. 7, on the basis of at least one embodiment of the pixel circuit shown in fig. 4, the pixel circuit further includes a tank circuit 70, a first light emission control circuit 71, a second light emission control circuit 72, a data writing circuit 73, and a second initialization circuit 74;

a first end of the energy storage circuit 70 is electrically connected with the control end of the driving circuit 11, a second end of the energy storage circuit 70 is electrically connected with a high voltage line VDD, and the energy storage circuit 70 is used for storing electric energy;

the first light emitting control circuit 71 is electrically connected to the light emitting control line E1, the high voltage line VDD and the second terminal of the driving circuit 11, respectively, and is configured to control the high voltage line VDD to communicate with the second terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control line E1;

the second light-emitting control circuit 72 is electrically connected to the light-emitting control line E1, the first end of the driving circuit 11, and the first electrode of the light-emitting element 10, and is configured to control communication between the first end of the driving circuit 11 and the first electrode of the light-emitting element 10 under the control of the light-emitting control signal; a second electrode of the light emitting element 10 is electrically connected to a low voltage line VSS;

The data writing circuit 73 is electrically connected to the scan line GT, the data line DT and the second end of the driving circuit 11, and is configured to control writing the data voltage Vdata provided by the data line DT into the second end of the driving circuit 11 under the control of the scan signal provided by the scan line GT;

the second initializing circuit 74 is electrically connected to the scan line GT, the initial voltage line I0, and the first electrode of the light emitting element 10, respectively, for writing the initial voltage Vinit supplied by the initial voltage line I0 to the first electrode of the light emitting element under the control of the scan signal supplied by the scan line GT.

In at least one embodiment of the pixel circuit shown in fig. 7, the first voltage line is the high voltage line VDD, and the second voltage line is the low voltage line VSS.

In at least one embodiment of the pixel circuit shown in fig. 7, the compensation control line is the scan line GT, the first initial voltage line is the initial voltage line I0, and the first initial voltage line and the second initial voltage line are the same initial voltage line.

As shown in fig. 8, on the basis of at least one embodiment of the pixel circuit shown in fig. 5, the pixel circuit further includes a tank circuit 70, a first light emission control circuit 71, a second light emission control circuit 72, a data writing circuit 73, and a second initialization circuit 74;

In at least one embodiment of the pixel circuit shown in fig. 8, the first voltage line is the high voltage line VDD, and the second voltage line is the low voltage line VSS.

In at least one embodiment of the pixel circuit shown in fig. 8, the compensation control line is the scan line GT, the first initial voltage line is the initial voltage line I0, and the first initial voltage line and the second initial voltage line are the same initial voltage line.

As shown in fig. 9, on the basis of at least one embodiment of the pixel circuit shown in fig. 6, the pixel circuit further includes a tank circuit 70, a first light emission control circuit 71, a second light emission control circuit 72, a data writing circuit 73, and a second initialization circuit 74;

In at least one embodiment of the pixel circuit shown in fig. 9, the first voltage line is the high voltage line VDD, and the second voltage line is the low voltage line VSS.

In at least one embodiment of the pixel circuit shown in fig. 9, the compensation control line is the scan line GT, the first initial voltage line is the initial voltage line I0, and the first initial voltage line and the second initial voltage line are the same initial voltage line.

the control terminal of the driving transistor is the control terminal of the driving circuit, the first terminal of the driving transistor is the first terminal of the driving circuit, and the second terminal of the driving transistor is the second terminal of the driving circuit;

In at least one embodiment of the present invention, the display substrate includes a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source drain metal layer stacked in order along a direction away from the substrate;

As shown in fig. 10, in at least one embodiment of the pixel circuit shown in fig. 7, the first light emitting control circuit 71 includes a third transistor T3, the second light emitting control circuit 72 includes a fourth transistor T4, the data writing circuit 73 includes a fifth transistor T5, the second initializing circuit 74 includes a sixth transistor T6, the driving circuit 11 includes a driving transistor T0, and the tank circuit 70 includes a storage capacitor C0; the light-emitting element is an organic light-emitting diode O1;

the first initializing circuit 13 includes a second transistor T2, and the second transistor T2 is a double-gate transistor;

the first gate of the second transistor T2 and the second gate of the second transistor T2 are electrically connected to the reset control line R1, the drain of the second transistor T2 is electrically connected to the initial voltage line I0, and the source of the second transistor T2 is electrically connected to the gate of the driving transistor T0;

A gate of the third transistor T3 is electrically connected to the emission control line E1, a drain of the third transistor T3 is electrically connected to the high voltage line VDD, and a source of the third transistor T3 is electrically connected to a source of the driving transistor T0;

the gate of the fourth transistor T4 is electrically connected to the emission control line E1, the drain of the fourth transistor T4 is electrically connected to the drain of the driving transistor T0, and the source of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected with a low voltage line VSS;

a gate of the fifth transistor T5 is electrically connected to the scan line GT, a drain of the fifth transistor T5 is electrically connected to the data line DT, and a source of the fifth transistor T5 is electrically connected to a source of the driving transistor T0;

a gate of the sixth transistor T6 is electrically connected to the scan line GT, a drain of the sixth transistor T6 is electrically connected to the initial voltage line I0, and a source of the sixth transistor T6 is electrically connected to an anode of the organic light emitting diode O1;

the first electrode of the storage capacitor C0 is electrically connected to the gate of the driving transistor T0, and the second electrode of the storage capacitor C0 is electrically connected to the high voltage line VDD.

In at least one embodiment of the pixel circuit shown in fig. 10, the first voltage line is the high voltage line VDD, and the second voltage line is the low voltage line VSS.

In at least one embodiment of the pixel circuit shown in fig. 10, the first of the light emitting elements is the anode of the organic light emitting diode O1, and the second of the light emitting elements is the cathode of the organic light emitting diode O1.

In at least one embodiment of the pixel circuit shown in fig. 10, all the transistors are p-type transistors, but not limited thereto.

In at least one embodiment of the pixel circuit shown in fig. 10, the first node N1 is electrically connected to the gate of the driving transistor T0.

As shown in fig. 11, the display period includes an initialization phase Ta, a compensation phase Tb, and a light-emitting phase Tc, which are sequentially arranged, according to at least one embodiment of the pixel circuit shown in fig. 10;

in the initialization phase Ta, E1 provides a high voltage signal, G1 provides a high voltage signal, R1 provides a low voltage signal, T1 is turned on, I0 provides an initialization voltage Vinit to write the initialization voltage Vinit to the first node N1, so that T0 can be turned on at the beginning of the compensation phase Tb;

In the compensation period Tb, R1 provides a high voltage signal, E1 provides a high voltage signal, G1 provides a low voltage signal, T2 and T5 are turned on, the data line DT provides a data voltage Vdata to write the data voltage Vdata into the source of T0 and control the communication between the drain of T0 and the gate of T0, C0 is charged by the data voltage Vdata to change the potential of the first node N1 until the potential of the first node N1 becomes vdata+vth, wherein Vth is the threshold voltage of T0; t6 is opened, I0 provides an initialization voltage Vinit, so that the initialization voltage Vinit is written into the anode of O1, so that O1 does not emit light, the potential of the anode of O1 is reset, and the residual charge of the anode of O1 is cleared;

in the light emitting period Tc, R1 provides a high voltage signal, E1 provides a low voltage line, G1 provides a high voltage signal, both T3 and T4 are on, and T0 drives O1 to emit light.

As shown in fig. 12, in at least one embodiment of the pixel circuit shown in fig. 8, the first light emitting control circuit 71 includes a third transistor T3, the second light emitting control circuit 72 includes a fourth transistor T4, the data writing circuit 73 includes a fifth transistor T5, the second initializing circuit 74 includes a sixth transistor T6, the driving circuit 11 includes a driving transistor T0, and the tank circuit 70 includes a storage capacitor C0; the light-emitting element is an organic light-emitting diode O1;

The compensation control circuit 12 includes a first transistor T1; the first transistor T1 is a double-gate transistor;

the first gate of the first transistor T1 and the second gate of the first transistor T1 are electrically connected to the scan line GT, the drain of the first transistor T1 is electrically connected to the gate of the driving transistor T0, and the source of the first transistor T1 is electrically connected to the drain of the driving transistor T0;

In at least one embodiment of the pixel circuit shown in fig. 12, all of the transistors are p-type transistors, but not limited thereto.

In at least one embodiment of the pixel circuit shown in fig. 12, the first voltage line is the high voltage line VDD, and the second voltage line is the low voltage line VSS.

In at least one embodiment of the pixel circuit shown in fig. 12, the first of the light emitting elements is the anode of the organic light emitting diode O1, and the second of the light emitting elements is the cathode of the organic light emitting diode O1.

In at least one embodiment of the pixel circuit shown in fig. 12, the first node N1 is electrically connected to the gate of the driving transistor T0.

As shown in fig. 11, the display period includes an initialization phase Ta, a compensation phase Tb, and a light-emitting phase Tc, which are sequentially arranged, according to at least one embodiment of the pixel circuit shown in fig. 12;

As shown in fig. 13, in at least one embodiment of the pixel circuit shown in fig. 9, the first light emitting control circuit 71 includes a third transistor T3, the second light emitting control circuit 72 includes a fourth transistor T4, the data writing circuit 73 includes a fifth transistor T5, the second initializing circuit 74 includes a sixth transistor T6, the driving circuit 11 includes a driving transistor T0, and the tank circuit 70 includes a storage capacitor C0; the light-emitting element is an organic light-emitting diode O1;

In at least one embodiment of the pixel circuit shown in fig. 13, all the transistors are p-type transistors, but not limited thereto.

In at least one embodiment of the pixel circuit shown in fig. 13, the first voltage line is the high voltage line VDD, and the second voltage line is the low voltage line VSS.

In at least one embodiment of the pixel circuit shown in fig. 13, the first of the light emitting elements is the anode of the organic light emitting diode O1, and the second of the light emitting elements is the cathode of the organic light emitting diode O1.

In at least one embodiment of the pixel circuit shown in fig. 13, the first node N1 is electrically connected to the gate of the driving transistor T0.

As shown in fig. 11, the display period includes an initialization phase Ta, a compensation phase Tb, and a light-emitting phase Tc, which are sequentially arranged, according to at least one embodiment of the pixel circuit shown in fig. 13;

Fig. 14 is a schematic diagram of the addition of a reference number to the counter electrode on the basis of at least one embodiment of the pixel circuit shown in fig. 10, and fig. 14 further differs from fig. 10 in that: the drain electrode is changed to the first electrode, and the source electrode is changed to the second electrode.

As shown in fig. 14, the compensation control circuit 12 includes a first transistor T1;

the first gate G11 of the first transistor T1 and the second gate G12 of the first transistor T1 are electrically connected to the scan line G1, the first electrode D1 of the first transistor T1 is electrically connected to the gate G0 of the driving transistor T0, and the second electrode S1 of the first transistor T1 is electrically connected to the first electrode D0 of the driving transistor T0;

The first adjusting circuit 141 includes a first capacitor C1;

a first polar plate C1a of the first capacitor C1 is electrically connected with the intermediate node T1M of the first transistor T1, and a second polar plate C1b of the first capacitor C1 is electrically connected with the first node N1;

the first gate electrode G21 of the second transistor T2 and the second gate electrode G22 of the second transistor T2 are electrically connected to the reset control line R1, the first electrode D2 of the second transistor T2 is electrically connected to the initial voltage line I0, and the second electrode S2 of the second transistor T2 is electrically connected to the gate electrode G0 of the driving transistor T0;

the first light emission control circuit 71 includes a third transistor T3, the second light emission control circuit 72 includes a fourth transistor T4, the data writing circuit 73 includes a fifth transistor T5, the second initialization circuit 74 includes a sixth transistor T6, the driving circuit 11 includes a driving transistor T0, and the tank circuit 70 includes a storage capacitor C0; the light-emitting element is an organic light-emitting diode O1;

a gate electrode G3 of the third transistor T3 is electrically connected to the emission control line E1, a first electrode D3 of the third transistor T3 is electrically connected to the high voltage line VDD, and a second electrode S3 of the third transistor T3 is electrically connected to a second electrode S0 of the driving transistor T0;

A gate electrode G4 of the fourth transistor T4 is electrically connected to the emission control line E1, a first electrode D4 of the fourth transistor T4 is electrically connected to a first electrode D0 of the driving transistor T0, and a second electrode S4 of the fourth transistor T4 is electrically connected to an anode of the organic light emitting diode O1;

a gate electrode G4 of the fifth transistor T5 is electrically connected to the scan line GT, a first electrode D5 of the fifth transistor T5 is electrically connected to the data line DT, and a second electrode S5 of the fifth transistor T5 is electrically connected to a second electrode S0 of the driving transistor T0;

a gate electrode G6 of the sixth transistor T6 is electrically connected to the scan line GT, a first electrode D6 of the sixth transistor T6 is electrically connected to the initial voltage line I0, and a second electrode S6 of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode O1;

the first plate C0a of the storage capacitor C0 is electrically connected to the gate G0 of the driving transistor T0, and the second plate C0b of the storage capacitor C0 is electrically connected to the high voltage line VDD.

In fig. 15, the middle active layer pattern of the first transistor T1 is denoted by 100, the first channel region of T1 is denoted by 101, the second channel region of T1 is denoted by 102, the first channel region of T2 is denoted by 201, the second channel region of T2 is denoted by 202, the channel region of T0 is denoted by 10, the channel region of T3 is denoted by 30, the channel region of T4 is denoted by 40, the channel region of T5 is denoted by 50, and the channel region of T6 is denoted by 60;

The middle active layer pattern 100 of the first transistor T1 is multiplexed as a first plate of C1.

As shown in fig. 16, a first gate electrode denoted by T1 and G11, a second gate electrode denoted by T1 and G12, a first gate electrode denoted by T2 and G21, a second gate electrode denoted by T2 and G22, a gate electrode denoted by T0 and G0, and a first plate electrode denoted by C0 are multiplexed; the gate electrode denoted by T3 and G3, the gate electrode denoted by T4 and G4, the gate electrode denoted by T5 and G5, the gate electrode denoted by T6 and G6, the reset control line denoted by R1, the scan line denoted by GT, and the emission control line denoted by E1, respectively.

In fig. 17, reference numeral I0 is an initial voltage line, and reference numeral C0b is a second plate of C0.

In fig. 18, a high voltage line denoted by VDD, a data line denoted by DT, a second plate denoted by C1b, a first conductive connection portion denoted by L1, the first conductive connection portion L1 being formed as a unitary structure with the second plate C1b of C1, the first conductive connection portion L1 being for electrically connecting the second plate C1b of C1 and the gate G0 of the driving transistor T0.

Fig. 19 is a layout of at least one embodiment of the pixel circuit shown in fig. 14, fig. 15 is a layout of the active layer in fig. 19, fig. 16 is a layout of the first gate metal layer in fig. 19, fig. 17 is a layout of the second gate metal layer in fig. 19, and fig. 18 is a layout of the source drain metal layer in fig. 19.

In fig. 20, the middle active layer pattern of the first transistor T1 is denoted by 100, the first channel region of T1 is denoted by 101, the second channel region of T1 is denoted by 102, the first channel region of T2 is denoted by 201, the second channel region of T2 is denoted by 202, the channel region of T0 is denoted by 10, the channel region of T3 is denoted by 30, the channel region of T4 is denoted by 40, the channel region of T5 is denoted by 50, and the channel region of T6 is denoted by 60;

As shown in fig. 21, a first gate electrode denoted by T1 and G11, a second gate electrode denoted by T1 and G12, a first gate electrode denoted by T2 and G21, a second gate electrode denoted by T2 and G22, a gate electrode denoted by T0 and G0, and a first plate electrode denoted by C0 are multiplexed; the gate electrode denoted by T3 and G3, the gate electrode denoted by T4 and G4, the gate electrode denoted by T5 and G5, the gate electrode denoted by T6 and G6, the reset control line denoted by R1, the scan line denoted by GT, and the emission control line denoted by E1, respectively.

In fig. 22, the initial voltage line is denoted by I0, the second electrode plate is denoted by C0 and C0, the second conductive connection is denoted by L2, and the second electrode plate is denoted by C1 and C1 b.

In fig. 23, reference numeral VDD is a high voltage line, reference numeral DT is a data line, and reference numeral L3 is a third conductive connection portion.

Fig. 24 is a layout of at least one embodiment of the pixel circuit shown in fig. 14, fig. 20 is a layout of the active layer in fig. 24, fig. 21 is a layout of the first gate metal layer in fig. 24, fig. 22 is a layout of the second gate metal layer in fig. 24, and fig. 23 is a layout of the source drain metal layer in fig. 24.

As shown in fig. 24, the second conductive connection portion L2 is electrically connected to the third conductive connection portion L3 through a via hole, the third conductive connection portion L3 is also electrically connected to the gate G0 of the driving transistor T0 through a via hole, and the second conductive connection portion L2 and the C1b are formed as an integral structure so that the C1b is electrically connected to the gate of the driving transistor T0.

The display device provided by the embodiment of the invention comprises the display substrate.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims

1. A display substrate, characterized by comprising a plurality of rows and columns of pixel circuits arranged in a display area of a substrate, wherein the pixel circuits comprise a light-emitting element, a driving circuit, a compensation control circuit, a first initialization circuit and a regulating circuit;

The adjusting circuit is also electrically connected with the control end of the driving circuit and is used for adjusting the potential of the control end of the driving circuit;

the compensation control circuit comprises a transistor which is a double-gate transistor, and the regulating circuit comprises a first regulating circuit; the first end of the first regulating circuit is electrically connected with the middle node of the transistor included in the compensation control circuit, the second end of the first regulating circuit is electrically connected with the control end of the driving circuit, and the first regulating circuit is used for regulating the potential of the control end of the driving circuit according to the potential of the middle node of the transistor included in the compensation control circuit; and/or the number of the groups of groups,

2. The display substrate of claim 1, wherein the compensation control circuit comprises a first transistor, the first adjustment circuit comprising a first capacitance; the first transistor is a double-gate transistor;

3. The display substrate according to claim 2, wherein the display substrate comprises a semiconductor layer, a first gate metal layer, and a source-drain metal layer, which are sequentially stacked in a direction away from the substrate; the first transistor comprises a first grid electrode, a second grid electrode and an active layer; the active layer of the first transistor comprises a first electrode, a second electrode, a first channel region, a second channel region and an intermediate active layer pattern arranged between the first channel region and the second channel region;

4. The display substrate according to claim 2, wherein the display substrate comprises a semiconductor layer, a first gate metal layer, and a source-drain metal layer, which are sequentially stacked in a direction away from the substrate; the first transistor comprises a first grid electrode, a second grid electrode and an active layer; the active layer of the first transistor comprises a first channel region, a second channel region and an intermediate active layer pattern arranged between the first channel region and the second channel region;

5. The display substrate of claim 2, wherein the first initialization circuit comprises a second transistor and the second adjustment circuit comprises a second capacitor; the second transistor is a double-gate transistor;

6. The display substrate according to claim 5, wherein the display substrate comprises a semiconductor layer, a first gate metal layer, and a source drain metal layer, which are sequentially stacked in a direction away from the substrate; the second transistor includes a first gate electrode, a second gate electrode, and an active layer; the active layer of the second transistor comprises a first channel region, a second channel region and an intermediate active layer pattern arranged between the first channel region and the second channel region;

7. The display substrate according to claim 5, wherein the display substrate comprises a semiconductor layer, a first gate metal layer, and a source drain metal layer, which are sequentially stacked in a direction away from the substrate; the second transistor includes a first gate electrode, a second gate electrode, and an active layer; the active layer of the second transistor comprises a first channel region, a second channel region and an intermediate active layer pattern arranged between the first channel region and the second channel region;

8. The display substrate according to any one of claims 1 to 7, wherein the pixel circuit further comprises a tank circuit, a first light emission control circuit, a second light emission control circuit, and a data writing circuit;

9. The display substrate of claim 8, wherein the pixel circuit further comprises a second initialization circuit;

10. The display substrate of claim 9, wherein the compensation control line, the write control line, and the initial control line access the same control signal.

11. The display substrate according to claim 9, wherein the first light-emitting control circuit includes a third transistor, the second light-emitting control circuit includes a fourth transistor, the data writing circuit includes a fifth transistor, the second initializing circuit includes a sixth transistor, the driving circuit includes a driving transistor, and the energy storing circuit includes a storage capacitor;

12. The display substrate according to claim 11, wherein the display substrate comprises a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source drain metal layer, which are sequentially stacked in a direction away from the substrate;

13. The display substrate of claim 12, wherein the compensation control line, the write control line, and the initial control line are all scan lines, and the scan lines, the reset control line, and the light emission control line are all included in the first gate metal layer;

14. A display device comprising the display substrate according to any one of claims 1 to 13.