CN114758617B

CN114758617B - Display substrate, driving method thereof and display device

Info

Publication number: CN114758617B
Application number: CN202210319404.1A
Authority: CN
Inventors: 李栋; 张慧娟; 刘政; 屈财玉; 陈登云
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-03-29
Filing date: 2022-03-29
Publication date: 2023-12-08
Anticipated expiration: 2042-03-29
Also published as: CN114758617A

Abstract

The invention relates to the technical field of display, in particular to a display substrate, a driving method thereof and a display device, so as to improve the stroboscopic phenomenon of the display device. The display substrate includes: and a pixel circuit. The pixel circuit includes: a switching circuit configured to transmit a data signal to the first node under control of the scan signal; a driving circuit configured to transmit an electrical signal of the first node to the third node under control of the potential of the second node; a compensation circuit configured to transmit an electrical signal of the third node to the second node under control of the scan signal; a dimming circuit configured to transmit an electric signal of the second node to an internal node of the driving circuit to increase a channel capacitance of the driving circuit in a case where a display gray level of the light emitting device is greater than or equal to a threshold gray level; or, in the case where the display gray scale of the light emitting device is smaller than the threshold gray scale, the channel capacitance of the driving circuit is reduced. The display substrate, the driving method thereof and the display device are used for image display.

Description

Display substrate, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display substrate, a driving method thereof, and a display device.

Background

An organic light emitting diode (Organic Light Emitting Diode, abbreviated as OLED) display technology is a technology that uses a light emitting material to emit light under the drive of current to realize display. The OLED display has the advantages of ultra-light, ultra-thin, high brightness, large viewing angle, low voltage, low power consumption, quick response, high definition, shock resistance, flexibility, low cost, simple process, few raw materials, high luminous efficiency, wide temperature range and the like.

Disclosure of Invention

An object of an embodiment of the present invention is to improve a strobe phenomenon of a display device.

In order to achieve the above purpose, the embodiment of the invention provides the following technical scheme:

some embodiments of the present invention provide a display substrate including a substrate, and a pixel circuit disposed on the substrate. The pixel circuit includes: the light-emitting device comprises a light-emitting device, a switching circuit, a driving circuit, a compensation circuit and a dimming circuit. The switch circuit is electrically connected with the scanning signal end, the data signal end and the first node and is configured to transmit the data signal provided by the data signal end to the first node under the control of the scanning signal provided by the scanning signal end. The driving circuit is electrically connected with a second node, the first node and a third node and is configured to transmit an electric signal from the first node to the third node under the control of the electric potential of the second node; the drive circuit includes an internal node. The compensation circuit is electrically connected with at least the scanning signal end, the second node and the third node, and is configured to transmit an electrical signal from the third node to the second node under the control of the scanning signal. The light modulation circuit is electrically connected with the control signal end, the second node and the internal node, and is configured to conduct a passage between the second node and the internal node and transmit an electric signal from the second node to the internal node when the display gray scale of the light emitting device is greater than or equal to a threshold gray scale, so that the driving circuit is controlled by the electric potential of the internal node and the channel capacitance of the driving circuit is increased; or, in the case where the display gray scale of the light emitting device is smaller than the threshold gray scale, cutting off the path between the second node and the internal node, so that the driving circuit is controlled by the potential of the second node, and reducing the channel capacitance of the driving circuit.

According to the display substrate provided by some embodiments of the invention, the pixel circuit of the display substrate comprises the switch circuit, the driving circuit, the compensation circuit and the dimming circuit, so that the data signal provided by the data signal end is transmitted to the second node of the pixel circuit, and the dimming circuit is arranged to control the conduction and disconnection of the passage between the second node and the internal node of the driving circuit, so that the conduction state of the dimming circuit can be controlled according to the relation between the display gray scale and the threshold gray scale of the light emitting device. Under the condition that the display gray level of the light emitting device is smaller than the threshold gray level, the dimming circuit cuts off the paths of the second node and the internal node of the driving circuit, so that the driving circuit is not controlled by the internal node, and the driving circuit is controlled by the second node. At this time, since the capacitance of the second channel capacitor composed of the second node and the channel of the driving circuit is small, the channel capacitance of the driving circuit is reduced with respect to the capacitance of the first channel capacitor composed of the internal node of the driving circuit and the channel of the driving circuit. Thus, the driving current generated by the driving circuit is reduced, the driving current transmitted to the light emitting device by the driving circuit is reduced, the light emitting luminance of the light emitting device is reduced, and the display gray scale of the light emitting device is reduced. Further, when the data signal is used for adjusting the display gray scale, the data signal with a larger voltage value range can be used for adjusting, a larger driving state range is provided, and the sensitivity of the driving current to the data signal is improved. Therefore, the display device can realize smaller gray scale display by adopting the setting mode, and can adjust the brightness of the light emitting device by adopting the full direct current dimming technology in a low gray scale range, thereby avoiding the stroboscopic phenomenon of the display device caused by dimming by adopting the PWM technology and avoiding the damage to the vision health of a user.

In some embodiments, the driving circuit includes: a first transistor. The first transistor includes a first gate and a second gate. The first gate of the first transistor is electrically connected to the second node, the second gate of the first transistor is electrically connected to the internal node, the first pole of the first transistor is electrically connected to the first node, and the second pole of the first transistor is electrically connected to the third node. The dimming circuit includes: and a second transistor. The grid electrode of the second transistor is electrically connected with the control signal end, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with the first grid electrode of the first transistor.

In some embodiments, the switching circuit includes a third transistor. The gate of the third transistor is electrically connected to the scan signal terminal, the first electrode of the third transistor is electrically connected to the data signal terminal, and the second electrode of the third transistor is electrically connected to the first node. The compensation circuit includes: a storage capacitor and a fourth transistor. The grid electrode of the fourth transistor is electrically connected with the scanning signal end, the first electrode of the fourth transistor is electrically connected with the third node, and the second electrode of the fourth transistor is electrically connected with the second node. The first polar plate of the storage capacitor is electrically connected with the second node, and the second polar plate of the storage capacitor is electrically connected with the first voltage signal end.

In some embodiments, the pixel circuit further comprises: the light emitting device comprises a first reset circuit, a light emitting control circuit and a second reset circuit. The first reset circuit is electrically connected with the reset signal end, the initial signal end and the second node, and is configured to transmit the initial signal provided by the initial signal end to the second node under the control of the reset signal provided by the reset signal end. The light-emitting control circuit is electrically connected with an enabling signal end, a first voltage signal end, the first node, the third node and the fourth node, and is configured to transmit a first voltage signal provided by the first voltage signal end to the first node under the control of an enabling signal provided by the enabling signal end; the driving circuit is further configured to generate a driving signal according to the potential of the second node and a first voltage signal from the first node; the light emission control circuit is further configured to transmit the drive signal to a fourth node; the fourth node is electrically connected to the light emitting device. The second reset circuit is electrically connected with the reset signal end, the initial signal end and the fourth node, and is configured to transmit the initial signal to the fourth node under the control of the reset signal.

In some embodiments, the first reset circuit comprises: and a fifth transistor. The grid electrode of the fifth transistor is electrically connected with the reset signal end, the first electrode of the fifth transistor is electrically connected with the initial signal end, and the second electrode of the fifth transistor is electrically connected with the second node. The light emission control circuit includes: a sixth transistor and a seventh transistor. The grid electrode of the sixth transistor is electrically connected with the enabling signal end, the first electrode of the sixth transistor is electrically connected with the first voltage signal end, and the second electrode of the sixth transistor is electrically connected with the first node. The grid electrode of the seventh transistor is electrically connected with the enabling signal end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the fourth node. The second reset circuit includes: and an eighth transistor. The gate of the eighth transistor is electrically connected to the reset signal terminal, the first pole of the eighth transistor is electrically connected to the initial signal terminal, and the second pole of the eighth transistor is electrically connected to the fourth node.

In some embodiments, the pixel circuit further comprises a plurality of transistors. Any of the remaining transistors, except the first transistor, includes a low-temperature polysilicon-type transistor or an oxide-type transistor.

In some embodiments, the display substrate includes: and the first active layer, the first insulating layer, the first conductive layer, the second insulating layer and the second conductive layer are sequentially stacked in a direction away from the substrate. The first transistor of the driving circuit in the pixel circuit includes: a first active pattern at the first active layer, a first gate at the first conductive layer, and a second gate at the second conductive layer.

In some embodiments, the first insulating layer has a thickness in the range of 100nm to 300nm; the thickness of the second insulating layer ranges from 100nm to 300nm.

In some embodiments, the thickness of the first insulating layer is the same as the thickness of the second insulating layer.

In some embodiments, the material of the first active layer comprises low temperature polysilicon.

In some embodiments, the display substrate further comprises: and the second active layer and the third conductive layer are sequentially laminated on one side of the second conductive layer far away from the first active layer. The material of the second active layer includes a metal oxide.

Some embodiments of the present invention also provide a driving method of a display substrate, which is applied to the display substrate according to any one of the above embodiments. The driving method includes a first stage and a second stage. In the first stage, the switching circuit transmits a data signal provided by the data signal terminal to the first node in response to a scanning signal provided by the scanning signal terminal; the driving circuit transmits an electrical signal from the first node to a third node; the compensation circuit transmits an electrical signal from the third node to the second node. In the second stage, when the display gray level of the light emitting device is greater than or equal to a threshold gray level, the dimming circuit turns on a path between the second node and an internal node of the driving circuit, and transmits an electric signal from the second node to the internal node, so that the driving circuit is controlled by the electric potential of the internal node, and increases the channel capacitance of the driving circuit; or, in the case that the display gray scale of the light emitting device is smaller than the threshold gray scale, cutting off a path between the second node and an internal node of the driving circuit, so that the driving circuit is controlled by the potential of the second node, and increasing the channel capacitance of the driving circuit.

The advantages achieved by the driving method of the display substrate provided by some embodiments of the present invention are the same as those achieved by the display substrate provided by some embodiments, and are not described herein.

In some embodiments, in the case where the pixel circuit includes a light emission control circuit, the driving method further includes: and a third stage. In the third stage, in response to an enable signal provided by an enable signal terminal, the light emission control circuit transmits a first voltage signal provided by a first voltage signal terminal to the first node, the driving circuit generates a driving signal according to a potential of the second node and the first voltage signal from the first node, and the light emission control circuit further transmits the driving signal to a fourth node.

In some embodiments, in the case where the pixel circuit includes a first reset circuit and a second reset circuit, the driving method further includes: and a fourth stage. In the fourth stage, in response to a reset signal provided by a reset signal terminal, the first reset circuit transmits an initial signal provided by an initial signal terminal to the second node; the second reset circuit transmits the initial signal to the fourth node.

Some embodiments of the present invention also provide a display apparatus including: the display substrate of any one of the above embodiments.

The beneficial effects of the display device provided by some embodiments of the present invention are the same as those of the display substrate provided by some embodiments, and are not described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present invention, the drawings that are required to be used in some embodiments of the present invention will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present invention, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic views, not limiting the actual size of the products, etc. according to the embodiments of the present invention.

FIG. 1 is a block diagram of a display device according to some embodiments of the invention;

FIG. 2 is a block diagram of a pixel circuit according to some embodiments of the invention;

FIG. 3 is a block diagram of another pixel circuit according to some embodiments of the invention;

FIG. 4a is a block diagram of yet another pixel circuit according to some embodiments of the invention;

FIG. 4b is a block diagram of yet another pixel circuit according to some embodiments of the invention;

FIG. 5 is a block diagram of yet another pixel circuit according to some embodiments of the invention;

FIG. 6 is a block diagram of a first transistor in a driving circuit according to some embodiments of the present invention;

FIG. 7 is a partial block diagram of a display substrate according to some embodiments of the invention;

fig. 8 is a transfer characteristic diagram of a pixel circuit according to some embodiments of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments obtained by a person skilled in the art based on the embodiments provided by the present invention fall within the scope of protection of the present invention.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the invention. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

The use of "configured to" herein is meant to be an open and inclusive language that does not exclude devices configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

The terms "first," "second," and the like herein are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

In the circuit structures (for example, pixel circuits) provided in the embodiments of the present invention, the transistors may be thin film transistors (Thin Film Transistor, abbreviated as TFTs), field effect transistors (Metal Oxide Semiconductor, abbreviated as MOS) or other switching devices with the same characteristics, and the thin film transistors are taken as examples in the embodiments of the present invention.

In the circuit structure provided by the embodiment of the invention, the first pole of each transistor is one of the source electrode and the drain electrode, and the second pole of each transistor is the other of the source electrode and the drain electrode. Since the source and drain of the transistor may be symmetrical in structure, the source and drain thereof may be indistinguishable in structure, that is, the first and second poles of the transistor in embodiments of the present invention may be indistinguishable in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In the circuit structure provided by the embodiment of the invention, the first node, the second node and other nodes do not represent actually existing components, but represent the junction points of the related coupling in the circuit diagram, that is, the nodes are equivalent nodes formed by the junction points of the related coupling in the circuit diagram.

In the invention, the P-type transistor can be conducted under the control of a low-level signal, and the N-type transistor can be conducted under the control of a high-level signal.

In the following, the present invention is described by taking P-type transistors as examples of the transistors included in the pixel circuit.

In one implementation manner, in order to meet the requirement that the low gray scale of the display device can be displayed in a large dynamic range in a dark environment, and the display characteristic meets the requirement of gamma characteristic, and meanwhile, the compensation capability of the threshold voltage of the pixel circuit under a small current can be improved, a pulse width modulation (Pulse Width Modulation, abbreviated as PWM) technology is mainly adopted at present to adjust the display brightness of the display device. The display device adopting the PWM technology has lower working frequency, lower picture refreshing frequency and longer holding time of one frame of pictures, so that the potential of the control node for controlling the on state of the driving circuit in the pixel circuit of the display device needs to be maintained for a longer time. This is easy to occur due to the leakage of the control node, resulting in a sudden (or gradual) increase in the light emission luminance of the light emitting device driven by the pixel circuit, so that the display device is stroboscopic and the visual health of the user is easily impaired.

Based on this, as shown in fig. 1, some embodiments of the present invention provide a display apparatus 1000.

In some examples, the display device 1000 described above may be in any display device that displays both motion (e.g., video) and stationary (e.g., still image) and text or images. More particularly, it is contemplated that the display device of the embodiments may be implemented in or associated with a variety of electronics such as, but not limited to, mobile phones, wireless devices, personal Data Assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer display, etc.), navigators, cabin controllers and/or displays, displays of camera views (e.g., displays of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images on a piece of jewelry), and the like.

Exemplary, the display device 1000 includes: frames, display driver ICs (Integrated Circuit, integrated circuits), and other electronic components.

In some examples, as shown in fig. 1, the display device 1000 further includes: and a display substrate 200. The display substrate 200 may include the pixel circuit 100 therein.

The pixel circuit 100 may be plural, for example. The plurality of pixel circuits may be arranged in an array.

For example, the pixel circuit 100 may include a circuit including a few transistors and a few capacitors, or the like.

In some examples, as shown in fig. 2, the pixel circuit 100 further includes: a light emitting device 10.

For example, one pixel circuit 100 may include one light emitting device 10. The circuits in the pixel circuit 100 described above may be electrically connected to the light emitting device 10.

Illustratively, in the display substrate 200, the circuitry in the pixel circuit 100 may generate a drive signal (here, a drive signal is taken as an example of a drive current). Each light emitting device 10 can emit light under the driving action of the driving signal generated by the pixel circuit 100 to which it belongs, and the light emitted by the plurality of light emitting devices 10 are mutually matched, so that the display substrate 200 and the display device 1000 realize the display function.

The light emitting device 10 may be an OLED, for example.

For example, the broken lines in fig. 2 and 3 indicate that the light emitting device 10 is indirectly electrically connected to the third node N3, that is, other circuit structures are further disposed between the light emitting device 10 and the third node N3. The light emitting device 10 is also electrically connected to the second voltage signal terminal Vss.

In some embodiments, as shown in fig. 2, the pixel circuit 100 includes: a switching circuit 20, a driving circuit 30, a compensation circuit 40, and a dimming circuit 50.

In some examples, as shown in fig. 2, the switch circuit 20 is electrically connected to the scan signal terminal Gate, the Data signal terminal Data and the first node N1. The switching circuit 20 is configured to transmit the Data signal supplied from the Data signal terminal Data to the first node N1 under the control of the scan signal supplied from the scan signal terminal Gate.

In some examples, as shown in fig. 2, the driving circuit 30 is electrically connected to the first node N1, the second node N2, and the third node N3. The driving circuit 30 is configured to transmit the electric signal from the first node N1 to the third node N3 under the control of the potential of the second node N2. The driving circuit 30 includes an internal node Nt.

Illustratively, the internal node Nt forms a first channel capacitor with the channel of the drive circuit 30, and the second node N2 forms a second channel capacitor with the channel of the drive circuit 30. The channel capacitance of the first channel capacitor or the channel capacitance of the second channel capacitor constitutes the channel capacitance of the driving circuit 30. The internal node Nt is a smaller distance from the channel of the driving circuit 30 than the external node (e.g., the second node N2). Thus, the channel capacitance of the first channel capacitor is greater than the channel capacitance of the second channel capacitor.

In some examples, as shown in fig. 2 and 3, the compensation circuit 40 is electrically connected to at least the scan signal terminal Gate, the second node N2, and the third node N3. The compensation circuit 40 is configured to transmit the electrical signal from the third node N3 to the second node N2 under control of the scan signal.

Illustratively, in the case where the level of the scan signal is an active level, the switching circuit 20 and the compensation circuit 40 may be turned on simultaneously under the control of the scan signal, the switching circuit 20 may receive and transmit the data signal to the first node N1, the driving circuit 30 may transmit the electrical signal (e.g., the data signal) from the first node N1 to the third node N3, and the compensation circuit 40 may transmit the electrical signal (e.g., the data signal) from the third node N3 to the second node N2 to compensate the driving circuit 30.

The "active level" in the present invention refers to a level at which the transistor can be turned on. An "active level" refers to a level that can cause a transistor to turn off. In the case where the transistor is an N-type transistor, the "effective level" is a high level; in the case of a P-type transistor, the "active level" is low. The following embodiments are the same as this and will not be described in detail.

Illustratively, as shown in FIG. 3, the compensation circuit 40 may also be electrically connected to the first voltage signal terminal Vdd.

Illustratively, the first voltage signal terminal Vdd is configured to transmit a dc high level signal. The dc high level signal is referred to herein as a first voltage signal, and the following embodiments are the same as the first voltage signal and will not be described again.

For example, after the compensation circuit 40 transmits the electrical signal (e.g., the data signal) from the third node N3 to the second node N2, the compensation circuit 40 is electrically connected to the first voltage signal terminal Vdd, and the first voltage signal is a dc high level signal, so that it is beneficial to ensure that the potential of the second node N2 has higher stability.

In some examples, as shown in fig. 2 and 3, the dimming circuit 50 is electrically connected to the control signal terminal Cot, the second node N2, and the internal node Nt of the driving circuit 30. The dimming circuit 50 is configured to, in the case where the display gray level of the light emitting device 10 is greater than or equal to the threshold gray level, turn on a path between the second node N2 and the internal node Nt, transmit an electric signal (e.g., a data signal) from the second node N2 to the internal node Nt, so that the driving circuit 30 is controlled by the potential of the internal node Nt, and increase the channel capacitance of the driving circuit 30; or, in the case where the display gray scale of the light emitting device 10 is smaller than the threshold gray scale, the path between the second node N2 and the internal node Nt is cut off, so that the driving circuit 30 is controlled by the potential of the second node N2, and the channel capacitance of the driving circuit 30 is reduced.

For example, the threshold gray level may be a boundary value between a middle gray level and a high gray level. When the display gray scale of the light emitting device is larger than or equal to the threshold gray scale, the display gray scale is judged to be the middle-high gray scale, and at the moment, the light emitting brightness of the light emitting device is the middle-high brightness. When the display gray scale of the light emitting device is smaller than the threshold gray scale, the display gray scale is judged to be low gray scale, and at this time, the light emitting brightness of the light emitting device is low.

For example, the control signal terminal Cot may be electrically connected to the display driving IC. Firstly, the display driving IC may obtain the display gray level of the light emitting device 10, then, the display driving IC compares and calculates the display gray level of the light emitting device 10 with a preset threshold gray level, and provides a corresponding control signal for the control signal terminal Cot according to the comparison and calculation result, where the control signal controls the on state of the dimming circuit 50, so as to control the on and off between the second node N2 and the internal node Nt of the driving circuit 30, and further increase and decrease the channel capacitance of the driving circuit 30.

The magnitude of the light emission luminance of the light emitting device depends on the magnitude of the driving current transmitted to the light emitting device; the magnitude of the driving current is proportional to the magnitude of the channel capacitance of the driving circuit. That is, the larger the channel capacitance of the driving circuit, the larger the driving current transmitted to the light emitting device, the larger the light emitting luminance of the light emitting device, and accordingly, the larger the display gray scale of the light emitting device. Conversely, the smaller the channel capacitance of the drive circuit, the smaller the drive signal (drive current) through the light emitting device, and the smaller the light emitting luminance of the light emitting device, and accordingly, the smaller the display gray scale of the light emitting device. Next, the magnitude of the driving signal (driving current) is also related to the voltage magnitude of the Data signal transmitted by the Data signal terminal Data. The smaller the voltage of the data signal, the smaller the electric signal transmitted to the second node N2 via the switching circuit 20, the driving circuit 30, and the compensating circuit 40, so that the driving circuit 30 generates a larger driving signal (driving current).

Illustratively, after the above-mentioned compensation circuit 40 transmits the electrical signal (e.g., the data signal) from the third node N3 to the second node N2, the display driving IC performs a comparison calculation of the display gray scale of the light emitting device 10 with the threshold gray scale.

For example, in the case where the display gray level of the light emitting device 10 is greater than or equal to the threshold gray level, the level of the control signal outputted by the control signal terminal Cot is an active level, the dimming circuit 50 is turned on, and an electrical connection between the second node N2 and the internal node Nt of the driving circuit 30 is achieved, and an electrical signal of the second node N2 is transmitted to the internal node Nt of the driving circuit 30. At this time, the driving circuit 30 is controlled by the electric signal of the internal node Nt, and since the channel capacitance of the first channel capacitor formed by the internal node Nt and the channel of the driving circuit 30 is large, the channel capacitance of the driving circuit 30 is large compared to the channel capacitance of the second channel capacitor formed by the second node N2 and the channel of the driving circuit 30, and thus the driving current generated by the driving circuit 30 is large, the driving current transmitted to the light emitting device 10 by the driving circuit 30 is large, the light emitting luminance of the light emitting device 10 is large, and the display gray scale of the light emitting device 10 is large. In addition, since the increase of the channel capacitance of the driving circuit 30 has already achieved the increase of the driving current, it is possible to avoid using a data signal varying in a larger range in the middle-high gray scale range to adjust the magnitude of the driving current. Therefore, the display device 1000 can realize larger gray scale display by adopting the above arrangement mode, and further can adjust the brightness of the light emitting device by adopting the full Direct Current (DC) dimming technology in a high gray scale range.

For another example, in the case that the display gray level of the light emitting device 10 is smaller than the threshold gray level, the level of the control signal output by the control signal terminal Cot is an inactive level, and the dimming circuit 50 is turned off, so that the dimming circuit 50 cuts off the path between the second node N2 and the internal node Nt of the driving circuit 30, and the driving circuit 30 is not controlled by the internal node Nt but controlled by the second node N2. At this time, since the capacitance of the second channel capacitor composed of the second node N2 and the channel of the driving circuit 30 is small, the channel capacitance of the driving circuit 30 is reduced with respect to the capacitance of the first channel capacitor composed of the internal node Nt and the channel of the driving circuit 30. Thus, the driving signal generated by the driving circuit 30, for example, the driving current decreases, the driving current transmitted to the light emitting device 10 by the driving circuit 30 decreases, the light emitting luminance of the light emitting device 10 decreases, and the display gray scale of the light emitting device 10 decreases. When the data signal is used for adjusting the display gray scale, the data signal with a larger voltage value range can be used for adjusting, a larger driving state range is provided, and the sensitivity of the driving current to the data signal is improved. Therefore, the display device 1000 can realize smaller gray scale display by adopting the above arrangement, and can adjust the brightness of the light emitting device by adopting the full Direct Current (DC) dimming technology in the low gray scale range.

Therefore, by adopting the above arrangement, the gray scales of the light emitting device 10 can be adjusted by using the full-dc dimming technology under the conditions of the middle and high gray scales and the low gray scales of the display substrate 200 and the display device 1000, so that the stroboscopic phenomenon of the display device caused by dimming by using the PWM technology is avoided, and the damage to the vision health of the user is avoided.

The structure of the driving circuit 30 in the pixel circuit 100 is exemplified in various ways, and may be set according to practical situations, which is not limited by the present invention.

In some embodiments, as shown in fig. 5, the driving circuit 30 includes: the first transistor T1, the first transistor T1 includes a first gate and a second gate.

For example, the first transistor T1 is a double gate transistor.

Illustratively, as shown in fig. 5, the second gate of the first transistor T1 is electrically connected to the second node N2, the first gate of the first transistor T1 is electrically connected to the internal node Nt, the first pole of the first transistor T1 is electrically connected to the first node N1, and the second pole of the first transistor T1 is electrically connected to the third node N3.

Illustratively, as shown in fig. 5, the dimming circuit 50 includes: and a second transistor T2. The gate of the second transistor T2 is electrically connected to the control signal terminal Cot, the first pole of the second transistor T2 is electrically connected to the second node N2, and the second pole of the second transistor T2 is electrically connected to the first gate of the first transistor T1.

Since the first gate is electrically connected to the internal node Nt, the channel capacitor formed by the first gate and the channel of the first transistor T1 may be equivalent to the first channel capacitor formed by the internal node Nt and the channel of the driving circuit 30. The second gate is electrically connected to the second node N2, and a channel capacitor formed by the second gate and a channel of the first transistor T1 may be identical to a second channel capacitor formed by the second node N2 and a channel of the driving circuit 30.

For example, when the display gray level of the light emitting device 10 is greater than or equal to the threshold gray level, the level of the control signal provided by the control signal terminal Cot is an effective level, the second transistor T2 is turned on under the control of the control signal, the electrical signal of the second node N2 is transmitted to the internal node Nt of the driving circuit 30, the electrical signal of the internal node Nt is transmitted to the first gate of the first transistor T1, and the first transistor T1 is turned on under the control of the electrical signal of the first gate, at this time, since the capacitance of the first channel capacitor formed by the internal node Nt (or the first gate) and the channel of the first transistor T1 is greater, the driving current flowing through the first transistor T1 to the light emitting device 10 is greater, and thus, the magnitude of the driving current can be adjusted by changing the magnitude of the driving current in the middle-high gray level range, the gray level range of the light emitting device is prevented from being adjusted by using the data signal varying in the large range, and thus the dimming of the gray level of the display device 1000 in the high gray level range can be achieved.

For another example, in the case that the display gray level of the light emitting device 10 is smaller than the threshold gray level, the level of the control signal provided by the control signal terminal Cot is a non-active level, the second transistor T2 in the dimming circuit 50 is turned off under the control of the control signal, the electric signal of the second node N2 is transmitted to the second gate of the first transistor T1, the first transistor T1 is turned on under the control of the voltage of the second gate, at this time, since the capacitance of the second channel capacitor formed by the second gate and the channel of the first transistor T1 is smaller, the driving current flowing through the first transistor T1 to the light emitting device 10 is smaller, the light emitting brightness of the light emitting device 10 is reduced, and the display gray level of the light emitting device 10 is reduced. When the data signal is used for adjusting the display gray scale, the data signal with a larger voltage value range can be used for adjusting, a larger driving state range is provided, and the sensitivity of the driving current to the data signal is improved. Accordingly, the display in the low gray scale range of the display device 1000 can be dimmed using DC dimming.

The structures of the switching circuit 20 and the compensation circuit 40 in the pixel circuit 100 are various, and may be set according to practical situations, which is not limited by the present invention.

In some embodiments, as shown in fig. 5, the switching circuit 20 includes a third transistor T3. The Gate of the third transistor T3 is electrically connected to the scan signal terminal Gate, the first pole of the third transistor T3 is electrically connected to the Data signal terminal Data, and the second pole of the third transistor T3 is electrically connected to the first node N1.

In an exemplary case where the level of the scan signal is an active level, the third transistor T3 is turned on to transmit the Data signal provided from the Data signal terminal Data to the first node N1.

In some examples, the third transistor T3 includes an oxide-type transistor or a low-temperature polysilicon-type transistor.

The third transistor T3 may be an oxide transistor, for example. Because the oxide transistor has lower leakage current, the first node N1 can be prevented from leaking from the third transistor T3 when the third transistor T3 is in the off state, so that the influence on the luminous current of the luminous device can be avoided, the display gray scale of the luminous device is avoided, and the accuracy of the actual display gray scale of the luminous device is improved.

The third transistor T3 may be a low temperature polysilicon type transistor, for example. Since the mobility of the low-temperature polysilicon transistor is high, the turn-on speed of the third transistor T3 can be increased, thereby increasing the reaction speed of the pixel circuit 100 and improving the display quality of the display device 1000.

In some examples, the compensation circuit 40 includes: and a storage capacitor Cst and a fourth transistor T4. The Gate of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first pole of the fourth transistor T4 is electrically connected to the third node N3, and the second pole of the fourth transistor T4 is electrically connected to the second node N2. The first plate of the storage capacitor Cst is electrically connected to the second node N2, and the second plate of the storage capacitor Cst is electrically connected to the first voltage signal terminal Vdd.

In an exemplary case where the level of the scan signal is an active level, the third transistor T3 is turned on under the control of the scan signal to transmit the Data signal provided from the Data signal terminal Data to the first node N1. The first transistor T1 is in an on state, and transmits an electrical signal (e.g., the data signal) of the first node N1 to the third node N3. The fourth transistor T4 is turned on under the control of the scan signal, and transmits an electrical signal (for example, the data signal) of the third node N3 to the second node N2, so as to compensate the threshold voltage of the first transistor T1.

In some embodiments, as shown in fig. 4a, the pixel circuit 100 further includes: a first reset circuit 60.

In some examples, the first reset circuit 60 is electrically connected to the reset signal terminal Rst, the initial signal terminal Vinit, and the second node N2. The first reset circuit 60 is configured to transmit the initial signal provided by the initial signal terminal Vinit to the second node N2 under the control of the reset signal provided by the reset signal terminal Rst.

Illustratively, the initial signal terminal Vinit is configured to transmit a dc low level signal. The dc low level signal is referred to herein as an initial signal, and the following embodiments are the same and will not be described again.

For example, in the case that the level of the reset signal is an active level, the first reset circuit 60 may be turned on under the control of the reset signal, transmit the initial signal to the second node N2, and complete the reset of the second node N2, and simultaneously turn on the first transistor T1.

In some embodiments, as shown in fig. 4a, the pixel circuit 100 further includes: a light emission control circuit 70.

In some examples, the light emission control circuit 70 is electrically connected to the enable signal terminal EM, the first voltage signal terminal Vdd, the first node N1, the third node N3, and the fourth node N4. The light emission control circuit 70 is configured to transmit a first voltage signal supplied from the first voltage signal terminal Vdd to the first node N1 under the control of an enable signal supplied from the enable signal terminal EM; the driving circuit 30 is further configured to generate a driving signal from the electric signal of the second node N2 and the first voltage signal from the first node N1; the light emission control circuit 70 is further configured to transmit the above-described driving signal to the fourth node N4; the fourth node N4 is electrically connected to the light emitting device 10.

For example, in case that the level of the enable signal is an active level, the light emission control circuit 70 may be turned on under the control of the enable signal, transmitting the first voltage signal to the first node N1. The driving circuit 30 generates a driving signal based on the electric signal (for example, the data signal) of the second node N2 and the first voltage signal of the first node N1, and transmits the driving signal to the third node N3. The light emission control circuit 70 transmits the third node N3 (e.g., the driving signal described above) to the fourth node N4. The light emitting device 10 emits light by the electric signal of the fourth node N4, that is, the driving signal described above, thereby causing the display apparatus 1000 to realize display.

As illustrated in fig. 4b, the light emission control circuit 70 includes: a first light emission control sub-circuit 71 and a second light emission control sub-circuit 72.

For example, the first light emitting control sub-circuit 71 is electrically connected to the first voltage signal terminal Vdd, the enable signal terminal EM, and the first node N1. The first light emitting control sub-circuit 71 is configured to transmit a first voltage signal to the first node N1 under control of an enable signal. The second light emission control sub-circuit 72 is electrically connected to the fourth node N4, the enable signal terminal EM, and the third node N3. The second light emission control sub-circuit 72 is configured to transmit an electrical signal (e.g., a first voltage signal) from the third node N3 to the fourth node N4 under control of an enable signal.

Illustratively, the fourth node N4 is electrically connected to one end of the light emitting device 10, and the other end of the light emitting device 10 is electrically connected to the second voltage signal terminal Vss.

In the above arrangement, under the control of the enable signal, the first light emission control sub-circuit 71 transmits the first voltage signal to the first node N1, the driving circuit 30 generates the driving signal according to the electrical signal of the second node N2 and the electrical signal of the first node N1 (e.g., the first voltage signal), and transmits the driving signal to the third node N3, and the second light emission control sub-circuit 62 transmits the electrical signal from the third node N3 (e.g., the driving signal) to the fourth node N4. Since the fourth node N4 is electrically connected to the light emitting device 10, the light emitting device 10 may emit light by an electrical signal (e.g., the driving signal) of the fourth node N4.

In some embodiments, as shown in fig. 4a, the pixel circuit 100 further includes: a second reset circuit 80.

In some examples, the second reset circuit 80 is electrically connected to the reset signal terminal Rst, the initial signal terminal Vinit, and the fourth node N4. The second reset circuit 80 is configured to transmit an initial signal to the fourth node N4 under control of a reset signal.

For example, in the case where the level of the reset signal is an active level, the second reset circuit 80 may be turned on under the control of the reset signal, transmit an initial signal to the fourth node N4, and reset the fourth node N4.

The first reset circuit 60, the light emission control circuit 70, and the second reset circuit 80 in the pixel circuit 100 may be configured according to actual needs, which is not limited by the present invention.

In some embodiments, as shown in fig. 5, the first reset circuit 60 includes: and a fifth transistor T5.

In some examples, the gate of the fifth transistor T5 is electrically connected to the reset signal terminal Rst, the first pole of the fifth transistor T5 is electrically connected to the initial signal terminal Vinit, and the second pole of the fifth transistor T5 is electrically connected to the second node N2.

For example, in case that the level of the reset signal is an active level, the fifth transistor T5 may be simultaneously turned on under the control of the reset signal. The fifth transistor T5 may transmit an initial signal to the second node N2, to reset the second node N2, and simultaneously turn on the first transistor T1.

In some embodiments, as shown in fig. 5, the second reset circuit 80 includes: and an eighth transistor T8.

In some examples, the gate of the eighth transistor T8 is electrically connected to the reset signal terminal Rst, the first pole of the eighth transistor T8 is electrically connected to the initial signal terminal Vinit, and the second pole of the eighth transistor T8 is electrically connected to the fourth node N4.

For example, in the case where the level of the reset signal is an active level, the eighth transistor T8 may be turned on under the control of the reset signal. The eighth transistor T8 may transmit an initial signal to the second node N2, implementing a reset of the second node N2.

In some examples, as shown in fig. 5, the light emission control circuit 70 includes: a sixth transistor T6 and a seventh transistor T7.

Illustratively, the first light emission control sub-circuit 71 in the light emission control circuit 70 may include a sixth transistor T6, and the second light emission control sub-circuit 72 in the light emission control circuit 70 may include a seventh transistor T7.

Illustratively, the gate of the sixth transistor T6 is electrically connected to the enable signal terminal EM, the first pole of the sixth transistor T6 is electrically connected to the first voltage signal terminal Vdd, and the second pole of the sixth transistor T6 is electrically connected to the first node N1. The gate of the seventh transistor T7 is electrically connected to the enable signal terminal EM, the first pole of the seventh transistor T7 is electrically connected to the third node N3, and the second pole of the seventh transistor T7 is electrically connected to the fourth node N4.

For example, in the case where the level of the enable signal is an active level, the sixth transistor T6 and the seventh transistor T7 may be turned on in synchronization under the control of the enable signal. The sixth transistor T6 transmits the first voltage signal provided by the first voltage signal terminal Vdd to the first node N1. The seventh transistor T7 transmits an electrical signal (e.g., a driving signal) from the third node N3 to the fourth node N4. The fourth node N4 is electrically connected to one end of the light emitting device 10, and the light emitting device 10 emits light by an electrical signal of the fourth node.

In some embodiments, the pixel circuit 100 further includes a plurality of transistors; any of the remaining transistors except the first transistor T1 includes a low-temperature polysilicon-type transistor or an oxide-type transistor.

In some examples, the first transistor T1 may be a low temperature polysilicon type transistor, and the remaining transistors in the pixel circuit 100 may be low temperature polysilicon type transistors, for example, the third transistor T3 may be a low temperature polysilicon type transistor, or the like.

In other examples, the remaining transistors in the pixel circuit 100 may be oxide-type transistors except the first transistor T1, for example, the third transistor T3 may be a low-temperature polysilicon-type transistor, or the like.

In still other examples, some of the remaining transistors of the pixel circuit 100 may be oxide-type transistors, such as the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 being oxide-type transistors, and the like, in addition to the first transistor T1; another part of the remaining transistors of the pixel circuit 100 may be low-temperature polysilicon type transistors.

In some embodiments, the display substrate 200 includes: a substrate 101.

Illustratively, the pixel circuit 100 described above is disposed on a substrate 101.

The substrate 101 may be a flexible substrate or a rigid substrate, for example.

For example, in the case where the substrate 101 is a flexible substrate, the material of the substrate 101 may be a material having high elasticity such as dimethylsiloxane, PI (Polyimide), PET (Polyethylene terephthalate), polyethylene terephthalate, or the like.

As another example, in the case where the substrate 101 is a rigid substrate, the material of the substrate 101 may be glass or the like.

In some embodiments, the display substrate 200 includes: the first active layer ACT1, the first insulating layer GI1, the first conductive layer Gt1, the second insulating layer GI2, and the second conductive layer Gt2 are stacked in this order in a direction away from the substrate 101.

Illustratively, the materials of the first conductive layer Gt1 and the second conductive layer Gt2 are conductive materials. The materials of the first conductive layer Gt1 and the second conductive layer Gt2 may be the same, for example.

For example, the conductive material may be a metal material such as Al (aluminum), ag (silver), cu (copper), cr (chromium), or the like.

Illustratively, the materials of the first insulating layer GI1 and the second insulating layer GI2 are both insulating materials. The materials of the first insulating layer GI1 and the second insulating layer GI2 may be the same, for example.

For example, the insulating material may be silicon oxide, silicon nitride, silicon oxynitride, or the like.

In some examples, as shown in fig. 6, the first transistor T1 of the driving circuit 30 in the pixel circuit 100 includes: the first active pattern located on the first active layer ACT1, the first gate electrode located on the first conductive layer Gt1, and the second gate electrode located on the second conductive layer Gt 2.

Illustratively, as shown in fig. 6, the first active pattern has a first facing portion with the first gate electrode. In the first active pattern, a portion opposite to the first gate electrode is a first channel Ch1. The first channel Ch1 and the first gate constitute a first channel capacitor.

As shown in fig. 6, the first active pattern and the second gate electrode have a second opposite portion, and the portion opposite to the second gate electrode in the first active pattern is a second channel Ch2. The second channel Ch2 and the second gate constitute a second channel capacitor.

Illustratively, the orthographic projection of the first gate electrode on the substrate 101 may coincide with the orthographic projection of the second gate electrode on the substrate 101, and thus, the position and the area size of the first channel Ch1 in the first active pattern may be the same as the position and the area size of the second channel Ch2 in the first active pattern. The capacitance of a capacitor is related to the area of the two plates in the capacitor and the spacing between the plates. And the area of the first channel capacitor is the same as that of the second channel capacitor, and the distance between the two plates of the first channel capacitor is smaller than that of the second channel capacitor, so that the capacitance of the first channel capacitor is larger than that of the second channel capacitor.

With the above arrangement, when the display gray level of the light emitting device 10 is greater than or equal to the threshold gray level, the first transistor T1 in the driving circuit 30 is controlled by the internal node Nt, and at this time, the channel capacitance of the driving circuit 30 is the capacitance of the first channel capacitor, and the channel capacitance of the driving circuit 30 is increased compared to the capacitance of the second channel capacitor. Thus, the driving current generated by the first transistor T1 in the driving circuit 30 increases, the driving current transmitted to the light emitting device 10 by the first transistor T1 increases, the light emitting luminance of the light emitting device 10 increases, and the display gray scale of the light emitting device 10 increases. In addition, since the increase of the channel capacitance of the driving circuit 30 has already achieved the increase of the driving current, it is possible to avoid using a data signal varying in a larger range in the middle-high gray scale range to adjust the magnitude of the driving current. In contrast, when the display gray scale of the light emitting device 10 is smaller than the threshold gray scale, the first transistor T1 in the driving circuit 30 is controlled by the second node N2, i.e., the second gate, and at this time, the channel capacitance of the driving circuit 30 is the capacitance of the second channel capacitor, and the channel capacitance of the driving circuit 30 is reduced compared with the capacitance of the first channel capacitor, whereby the driving signal generated by the first transistor T1 in the driving circuit 30, for example, the driving current is reduced, the driving current transmitted to the light emitting device 10 by the first transistor T1 is reduced, the light emitting luminance of the light emitting device 10 is reduced, and the display gray scale of the light emitting device 10 is reduced. When the data signal is used for adjusting the display gray scale, the data signal with a larger voltage value range can be used for adjusting, a larger driving state range is provided, and the sensitivity of the driving current to the data signal is improved. Accordingly, the display device displayed in the low gray scale range can be dimmed using DC dimming.

For example, in order to describe in detail the variation of the driving current Ids flowing through the first transistor T1 under the first gate control and the second gate control under the different gate-source voltage differences (the difference between the voltage Vg of the gate of the first transistor T1 and the voltage Vs of the source), the present invention is simulated for the transfer characteristic curve Q1 of the driving circuit 30 in the case where the first transistor T1 is controlled by the first gate and the transfer characteristic curve Q2 of the driving circuit 30 in the case where the first transistor T1 is controlled by the second gate, and the obtained graph is shown in fig. 8.

The transfer characteristic curve is a correspondence curve between the driving current Ids passing through the first transistor T1 and the gate-source voltage difference Vgs of the first transistor T1.

As shown in fig. 8, in the range of the gate-source voltage difference Vgs of-15V to 15V, the driving current Ids of the transfer characteristic curve Q1 and the driving current Ids of the transfer characteristic curve Q2 both tend to decrease and then gradually increase as the gate-source voltage difference Vgs increases.

As shown in fig. 8, in the case where the gate-source voltage difference Vgs is smaller than 0V, the driving current Ids of the transfer characteristic curve Q1 is almost larger than the driving current Ids of the transfer characteristic curve Q2 when the gate-source voltage differences Vgs are the same. In a range where the gate-source voltage difference Vgs is greater than 2.5V, the driving current Ids of the transfer characteristic curve Q1 is almost equal to the driving current Ids of the transfer characteristic curve Q2 when the gate-source voltage differences Vgs are the same.

For example, as shown in fig. 8, in the case where the gate-source voltage Vgs is smaller than 0V (for example, the gate-source voltage difference Vgs is in the range of-15V to-2.5V), the driving current Ids corresponding to the transfer characteristic curve Q1 is larger than the driving current Ids corresponding to the transfer characteristic curve Q2, and at this time, the driving current Ids corresponding to the transfer characteristic curve Q1 may be adopted so that the first gate controls the turn-on of the first transistor T1, so that the light emitting device 10 may obtain a larger driving current, and the variation range of the larger driving current (about 10 ^-12 A～10 ^-5 A) Is greater than the corresponding variation range (about 10) of the driving current Ids in the same gate-source voltage range (about-15V to-2.5V) in the transfer characteristic curve Q2 ^-12 A～10 ^-6 A) Therefore, the dimming circuit 50 is adopted to control the conduction between the second node N2 and the node Nt inside the driving circuit 30, so that the channel capacitance of the driving circuit 30 is increased, the light-emitting brightness range of the light-emitting device 10 under the medium-high gray scale can be enlarged, the light-emitting brightness of the light-emitting device 10 is increased, and then the dimming can be performed in the high gray scale range by adopting the direct current dimming technology.

As another example, as shown in fig. 8, in the case where the gate-source voltage Vgs is greater than 0V (for example, the gate-source voltage difference Vgs is in the range of 2.5V to 15V), the slope of the transfer characteristic curve Q1 is greater than the slope of the transfer characteristic curve Q2, and the subthreshold swing SS of the transfer characteristic curve Q2 is greater than the subthreshold swing SS of the transfer characteristic curve Q1 (note that the subthreshold swing formula is ss=d (Vgs)/d (log (Ids)). The larger the subthreshold swing SS is, the larger the value of the gate-source voltage difference Vgs is increased by 1V, the larger the corresponding increase of the driving current Vgs is, therefore, the larger the subthreshold swing SS is, the more sensitive the driving current Vgs is to the change of the gate-source voltage difference Vgs, the larger Igs change can be obtained only by smaller adjustment of the gate-source voltage difference Vgs, the larger gray scale adjustment can be obtained for the light emitting device 10 corresponding to the driving current Vgs, therefore, under the condition of low gray scale, the first transistor T1 of the driving circuit 30 can work under the control of the second grid, the corresponding transfer characteristic curve of the pixel circuit 30 is Q2, further, the gray scale of the light emitting device 10 in the low gray scale range can be finely adjusted by adjusting the gate-source voltage difference Vgs, the sensitivity to the voltage of the gate-source voltage difference Vgs and the data signal is improved, in addition, a larger adjustment range can be provided, and the direct current dimming technology can be adopted in the low gray scale range.

Illustratively, the display substrate 200 further includes: and a fourth conductive layer Sd disposed on a side of the second conductive layer Gt2 remote from the second insulating layer GI 2.

Illustratively, as shown in fig. 6, the first transistor T1 further includes: at the first pole S1 of the fourth conductive layer Sd.

Illustratively, the fourth conductive layer Sd includes: the first connecting block and the second connecting block.

For example, one end of the first connection block is electrically connected to the first gate of the first transistor T1 through a via hole, and the other end of the first connection block is electrically connected to the second pole of the second transistor T2 through a via hole. One end of the second connecting block is electrically connected with the second grid electrode of the first transistor T1 through a via hole, and the other end of the second connecting block is electrically connected with the first pole of the second transistor T2 through a via hole.

In some embodiments, the thickness of the first insulating layer GI1 ranges from 100nm to 300nm; the thickness of the second insulating layer GI2 ranges from 100nm to 300nm.

In some examples, the thickness of the first insulating layer GI1 may be 100nm, 150nm, 210nm, 270nm, 300nm.

In some examples, the thickness of the second insulating layer GI2 may be 100nm, 150nm, 210nm, 270nm, 300nm.

By adopting the arrangement mode, the first channel capacitor and the second channel capacitor can be prevented from being broken down by current, and the capacitance of the first channel capacitor and the channel capacitance of the second channel capacitor can have larger difference, so that the driving current of the light-emitting device has larger variation range, and the full direct current dimming technology can be adopted for dimming under different gray scales of the light-emitting device.

The thicknesses of the first insulating layer GI1 and the second insulating layer GI2 may be set in various manners, and may be set according to practical situations, which is not limited by the present invention.

In some examples, the thickness of the first insulating layer GI1 may be different from the thickness of the second insulating layer GI 2.

In other examples, the thickness of the first insulating layer GI1 is the same as the thickness of the second insulating layer GI 2. Thus, the first insulating layer GI1 and the second insulating layer GI2 can be manufactured by the same process, and the manufacturing process of the display device can be simplified.

For example, the thickness of the first insulating layer GI1 and the thickness of the second insulating layer GI2 may be 100nm, 150nm, 200nm, 250nm, 300nm, or the like.

In some examples, the material of the first active layer ACT1 includes low temperature polysilicon.

The first active pattern of the first transistor T1 is illustratively located in the first active layer, and the first transistor T1 is a low temperature polysilicon type transistor.

In some examples, as shown in fig. 7, the third transistor T3 of the switching circuit 20 in the pixel circuit 100 includes: and a third active pattern. The third active pattern is located on the first active layer ACT1.

Thus, the third transistor T3 is a low-temperature polysilicon type transistor.

In some embodiments, as shown in fig. 7, the display substrate 200 further includes: the second active layer ACT2 and the third conductive layer Gt3 are sequentially stacked on the side of the second conductive layer Gt2 away from the first active layer ACT 1.

In some examples, the material of the second active layer ACT2 includes a metal oxide.

For example, the metal oxide may be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO).

In some examples, the third transistor T3 of the switching circuit 20 includes: and a third active pattern.

In some examples, the third active pattern is located at the second active layer ACT2.

Thus, the third transistor T3 may be an oxide transistor.

Some embodiments of the present invention also provide a driving method of a display substrate, which is applied to the display substrate 200 in any of the above embodiments.

In some examples, the driving method described above includes a first phase P1 and a second phase P2.

Illustratively, in the first stage P1, the switching circuit 20 transmits the Data signal provided by the Data signal terminal Data to the first node N1 in response to the scan signal provided by the scan signal terminal Gate; the driving circuit 30 transmits the electric signal from the first node N1 to the third node N3; the compensation circuit 40 transmits the electrical signal from the third node N3 to the second node N2.

For example, the first phase P1 may include: and a data writing and compensating stage.

For example, in the first stage P1, the Data signal provided by the Data signal terminal Data is sequentially transmitted to the second node N2 through the third transistor T3 of the switching circuit 20, the first node N1, the first transistor T1 of the driving circuit 30, the third node N3, and the fourth transistor T4 of the compensation circuit 40 under the control of the scan signal provided by the scan signal terminal Gate.

Illustratively, in the second stage P2, in the case where the display gray level of the light emitting device 10 is greater than or equal to the threshold gray level, the dimming circuit 50 turns on the path between the second node N2 and the internal node Nt, transmits the electric signal from the second node N2 to the internal node Nt, so that the driving circuit 30 is controlled by the potential of the internal node Nt, and increases the channel capacitance of the driving circuit 30; or, in the case where the display gray scale of the light emitting device 10 is smaller than the threshold gray scale, the path between the second node N2 and the internal node Nt is cut off, so that the driving circuit 30 is controlled by the potential of the second node N2, and the channel capacitance of the driving circuit 30 is increased.

For example, the second stage P2 may include: and (3) a dimming stage.

For example, in the second stage P2, in the case where the display gray level of the light emitting device 10 is greater than or equal to the threshold gray level, the level of the control signal outputted from the control signal terminal Cot is an active level, the dimming circuit 50 is turned on, and the electric signal from the second node N2 is transmitted to the internal node Nt, so that the driving circuit 30 operates under the control of the internal node Nt. In the case where the display gray level of the light emitting device 10 is less than the threshold gray level, the level of the control signal outputted from the control signal terminal Cot is an inactive level, and the dimming circuit 50 is turned off so that the driving circuit 30 operates under the control of the second node N2.

Illustratively, the second phase P2 may be performed synchronously with the first phase P1, or the second node P2 may be performed after the first phase P1.

In some embodiments, the driving method further includes a third stage P3.

Illustratively, in the third stage P3, in response to the enable signal provided by the enable signal terminal EM, the light emission control circuit 70 transmits the first voltage signal provided by the first voltage signal terminal Vdd to the first node N1, and the driving circuit 30 generates a driving signal according to the electrical signal of the second node N2 and the first voltage signal from the first node N1, and the light emission control circuit 70 also transmits the driving signal to the fourth node N4.

The driving signal is related to a Data signal provided by the Data signal terminal Data and a first voltage signal provided by the first voltage signal terminal.

For example, the fourth node N4 is electrically connected to the light emitting device 10. The light emitting device 10 emits light by an electric signal (e.g., the above-described driving signal) supplied from the fourth node N4.

For example, the third phase P3 may include: and a light emitting stage.

In some embodiments, the driving method further includes a fourth stage P4.

Illustratively, in the fourth phase P4, the first reset circuit 70 transmits the initial signal provided by the initial signal terminal Vinit to the second node N2 in response to the reset signal provided by the reset signal terminal Rst; the reset of the second node N2 is completed ready for the next stage. The second reset circuit 80 transmits the initial signal provided by the initial signal terminal Vinit to the fourth node N4; the reset of the fourth node N4 is completed ready for the next stage.

For example, the fourth phase P4 may include: and a reset stage.

The fourth phase P4 described above may be performed, for example, before the first phase P1.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will recognize that changes and substitutions are within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A display substrate, the display substrate comprising a substrate, and a pixel circuit disposed on the substrate, the pixel circuit comprising:

a light emitting device;

the switching circuit is electrically connected with the scanning signal end, the data signal end and the first node and is configured to transmit the data signal provided by the data signal end to the first node under the control of the scanning signal provided by the scanning signal end;

a driving circuit electrically connected to a second node, the first node, and a third node, and configured to transmit an electrical signal from the first node to the third node under control of a potential of the second node; the driving circuit includes an internal node;

A compensation circuit electrically connected to at least the scanning signal terminal, the second node, and the third node and configured to transmit an electrical signal from the third node to the second node under control of the scanning signal;

the dimming circuit is electrically connected with the control signal end, the second node and the internal node, and is configured to conduct a passage between the second node and the internal node and transmit an electric signal from the second node to the internal node under the condition that the display gray level of the light emitting device is greater than or equal to a threshold gray level, so that the driving circuit is controlled by the electric potential of the internal node and the channel capacitance of the driving circuit is increased; or, in the case where the display gray scale of the light emitting device is smaller than the threshold gray scale, cutting off the path between the second node and the internal node, so that the driving circuit is controlled by the potential of the second node, and reducing the channel capacitance of the driving circuit.

2. The display substrate according to claim 1, wherein the driving circuit comprises: a first transistor including a first gate and a second gate;

A first gate of the first transistor is electrically connected to the second node, a second gate of the first transistor is electrically connected to the internal node, a first pole of the first transistor is electrically connected to the first node, and a second pole of the first transistor is electrically connected to the third node;

the dimming circuit includes: a second transistor;

the grid electrode of the second transistor is electrically connected with the control signal end, the first electrode of the second transistor is electrically connected with the second node, and the second electrode of the second transistor is electrically connected with the first grid electrode of the first transistor.

3. The display substrate according to claim 1, wherein the switching circuit comprises a third transistor;

a gate of the third transistor is electrically connected to the scan signal terminal, a first electrode of the third transistor is electrically connected to the data signal terminal, and a second electrode of the third transistor is electrically connected to the first node;

the compensation circuit includes: a storage capacitor and a fourth transistor;

the grid electrode of the fourth transistor is electrically connected with the scanning signal end, the first electrode of the fourth transistor is electrically connected with the third node, and the second electrode of the fourth transistor is electrically connected with the second node;

The first polar plate of the storage capacitor is electrically connected with the second node, and the second polar plate of the storage capacitor is electrically connected with the first voltage signal end.

4. The display substrate of claim 1, wherein the pixel circuit further comprises:

the first reset circuit is electrically connected with the reset signal end, the initial signal end and the second node and is configured to transmit an initial signal provided by the initial signal end to the second node under the control of a reset signal provided by the reset signal end;

the light-emitting control circuit is electrically connected with an enabling signal end, a first voltage signal end, the first node, the third node and the fourth node and is configured to transmit a first voltage signal provided by the first voltage signal end to the first node under the control of an enabling signal provided by the enabling signal end; the driving circuit is further configured to generate a driving signal according to the potential of the second node and a first voltage signal from the first node; the light emission control circuit is further configured to transmit the drive signal to a fourth node; the fourth node is electrically connected with the light emitting device;

And the second reset circuit is electrically connected with the reset signal end, the initial signal end and the fourth node and is configured to transmit the initial signal to the fourth node under the control of the reset signal.

5. The display substrate according to claim 4, wherein,

the first reset circuit includes: a fifth transistor;

the grid electrode of the fifth transistor is electrically connected with the reset signal end, the first electrode of the fifth transistor is electrically connected with the initial signal end, and the second electrode of the fifth transistor is electrically connected with the second node;

the light emission control circuit includes: a sixth transistor and a seventh transistor;

the grid electrode of the sixth transistor is electrically connected with the enabling signal end, the first electrode of the sixth transistor is electrically connected with the first voltage signal end, and the second electrode of the sixth transistor is electrically connected with the first node;

the grid electrode of the seventh transistor is electrically connected with the enabling signal end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the fourth node;

the second reset circuit includes: an eighth transistor;

The gate of the eighth transistor is electrically connected to the reset signal terminal, the first pole of the eighth transistor is electrically connected to the initial signal terminal, and the second pole of the eighth transistor is electrically connected to the fourth node.

6. The display substrate according to claim 2, wherein the pixel circuit further comprises a plurality of transistors;

any of the remaining transistors, except the first transistor, includes a low-temperature polysilicon-type transistor or an oxide-type transistor.

7. The display substrate according to claim 2 or 6, wherein the display substrate comprises: a first active layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer, which are sequentially stacked in a direction away from the substrate;

the first transistor includes: a first active pattern at the first active layer, a first gate at the first conductive layer, and a second gate at the second conductive layer.

8. The display substrate of claim 7, wherein the display substrate comprises a transparent substrate,

the thickness of the first insulating layer ranges from 100nm to 300nm; the thickness of the second insulating layer ranges from 100nm to 300nm.

9. The display substrate according to claim 7, wherein a thickness of the first insulating layer is the same as a thickness of the second insulating layer.

10. The display substrate of claim 7, wherein the display substrate comprises a transparent substrate,

the material of the first active layer includes low-temperature polysilicon.

11. The display substrate of claim 7, wherein the display substrate further comprises: the second active layer and the third conductive layer are sequentially laminated on one side of the second conductive layer far away from the first active layer;

the material of the second active layer includes a metal oxide.

12. A driving method of a display substrate, characterized in that the driving method is applied to the display substrate according to any one of claims 1 to 11; the driving method includes: a first stage and a second stage;

in the first stage, the switching circuit transmits a data signal provided by the data signal terminal to the first node in response to a scanning signal provided by the scanning signal terminal; the driving circuit transmits an electrical signal from the first node to a third node; the compensation circuit transmits an electrical signal from the third node to a second node;

in the second stage, when the display gray level of the light emitting device is greater than or equal to a threshold gray level, the dimming circuit turns on a path between the second node and an internal node of the driving circuit, and transmits an electric signal from the second node to the internal node, so that the driving circuit is controlled by the electric potential of the internal node, and increases the channel capacitance of the driving circuit; or, in the case that the display gray scale of the light emitting device is smaller than the threshold gray scale, cutting off a path between the second node and an internal node of the driving circuit, so that the driving circuit is controlled by the potential of the second node, and increasing the channel capacitance of the driving circuit.

13. The driving method according to claim 12, wherein,

in the case where the pixel circuit includes a light emission control circuit, the driving method further includes: a third stage;

in the third stage, in response to an enable signal provided by an enable signal terminal, the light emission control circuit transmits a first voltage signal provided by a first voltage signal terminal to the first node, the driving circuit generates a driving signal according to a potential of the second node and the first voltage signal from the first node, and the light emission control circuit further transmits the driving signal to a fourth node.

14. The driving method according to claim 13, wherein,

in the case where the pixel circuit includes a first reset circuit and a second reset circuit, the driving method further includes: a fourth stage;

in the fourth stage, in response to a reset signal provided by a reset signal terminal, the first reset circuit transmits an initial signal provided by an initial signal terminal to the second node; the second reset circuit transmits the initial signal to the fourth node.

15. A display device, comprising: the display substrate according to any one of claims 1 to 11.