CN114746931A

CN114746931A - Display device and driving method of display device

Info

Publication number: CN114746931A
Application number: CN202080083445.4A
Authority: CN
Inventors: 土屋春树; 木村圭; 三并徹雄
Original assignee: Sony Group Corp
Current assignee: Sony Group Corp
Priority date: 2019-12-19
Filing date: 2020-11-19
Publication date: 2022-07-12
Also published as: WO2021124785A1; DE112020006205T5; JP2021096420A

Abstract

A display device is provided which includes a plurality of scanning lines, a plurality of data lines, and a pixel unit in which rows are designated by the scanning lines and columns are designated by the data lines. In a display device, a row or column is specified by the output of an address decoder that decodes an address. A control signal line is provided which supplies a control signal to the address decoder together with an address. The address decoder is configured such that a plurality of rows or a plurality of columns adjacent to each other are simultaneously designated by the control signal.

Description

Display device and driving method of display device

Technical Field

The present technology relates to an active matrix type display device and a driving method for the display device.

Background

A display device using an organic light emitting diode (hereinafter referred to as an OLED (organic light emitting diode)) element or the like as a light emitting element is known. In the display device, a pixel circuit including a light emitting element, a transistor, and the like is provided corresponding to a pixel at each intersection between a scanning line (gate line) from a vertical scanning circuit and a data line (signal line) from a horizontal scanning circuit. When a data signal of a potential according to a gray scale of a pixel is applied to a gate of a transistor of a pixel circuit, the transistor supplies a current according to a voltage between the gate and a source thereof to a light emitting element, and the light emitting element emits light having luminance according to the gray scale.

Conventional vertical scanning circuits have been implemented by shift registers. The basic drive of the shift register circuit is line-sequential scanning by which lines to be written are sequentially selected one by one for each clock cycle. On the other hand, an address scanning method using an address decoding circuit instead of a shift register circuit is known (for example, refer to PTL 1). In addition to line-sequential scanning, the address scanning method makes it possible to perform scanning only within freely selected blocks.

[ list of references ]

[ patent document ]

[PTL 1]

JP 2008-020781A。

Disclosure of Invention

[ problem ] to

In addition to line-sequential scanning, the address scanning method enables high-speed operation and reduction in power consumption by making it possible to perform scanning only within freely selected blocks. However, in the ordinary address scanning method, a single address is assigned to each row, and therefore, a two-row simultaneous scanning function cannot be added.

Therefore, an object of the present technology is to provide a display device and a driving method for the display device, by which two-line simultaneous scanning can be realized in an address scanning method.

[ solution of problem ]

The present technology is a display device including a plurality of scan lines, a plurality of data lines, and a pixel unit in which a row is designated by the scan lines and a column is designated by the data lines, wherein the row or the column is designated by an output of an address decoder that decodes an address, a control signal line that supplies a control signal to the address decoder together with the address is provided, and the address decoder is configured such that a plurality of rows or columns adjacent to each other are designated at the same time by the control signal.

Drawings

FIG. 1 is a block diagram of an example of a display device to which the present techniques may be applied.

Fig. 2 shows a schematic diagram of a driving method of the display device.

Fig. 3 is a block diagram showing a part of the configuration of the first embodiment of the present technology.

Fig. 4 is a schematic diagram of an address table showing a relationship between a row and an address in the first embodiment of the present technology.

Fig. 5 is a timing chart illustrating an operation in one line scanning of the first embodiment.

Fig. 6 is a timing chart illustrating an operation in an odd field in two-line simultaneous scanning (MLS driving) of the first embodiment.

Fig. 7 is a timing chart illustrating an operation in an even field in two-row simultaneous scanning (MLS driving) of the first embodiment.

Fig. 8A and 8B are schematic diagrams of address tables for the odd field and the even field of the first embodiment, respectively.

Fig. 9 is a block diagram showing a part of the configuration of the second embodiment of the present technology.

FIG. 10 is a diagram of an address table in a second embodiment of the present technology.

Fig. 11 is a block diagram showing a part of the configuration of the third embodiment of the present technology.

Fig. 12 is a block diagram showing an operation in one line scanning of the third embodiment of the present technology.

Fig. 13 is a block diagram illustrating an operation in an odd field in the MLS drive of the third embodiment of the present technology.

Fig. 14 is a block diagram illustrating an operation in an even field in the MLS drive of the third embodiment of the present technology.

Fig. 15 is a block diagram showing a part of the configuration of the fourth embodiment of the present technology.

Detailed Description

The embodiments described below are preferred specific examples of the present technology and are subject to various limitations that are technically preferred. However, the scope of the present technology is not particularly limited to such embodiments unless otherwise indicated in the following description.

Before describing the present technology, an active matrix type driving circuit for a conventional display device will be described with reference to fig. 1. Fig. 1 is a block diagram describing a schematic configuration of a display device.

A display device including an active matrix type drive circuit, for example, an organic EL display device, includes a vertical scanning circuit (scanning line drive circuit) 11, a horizontal scanning circuit (data line drive circuit) 12, and a pixel unit 13, all of which are formed on a semiconductor substrate, for example, a silicon substrate. A plurality of (m) scan lines X1 to Xm from the vertical scan circuit 11 extend in the horizontal direction to the pixel unit 13, and a plurality of (n) data lines Y1 to Yn from the horizontal scan circuit 12 extend in the vertical direction. The pixel circuits are connected in a matrix with data lines extending in the vertical direction and scan lines extending in the horizontal direction. In each pixel circuit, pixel circuits (sub-pixel circuits) corresponding to pixels of three primary colors of R (red), G (green), and blue (B) are provided. Three pixels represent one point of the color image.

The vertical scanning circuit 11 described above performs vertical scanning by an address scanning method. Specifically, the vertical scanning circuit 11 is configured to appropriately select a freely selected row in accordance with scanning line address information from a display control circuit (not shown). In the embodiment of the present technology, the vertical scanning circuit 11 is configured such that it selects two or more rows adjacent to each other, for example, two rows adjacent to each other at the same time. By such driving as just described, two-row simultaneous scanning (two-row simultaneous driving or two-row simultaneous writing) can be performed.

Here, as the two-line simultaneous scanning method, a first driving method and a second driving method are available. The first driving method is two-line simultaneous scanning (hereinafter referred to as double driving), in which the combination of two lines is fixed between an odd field and an even field. The second driving method is two-line simultaneous scanning (hereinafter, referred to as MLS driving), in which the positions of two lines simultaneously scanned are shifted by one line in the vertical direction between the odd field and the even field. These driving methods are described. For example, assume that the number m of scanning lines of the display device is 960. As shown in fig. 2A, in the case of normal line writing, a signal is written to 480 (1 st, 3 rd, 5 th, 9 th lines) lines in an odd field, and a signal is written to 480 (2 nd, 4 th, 6 th, 960 th lines) lines in an even field. In a typical display, the odd and even fields are alternately repeated.

In the multiplication driving, two rows adjacent to each other are designated at the same time as depicted in fig. 2B. For example, in the odd field and the even field, the scanning line X1 of the first line and the scanning line X2 of the second line are designated at the same time. By the multiplication driving as described above, it is possible to shorten the time period required for display of one frame signal to half and increase the panel response speed to twice.

In the MLS drive, two-line simultaneous scanning is performed, and as shown in fig. 2C, one-line shift (one-line shift) is performed on the positions of two lines. In the odd field, a first line is specified, and two-line simultaneous scanning is performed for a second line and subsequent lines. For the last line, the signal for the last line of the even field (line 960) is provided. In the next even field, two-line simultaneous scanning is performed without performing one-line displacement. In the case of MLS driving, the panel response speed can be doubled similarly as in the multiplication driving. Further, the resolution in the vertical direction of an image of one frame formed by images of odd and even fields can be improved as compared with the multiplication driving.

A first embodiment of the present technology that performs MLS driving is described with reference to fig. 3. An address bus 21 for a predetermined number of bits (e.g., 12 bits) is provided so that 4096 scan addresses can be formed. In the address bus 21, a bit inverted from each address bit is formed by an inverter. Since the address buses output their bits and inverted phases in this manner, the number of lines equal to twice the required number of bits is arranged. The address bus 21 is connected to an address decoder 23. The control signal line 22 is provided between the address bus 21 and the address decoder 23. The scan lines X1, X2, … … are led from the address decoder 23. Note that in fig. 2, the arrangement of some scanning lines, that is, the scanning lines X1, X2, and X3 is illustrated, and the arrangement of the other scanning lines is omitted for simplicity of illustration.

The control signal line 22 supplies the control signal ODD for the ODD fields, the control signal EVEN for the EVEN fields, and the clock CLK to the address decoder 23. The address decoder 23 includes, for each scan line: an AND gate a1, a2, or A3 to which a predetermined bit of the address bus 21 is supplied; and OR gates (O11, O12) OR (O21, O22) OR gate O31, a control signal from the control signal line 22 and a predetermined bit of the address bus 21 being supplied to each OR gate.

The control signal lines 22 include three control signal lines, and CLK, ODD, and EVEN are supplied to the respective control signal lines. CLK is a clock signal and is a signal that defines timing. ODD and EVEN are control signals for two-line simultaneous scanning. Specifically, the ODD is supplied to one of OR gates provided for the address decoder 23, and the EVEN is supplied to the other of the OR gates. The other input of each OR gate is connected to a predetermined one of the address lines of the address bus 21.

The 12-bit address supplied to the address bus 21 is encoded in gray code. Gray codes have the following characteristics: the hamming distance between codes adjacent to each other in consecutive order is always 1. In fig. 4, an address table (a section from the first row to the eleventh row) is depicted in which addresses of designated rows in order from the first row are encoded in gray code. In the gray code, adjacent addresses differ only by one bit between high (indicating a high level (1)) and low (indicating a low level (0)).

In the address decoder 23, when all the inputs to the AND gate are high, the output of the AND gate is high AND the scan line connected to the AND gate is specified. For example, the address specifying the first row (scan line X1) is (000000000001). Thus, the least significant bit is supplied to the AND gate a1 without being inverted, AND the other 11 bits are inverted AND supplied to the AND gate a1, AND as a result, the scan line X1 is specified. The address designating the second row (scan line X2) is (000000000011). Thus, the least significant bit AND the second least significant bit are supplied to the AND gate a2 without being inverted, AND the other 10 bits are inverted AND supplied to the AND gate a2, AND as a result, an address specifying the scan line X2 is generated. The address designating the third row (scan line X3) is (000000000010). Thus, the second least significant bit is provided to the AND gate A3 without being inverted, while the other 11 bits are inverted AND provided to the AND gate A3, AND as a result, an address specifying the scan line X3 can be generated. Likewise, addresses designating any other scan lines may be similarly generated.

The control signal ODD is for ODD fields and the control signal EVEN is for EVEN fields. In the case where the ODD supplied to the OR gate is low, another bit (low OR high) appears at the output of the OR gate as is. In other words, the other bit is not masked. The same applies when EVEN is low. In the case of normal driving, ODD and EVEN become low. When the ODD supplied to the OR gate is high, the output of the OR gate is normally high even if the other bit is low OR high. In other words, ODD (high) is a signal masking another bit. Similarly, EVEN (high) is also the signal that masks the other bit.

The timing diagram in a single row scan is depicted in fig. 5. In a single line scan, ODD and EVEN are both low. The address of the address bus 21 is sequentially incremented in synchronization with the clock CLK. As described above, the scan signals for specifying the scan lines X1, X2, X3, … are sequentially output from the address decoder 23.

In the case of MLS driving, ODD (high) is supplied to OR gates O11, O21, and O31 in ODD fields, each of which outputs the least significant bit of the address, so that the low of the least significant bit of the address encoded in gray code becomes high, as shown in fig. 3. As enclosed by the blocks in fig. 4, two least significant bits of a pair of two consecutive addresses between which the least significant bits are opposite to each other can be set high by ODD (high). When an address for selecting the first row is supplied from the address bus 21, the output of the AND gate a1 becomes high, AND the scan line X1 is designated. Then, when an address for selecting the second row is supplied to the address bus 21, the output of the AND gate a2 AND the output of the AND gate A3 go high, the scan lines X2 AND X3 are specified, AND thus, two-row simultaneous scanning is performed. Thereafter, two-line simultaneous scanning is similarly performed.

A timing diagram of an odd field in MLS driving is depicted in fig. 6. The control signal ODD is high and the control signal EVEN is low. The row designation address is incremented by (2n +1) in synchronization with the clock CLK. In the case of the first address (1), an output (high) designating the scan line X1 is generated from the AND gate a1 of the address decoder 23. In the case of the next address (3), as shown in fig. 8A, the addresses adjacent to each other become the same as each other, and outputs (high) for specifying the scan lines X2 and X3 are generated from the address decoder 22. Thereafter, two-line simultaneous scanning is similarly performed.

In an EVEN field, EVEN may have two bits opposite each other in a pair of two consecutive addresses high, as surrounded by the box in fig. 4. For example, in the pair of the first address and the second address, since they do not coincide at the second least significant bit, EVEN is supplied to the OR gate O12 and the OR gate O22 that output the second least significant bit, respectively, and both the second least significant bits become high. Thus, when an address for selecting the first row is supplied from the address bus 21, the output of the AND gate a1 AND the output of the AND gate a2 become high, AND the scan lines X1 AND X2 are selected, respectively, AND two-row simultaneous scanning is performed. Thereafter, two-line simultaneous scanning is similarly performed.

A timing diagram of an even field in MLS driving is depicted in fig. 7. The control signal ODD is low and the control signal EVEN is high. Similarly to the odd field, the line designation address is incremented by (2n +1) in synchronization with the clock CLK. In the case of the first address (1), as shown in fig. 8B, the first address AND the second address become equal to each other, AND outputs (high) for specifying the scan lines X1 AND X2 are generated from AND gates a1 AND a2 of the address decoder 23, respectively. Thereafter, two-line simultaneous scanning is similarly performed.

In this way, the MLS driving is realized by exchanging combinations of rows to be paired with each other for each field period. Further, the multiplication driving can be realized in the state of any one of the odd field and the even field.

The first embodiment of the present technology described above is an address scanning type display device, and is configured such that a unique address is assigned to each decoder, and the decoders of the rows corresponding to the input address signals designate scanning lines. Also, in the present technology, the display device can be driven at twice the frequency by two-line simultaneous scanning without changing the data rate and the clock frequency. In MLS driving, combinations of rows paired with each other are alternately exchanged for each field. In addition, address encoding is performed using gray code. By using gray codes for the addresses assigned to each row, a two-row simultaneous scan is achieved. Further, by adding control lines, a pair of rows can be selected for each field. Adding a signal line for controlling a pair of rows to the address scanning method makes it possible to realize a circuit that performs simultaneous write operations of two rows using a single address signal.

Therefore, according to the first embodiment of the present technology, by implementing two-line simultaneous scanning (multiplication driving, MLS driving) in addition to partial scanning by the address decoder, an optimum driving method can be selected according to the video image type. Further, by combining the two driving methods within one frame period, it is possible to output a video image that realizes both the refresh rate and the resolution while suppressing the amount of video image data. Further, only the central field of view can be rendered at high resolution, while the peripheral field of view can be rendered at low resolution.

Now, a second embodiment of the present technology is described. The second embodiment performs multiplication driving. Fig. 9 shows a part of the configuration of the second embodiment. Elements corresponding to those in the configuration of the first embodiment described above are denoted by the same reference numerals.

The address code supplied to the address bus 21 is encoded in gray code, and a correspondence table between the row number and the address is described in fig. 10. The address for the first row is a12 bit all low code and the address for the second row is a code with only the least significant bit high. When the correspondence table is compared with the correspondence table between the row numbers and the addresses in the first embodiment, the addresses are shifted by one row.

Also, in the second embodiment, two-line simultaneous scanning, i.e., multiplication driving (refer to fig. 2B), which does not include one-line shift in any of the odd-numbered field and the even-numbered field, is performed. Thus, a single control signal line supplying the control signal DBL is provided. The control signal lines are connected to OR gates O1, O2, and O3 of the address decoder 23. The other input bits of the OR gates O1, O2, and O3 are the least significant bits.

In the address table shown in fig. 10, only the least significant bits are different from each other in a pair of addresses of rows adjacent to each other. Therefore, in a state where the control signal DBL is high, for example, in a case where an address (all bits are low) of the first row is supplied from the address bus 21, not only the output of the AND gate a1 but also the output of the AND gate a2 becomes high, AND the first row AND the second row are designated at the same time. Then, when an address for the third row is supplied, the third row and the fourth row are designated at the same time. Thereafter, two-line simultaneous scanning is performed in a similar manner, and multiplication driving is performed.

The second embodiment of the present technology described above is an address scanning type display device, and is configured to assign a unique address to each decoder and make high the outputs of the decoders corresponding to the row of the input address signal and the adjacent row. Also, in the present technology, the display device can be driven at twice the frequency by two-line simultaneous scanning without changing the data rate and the clock frequency. Further, by using a gray code for address allocation for each row, two-row simultaneous scanning is realized. The following configuration can be realized: signal lines for controlling pairs of rows scanned simultaneously by two rows are added to the address scanning method, and two rows are simultaneously specified with a single address signal.

Therefore, according to the second embodiment of the present technology, the refresh rate can be improved by realizing two-line simultaneous scanning (multiplication driving) in addition to the partial scanning by the address decoder.

A part of the configuration of the third embodiment of the present technology is described in fig. 11. The

address decoders

231, 232, 233, and 234 are connected to scan lines X1, X2, X3, and X4, respectively. The address decoder 231 includes AND gates a11 AND a12 AND an OR gate O1 to which outputs of the AND gates a11 AND a12 are supplied, AND an output of the OR gate O1 is connected to the scan line X1 of the first row. The address from the address bus is provided to AND gate a 11. Similar to the first and second embodiments, the address bus includes signal lines of 12 bits and signal lines in which bits are inverted. When an address designating the scan line X1 is input thereto, the AND gate a11 generates a high output. The output of the address decoder (AND gate) of the previous stage AND the control signal ODD are supplied to an AND gate a 12. The output of AND gate a12 is provided to OR gate O1.

The address decoder 232 includes AND gates a21 AND a22 AND an OR gate O2 to which outputs of the AND gates a21 AND a22 are supplied, AND an output of the OR gate O2 is connected to the scan line X2 of the second row. An address from the address bus is supplied to the AND gate a21, AND when an address specifying the scan line X2 is input, a high output is generated from the AND gate a 21. The output of AND gate a11 for the paired row address decoder 231 AND control signal EVEN are provided to AND gate a 22. The output of AND gate a22 is provided to OR gate O2.

Further, the address decoder 233 for the scanning line X3 of the odd-numbered row is configured similarly to the address decoder 231 for the scanning line X1, and the address decoder 234 for the scanning line X4 of the even-numbered row is configured similarly to the address decoder 232 for the scanning line X2. The output of the AND gate a41 of the address decoder 234 is connected to one side of the input of the AND gate of the row in the next stage.

In the third embodiment, it is not necessary that the address is encoded with gray code, and the address may be encoded with a normal binary number. In the third embodiment, a configuration for realizing the multiplication driving or the MLS driving is added to the address decoder for the normal one-line driving.

The third embodiment is further described with reference to fig. 12, 13 and 14. In the case of a single line scan, both ODD and EVEN are low. Therefore, as shown in fig. 12, the outputs of the AND gates a12, a22, a32, AND a42 become low, AND the scan lines are designated by the outputs of the AND gates a11, a21, a31, AND a41, respectively.

In the case of an odd field in two-line simultaneous scanning (MLS driving), the signal route is as shown in fig. 13 (the route is indicated by a thick solid line). ODD goes high and EVEN goes low. The scan line X1 for the first row is designated by high output from AND gate a12 AND OR gate O1. The high designation output by scan line X2 for the second row via AND gate A21 AND OR gate O2. Since the output of the AND gate a21 is supplied to the AND gate a32 of the address decoder 233 for the scan line X3 for the third row, the outputs via the AND gate a32 AND the OR gate O3 become high, AND the third row is also specified. In other words, the second and third rows are scanned simultaneously. Thereafter, two rows, denoted as a row pair in fig. 13, are scanned simultaneously.

In the case of an even field in two-line simultaneous scanning (MLS driving), the signal route is as shown in fig. 14 (the route is indicated by a thick solid line). EVEN is high and ODD is low. The scan line X1 for the first row is designated by a high output via AND gate a11 AND OR gate O1. Since the output of the AND gate a11 is supplied to the AND gate a22 of the address decoder 232 for the scan line X2 of the second row, the output of the AND gate a22 becomes high AND is output via the OR gate O2. Thus, the second row is also specified. In other words, the first and second rows are scanned simultaneously. Thereafter, two rows, represented as a row pair in fig. 14, are scanned simultaneously.

The third embodiment of the present technology described above is an address scanning type display device, and is configured such that a unique address is assigned to each decoder, and the decoders of the rows corresponding to the input address signals specify scanning lines. Further, in the present technology, the display device can be driven at twice the frequency by two-line simultaneous scanning without changing the data rate and the clock frequency. In the MLS drive, combinations of rows paired with each other are alternately exchanged for each field. Furthermore, adding control lines makes it possible to select two-line simultaneous scanning pairs for each field. Signal lines for controlling two-row simultaneous scanning pairs are added to the address scanning method, and therefore, a circuit for performing simultaneous write operations for two rows with a single address signal is realized.

According to the third embodiment of the present technology described above, by realizing two-line simultaneous scanning (multiplication driving, MLS driving) in addition to the partial scanning by the address decoder, an optimum driving method can be selected according to the video image type. Further, by combining the two driving methods within one frame period, it is possible to output a video image that realizes both the refresh rate and the resolution while suppressing the amount of video image data. Further, it is possible to realize driving for drawing only the central field of view at a high resolution and drawing the peripheral field of view at a low resolution.

Fig. 15 depicts a part of the configuration of the fourth embodiment of the present technology in which only the multiplication driving is performed. Similar to the third embodiment, address

decoders

231, 232, 233, and 234 are provided. A single control signal line supplying a control signal DBL is provided. For the address decoders 231 AND 233 for the odd rows (X1 AND X3), AND gates a11 AND a31 as address decoders are provided, respectively. In the address decoders 232 AND 234 for the even-numbered rows (X2 AND X4), the outputs of the AND gates a11 AND a31 of the lower (upper side in fig. 15) address decoders are supplied to the OR gates O2 AND O4, respectively.

In the fourth embodiment, in the case where the control signal DBL is low, normal one-line scanning is performed. In the case where the control signal DBL is high, when an odd-numbered row is designated, an even-numbered row next to the odd-numbered row is also designated. In this way, pairs of odd lines and even lines are designated at the same time, and multiplication driving is performed.

According to the fourth embodiment of the present technology described above, it is possible to increase the refresh rate while suppressing the amount of video image data by realizing two-line simultaneous scanning (multiplication driving) in addition to the partial scanning of the address decoder.

A fifth embodiment of the present technology realizes multi-column simultaneous scanning by applying the configuration of the first embodiment to the horizontal scanning side of a dot sequential scanning type panel. For horizontal scanning, an address scanning method is applied. Two modes are prepared for column alignment and each field is swapped. In other words, the MLS driving is performed on the horizontal scanning side.

A sixth embodiment of the present technology realizes simultaneous scanning of a plurality of columns by applying the arrangement of the second embodiment to the horizontal scanning side of a dot sequential scanning type panel. For horizontal scanning, an address scanning method is applied. In other words, the multiplication driving is performed on the horizontal side.

Although the embodiments of the present technology have been described specifically, the above-described embodiments are not restrictive and may be modified in various forms based on the technical idea of the present technology. Further, the modification mode may also be performed by appropriately combining one or more modifications freely selected. Also, the configurations, methods, steps, shapes, materials, numerical values, and the like of the above-described embodiments may be combined with each other unless departing from the subject matter of the present technology.

Although in the above-described embodiments, the OLED as the light emitting element is exemplified, the present technology can be applied to a display device using an element that emits light with luminance according to current, for example, an inorganic light emitting diode or an LED (light emitting diode).

Further, the display device according to the embodiment and the like is suitable for application of high-definition display in which the size of a pixel is small. Therefore, the display device can be applied as an electronic apparatus to a display device of a head-mounted display, smart glasses, a smart phone, an electronic viewfinder for a digital camera, or the like.

It should be noted that the present technology may also take the configuration described below.

(1)

A display device, comprising:

a plurality of scan lines;

a plurality of data lines; and

pixel units, wherein rows are designated by the scan lines and columns are designated by the data lines, wherein

The row or the column is specified by the output of an address decoder that decodes the address,

setting a control signal line for supplying a control signal to the address decoder together with the address, an

The address decoder is configured such that a plurality of rows or columns adjacent to each other are simultaneously designated by the control signal.

(2)

The display device according to (1), wherein,

the first driving method is performed in which positions of a plurality of rows or a plurality of columns designated at the same time between the odd-numbered field and the even-numbered field are the same.

(3)

The display device according to (1), wherein,

a second driving method is performed in which the positions of a plurality of rows or a plurality of columns designated at the same time are shifted by one row or one column between the odd-numbered field and the even-numbered field.

(4)

The display device according to (1), wherein,

a first driving method in which positions of a plurality of rows or a plurality of columns designated at the same time are the same between an odd field and an even field, and

a second driving method in which the positions of a plurality of rows or a plurality of columns designated at the same time are shifted by one row or one column between an odd field and an even field;

and (6) executing.

(5)

The display device according to any one of (1) to (4), wherein,

encoding an address specifying said row or said column with a gray code, and

the address decoder performs two-row simultaneous designation by masking one bit that differs between addresses of two consecutive rows or columns.

(6)

The display device according to any one of (1) to (5),

the address decoder includes logic circuitry to decode an address of the row or the column, an

Masking at least one bit of the logic circuit with the control signal.

(7)

A driving method of a display device including a plurality of scanning lines, a plurality of data lines, and pixel units in which rows are designated by the scanning lines and columns are designated by the data lines, wherein,

the row or the column is specified by an output of an address decoder that decodes the address, an

Control signals are supplied to the address decoder to simultaneously designate a plurality of rows or columns adjacent to each other.

[ list of reference numerals ]

11: vertical scanning circuit

12: horizontal scanning circuit

13: pixel unit

21: address bus

22: control signal line

23: an address decoder.

Claims

1. A display device, comprising:

a plurality of scanning lines;

a plurality of data lines; and

providing a control signal line that supplies a control signal to the address decoder together with the address, an

The address decoder is configured such that a plurality of rows or a plurality of columns adjacent to each other are simultaneously designated by the control signal.

2. The display device according to claim 1,

a first driving method is performed in which positions of a plurality of rows or a plurality of columns designated at the same time are the same between the odd field and the even field.

3. The display device according to claim 1,

a second driving method is performed in which positions of a plurality of lines designated at the same time are shifted by one line between the odd field and the even field or positions of a plurality of columns designated at the same time are shifted by one column between the odd field and the even field.

4. The display device according to claim 1, wherein a first driving method and a second driving method are performed,

in the first driving method, positions of a plurality of rows or a plurality of columns designated at the same time are the same between an odd field and an even field, and

in the second driving method, positions of a plurality of lines designated at the same time are shifted by one line between the odd field and the even field or positions of a plurality of columns designated at the same time are shifted by one column between the odd field and the even field.

5. The display device according to claim 1,

encoding the address specifying the row or the column with a Gray code, an

The address decoder performs two-row simultaneous designation by masking one bit that differs between addresses of two consecutive rows or two consecutive columns.

6. The display device according to claim 5,

Masking at least one bit of the logic circuit with the control signal.

7. A driving method of a display device including a plurality of scanning lines, a plurality of data lines, and pixel units in which rows are designated by the scanning lines and columns are designated by the data lines, wherein,

Control signals are supplied to the address decoder to simultaneously designate a plurality of rows or a plurality of columns adjacent to each other.