CN114745241A - Amplitude modulation signal demodulation device and power supply equipment - Google Patents

Amplitude modulation signal demodulation device and power supply equipment Download PDF

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Publication number
CN114745241A
CN114745241A CN202210484562.2A CN202210484562A CN114745241A CN 114745241 A CN114745241 A CN 114745241A CN 202210484562 A CN202210484562 A CN 202210484562A CN 114745241 A CN114745241 A CN 114745241A
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unit
voltage division
signal
voltage
analog signal
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CN114745241B (en
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周超
苟格
陈强
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Zhejiang Geoforcechip Technology Co Ltd
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Zhejiang Geoforcechip Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/80—Circuit arrangements or systems for wireless supply or distribution of electric power involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Near-Field Transmission Systems (AREA)

Abstract

The embodiment of the application provides an amplitude modulation signal demodulation device and power supply equipment, and relates to the technical field of electronics. The method comprises the following steps: the voltage division biasing circuit comprises a voltage division biasing circuit, a comparison unit and a processing unit; the voltage division biasing circuit is respectively electrically connected with the first input end of the comparison unit and the fixed power supply, and is used for carrying out voltage division biasing processing on the first analog signal sent by the voltage sampling unit to obtain a second analog signal; the second input end of the comparison unit is used for accessing the first analog signal, the output end of the comparison unit is electrically connected with the processing unit, and the comparison unit is used for comparing the first analog signal with the second analog signal and outputting a target digital signal to the processing unit; the processing unit is used for decoding the target digital signal to obtain target communication data. The comparison unit directly obtains a target digital signal according to the first analog signal and a second analog signal output by the voltage division biasing circuit, so that the target digital signal has stronger anti-interference capability and target communication data are more accurate.

Description

Amplitude modulation signal demodulation device and power supply equipment
Technical Field
The application relates to the technical field of electronics, in particular to an amplitude modulation signal demodulation device and power supply equipment.
Background
Wireless charging is an emerging technology that can lead the electric power revolution, compares in traditional wired charging mode, and wireless charging separates battery charging outfit and power, and it is safer to charge. In order to ensure the compatibility and universality of wireless charging, a QI protocol provides a complete wireless charging standard. In the wireless protocol of QI standard, during the wireless charging process, the power supply and the charging device communicate with each other through Amplitude Shift Keying (ASK) signals.
In the wireless communication process, the ASK signal is directly embodied in the waveform in the form of voltage. Therefore, in the prior art, the received ASK signal is generally demodulated by a voltage sampling method to obtain target data.
However, the voltage amplitude of the ASK signal is susceptible to external interference, so that the target data cannot be obtained through demodulation or the data is lost.
Disclosure of Invention
The object of the present application includes, for example, providing an amplitude modulation signal demodulation apparatus and a power supply device, wherein a comparison unit directly obtains a target digital signal according to a first analog signal and a second analog signal obtained after processing by a voltage division bias circuit. The target digital signal generated by the method has stronger anti-interference capability, and the obtained target communication data is more accurate.
The embodiment of the application can be realized as follows:
in a first aspect, the present application provides an amplitude modulated signal demodulation apparatus, the apparatus comprising:
the voltage division biasing circuit comprises a voltage division biasing circuit, a comparison unit and a processing unit;
the voltage division biasing circuit is respectively electrically connected with the first input end of the comparison unit and the fixed power supply, and is used for carrying out voltage division biasing processing on the first analog signal sent by the voltage sampling unit to obtain a second analog signal;
the second input end of the comparison unit is used for accessing the first analog signal, the output end of the comparison unit is electrically connected with the processing unit, and the comparison unit is used for comparing the first analog signal with the second analog signal and outputting a target digital signal to the processing unit;
and the processing unit is used for decoding the target digital signal to obtain target communication data.
In an alternative embodiment, the voltage divider bias circuit includes: the first pressure division unit, the second pressure division unit, the third pressure division unit and the ground pressure division unit;
the first voltage division unit is electrically connected with the second voltage division unit, the third voltage division unit, the fixed power supply and the ground voltage division unit respectively;
the second voltage division unit is electrically connected with the third voltage division unit, the voltage sampling unit and the ground voltage division unit respectively;
the third voltage division unit is electrically connected with the comparison unit and the ground voltage division unit.
In an alternative embodiment, the first pressure dividing unit includes: a first resistor;
the first end of the first resistor is electrically connected with a fixed power supply, and the second end of the first resistor is electrically connected with the second voltage division unit, the third voltage division unit and the ground voltage division unit respectively.
In an alternative embodiment, the second voltage division unit includes: a second resistor;
the first end of the second resistor is electrically connected with the voltage sampling unit, and the second end of the second resistor is electrically connected with the first voltage division unit, the third voltage division unit and the ground voltage division unit respectively.
In an alternative embodiment, the third partial pressure unit includes: a third resistor;
the first end of the third resistor is electrically connected with the first voltage division unit, the second voltage division unit and the ground voltage division unit respectively, and the second end of the third resistor is connected with the first input end of the comparison unit.
In an optional implementation manner, the comparing unit is specifically configured to:
and comparing the first analog signal with the second analog signal to obtain a voltage comparison result, and determining the target digital signal according to the voltage comparison result.
In an optional implementation manner, the processing unit is specifically configured to:
determining the signal duration of the target digital signal according to the plurality of edge change time values of the target digital signal; and if the signal duration is longer than the preset signal period, decoding the target digital signal to obtain target communication data.
In an optional implementation manner, the processing unit is specifically configured to:
when the target digital signal is subjected to edge change for the first time, acquiring a first edge change time value; sequentially collecting edge change time values corresponding to edge changes of the target digital signal, and taking the edge change time value collected at the last time as a second edge change time value; and determining the signal time length of the target digital signal according to the difference value of the second edge change time value and the first edge change time value.
In an alternative embodiment, the comparison unit comprises: a comparator;
a first access end of the comparator is connected with the voltage division biasing circuit, a second access end of the comparator is used for receiving a first analog signal sent by the voltage sampling unit, and an output end of the comparator is connected with the processing unit;
the processing unit includes: a micro control unit;
the first end of the micro control unit is connected with the comparison unit, and the second end of the micro control unit is used for outputting target communication data.
In a second aspect, the present application provides a power supply apparatus comprising: a voltage sampling unit and an amplitude modulation signal demodulation device according to any one of the first aspect electrically connected with the voltage sampling unit;
the voltage sampling unit is used for preprocessing an amplitude shift keying signal sent by the charging equipment to obtain a first analog signal.
The beneficial effects of the embodiment of the application include:
by adopting the amplitude modulation signal demodulation device and the power supply equipment, the voltage division bias unit is used for carrying out voltage division bias processing on the first analog signal sent by the voltage sampling unit to obtain the second analog signal, and the comparator can directly obtain the target digital signal according to the comparison result of the first analog signal and the second analog signal. This application includes by adopting less device: the voltage division bias circuit and the comparison unit can directly obtain the target digital signal, and the obtained target digital signal has strong anti-interference capability and high precision.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a waveform diagram of an ASK signal emitted from a charging device in the prior art;
FIG. 2 is a schematic diagram of a prior art peak detector circuit;
FIG. 3 is a waveform diagram of an envelope signal output by a peak detection circuit in the prior art;
fig. 4 is a waveform diagram of an output signal obtained by processing an envelope signal in the prior art;
fig. 5 is a schematic structural diagram of an amplitude modulation signal demodulation system according to an embodiment of the present application;
fig. 6 is a schematic waveform diagram of an input signal and an output signal of an am signal demodulation apparatus according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an am signal demodulating apparatus according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an amplitude modulation signal demodulation apparatus according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of an amplitude-modulated signal demodulating apparatus according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of an amplitude modulation signal demodulation apparatus according to an embodiment of the present application.
Icon: 1-a charging device; 2-a power supply device; 10-a voltage sampling unit; 20-amplitude modulated signal demodulating means; 201-a voltage division bias circuit; 2011-a first partial pressure unit; 2012-a second pressure dividing unit; 2013-a third partial pressure unit; 2014-a ground partial pressure unit; 202-a comparison unit; 2021-a comparator; 203-a processing unit; 2031-a micro control unit; 204-fixed power supply.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the present invention product is usually put into use, it is only for convenience of describing the present application and simplifying the description, but it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present application.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
The QI standard proposed by the wireless charging alliance is widely applied to the field of wireless charging, the QI protocol is a wireless charging standard between a power supply device and a charging device, after the power supply device and the charging device establish communication connection, information content is generated by the charging device according to the standard of the QI protocol and then is transmitted to the power supply device, so that the power supply device can determine charging information such as charging power of the power supply device.
The QI protocol determines the information content, and bidirectional communication between the power supply device and the charging device may be performed by Amplitude Shift Keying (ASK), Frequency Shift Keying (FSK), or the like. The ASK communication method is a communication method in which ASK signals are directly embodied in waveforms in the form of voltage, and is a common communication method in wireless charging.
In the prior art, the demodulation mode of the wireless charging power supply device for ASK signals generally adopts a voltage sampling mode, including: after processing hardware circuits such as detection, filtering, amplification and the like of an ASK signal peak value sent by a charging device, a "sine wave-like" signal is obtained, and finally the "sine wave" is processed by a micro control Unit (MCU for short) to obtain target data.
As shown in fig. 1, the charging device sends out ASK signal by adjusting the load, and voltage amplitude variation is generated on the coil of the power supply device, and the waveform of the input signal is shown in the white broadband portion of fig. 1.
Next, an input signal sign _ N having a waveform shown in a white wide band portion of fig. 3 is input to the peak detection circuit shown in fig. 2, and subjected to resistance voltage division and dc blocking capacitance processing, thereby outputting an envelope signal VDM having a waveform shown in a white line of fig. 3. The signal waveform TP3 shown in fig. 3 is a signal waveform after passing through the resistor R8 of the peak detector circuit, and the signal waveform TP4 is a signal waveform after passing through the envelope of the peak detector circuit.
Finally, the output VDM envelope signal is subjected to voltage division, filtering and amplification to obtain a "sine-like wave" shown in fig. 4, and the sine-like wave is input to the MCU, processed by the MCU, and decoded to obtain data in the ASK signal sent by the charging device.
According to the process, in the prior art, the demodulated sine-like wave is not accurate enough and is easy to be interfered by the outside in a voltage sampling mode, so that the MCU is difficult to obtain accurate data in the ASK signal through analysis.
Based on this, the applicant has proposed an amplitude modulation signal demodulation apparatus and a power supply device through research, wherein the comparison unit can compare the second analog signal output by the voltage division bias circuit with the first analog signal, directly output a target digital signal, and then decode the target digital signal by the processing unit to obtain target communication data. In this way, a target digital signal with higher interference rejection capability can be obtained in addition to the "sine-like wave" so as to improve the accuracy of target communication data.
Fig. 5 is a schematic structural diagram of a power supply device 2 according to an embodiment of the present application, and as shown in fig. 5, the power supply device 2 includes: a voltage sampling unit 10 and an amplitude modulation signal demodulation apparatus 20 electrically connected with the voltage sampling unit 10 as described in the following embodiments.
The voltage sampling unit 10 is configured to preprocess an amplitude shift keying signal sent by the charging device 1 to obtain a first analog signal.
The voltage sampling unit 10 may include a peak detection circuit, a voltage dividing circuit, a filter circuit, an amplification circuit, and the like, and is configured to receive the ASK signal sent by the charging device 1, and perform resistance voltage dividing processing, blocking capacitance processing, voltage dividing processing, filter processing, and amplification processing on the ASK signal to obtain a first analog signal.
Since the ASK signal is directly embodied in the waveform in the form of voltage, the first analog signal may be an analog signal having the same period of voltage fluctuation as the ASK signal emitted from the charging apparatus 1.
The amplitude modulation signal demodulation device 20 is configured to perform voltage division and offset processing on the first analog signal to obtain a second analog signal, compare the first analog signal with the second analog signal to obtain a target digital signal, and perform decoding processing on the target digital signal to obtain target communication data.
The am signal demodulating apparatus 20 may first perform a voltage division bias process on the first analog signal through a voltage division bias circuit to obtain a second analog signal. The second analog signal after the voltage division and bias processing may be an analog signal having the same voltage fluctuation period as the first analog signal but different voltage peak value.
Next, the comparison unit in the am signal demodulation apparatus 20 compares the first analog signal and the second analog signal. The comparing unit may include a comparator, and the comparator may be configured to compare the input first analog signal and the input second analog signal according to an operation principle of the comparator, so as to determine a magnitude relationship between the input two analog signals. In this embodiment, as shown in fig. 6, if the first analog signal is greater than the second analog signal, the output value of the comparator is a binary digital signal 1. On the contrary, if the first analog signal is smaller than the second analog signal, the output value of the comparator is binary digit 0. When the first analog signal is equal to the second analog signal, the output value of the comparator is equal to the first analog signal and the second analog signal. Thus, a target digital signal having a square wave waveform is obtained. Compared with the first analog signal, the square waveform of the target digital signal is more stable, and the anti-jamming capability is stronger.
Finally, the processing unit in the am signal demodulation apparatus 20 analyzes the square wave signal, since the ASK signal represents a logic digital 1 by a high level and represents a logic digital 0 by a low level. The processing unit can analyze the square waveform of the target digital signal according to the data to obtain a binary number string for describing the target communication data. And the processing unit analyzes the binary digit string according to the QI protocol to obtain target communication data.
Next, the structure and the operation flow of the above-described amplitude modulation signal demodulation apparatus 20 according to the embodiment of the present application will be described in detail.
Fig. 7 is a schematic structural diagram of an am signal demodulation apparatus provided in the present application, which may be disposed on a wireless charging power supply apparatus and used for demodulating an ASK signal sent by a charging apparatus. As shown in fig. 7, the apparatus includes:
a voltage division bias circuit 201, a comparison unit 202 and a processing unit 203.
The voltage dividing and biasing circuit 201 may be a circuit that performs voltage dividing and biasing processing on the first analog signal, and may be composed of a plurality of voltage dividing resistors.
The comparison unit 202 may be an electronic device for comparing the first analog signal and the second analog signal to determine their magnitude relationship. Functionally, the comparing unit 202 can be equivalent to an analog-to-digital converter, and converts the two input analog signals into digital signals.
The processing unit 203 may be an arithmetic device having arithmetic processing capability for performing analysis processing on the target digital signal output by the comparison unit 202.
The voltage division bias circuit 201 is electrically connected to the first input terminal of the comparing unit 202 and the fixed power supply 204, and the voltage division bias circuit 201 is configured to perform voltage division bias processing on the first analog signal sent by the voltage sampling unit 10 to obtain a second analog signal.
The voltage division bias processing may be a processing procedure of increasing the positive voltage peak value or decreasing the negative voltage peak value of the first analog signal output by the voltage sampling unit 10 through the voltage division of the fixed power supply 204 and the plurality of resistors, as shown in fig. 6, the voltage fluctuation period of the second analog signal after the voltage division bias processing is the same as the voltage fluctuation period of the first analog signal, but the voltage peak value is different.
A second input end of the comparing unit 202 is configured to access the first analog signal, an output end of the comparing unit 202 is electrically connected to the processing unit 203, and the comparing unit 202 is configured to compare the first analog signal and the second analog signal and output a target digital signal to the processing unit 203.
The first input end of the comparing unit 202 is connected to the second analog signal after the voltage division and bias processing by the voltage division and bias unit, and the first input end is connected to the first analog signal.
The comparing unit 202 is configured to output a target digital signal according to a comparison result of the first analog signal and the second analog signal that are input simultaneously. With continued reference to fig. 6, when the first analog signal is greater than the second analog signal, the comparing unit 202 continues to output the digital signal 1. When the first analog signal is smaller than the second analog signal, the comparing unit 202 continuously outputs the digital signal 0. When the first analog signal is equal to the second analog signal, the comparing unit 202 outputs voltages equal to the first analog signal and the second analog signal as a signal rising edge and a signal falling edge of the square wave signal. Thus, the comparison unit 202 obtains the target digital signal with a square wave waveform and outputs the target digital signal to the processing unit 203.
The processing unit 203 is configured to perform decoding processing on the target digital signal to obtain target communication data.
After receiving the target digital signal, the processing unit 203 converts the target digital signal into a corresponding binary string, and then analyzes the target digital signal according to the QI protocol to obtain target communication data.
In this embodiment, the comparison unit of the am signal demodulation apparatus directly obtains the target digital signal according to the second analog signal and the first analog signal obtained after the voltage division and offset processing. By adopting fewer devices, the target digital signal with stronger anti-interference capability is realized, and the target communication data analyzed by the processing unit can be more accurate.
Alternatively, as shown in fig. 8, the voltage dividing bias circuit includes: a first pressure dividing unit 2011, a second pressure dividing unit 2012, a third pressure dividing unit 2013, and a ground pressure dividing unit 2014.
The first voltage dividing unit 2011 is electrically connected to the second voltage dividing unit 2012, the third voltage dividing unit 2013, the fixed power source 204, and the ground voltage dividing unit 2014, respectively.
The second voltage dividing unit 2012 is electrically connected to the third voltage dividing unit 2013, the voltage sampling unit 10, and the ground voltage dividing unit 2014, respectively.
The third voltage dividing unit 2013 is electrically connected to the comparing unit 202 and the ground voltage dividing unit 2014.
The first voltage division unit 2011 is connected to a fixed power supply to realize voltage division of the second voltage division unit 2012. Illustratively, the fixed power supply may be 3.3V in size.
Alternatively, as shown in fig. 9, the ground voltage dividing unit 2014 may include a fourth resistor R4 having a resistance value of 100K, a first end of the fourth resistor R4 is connected to the first voltage dividing unit 2011, the second voltage dividing unit 2012 and the third voltage dividing unit 2013, and a second end of the fourth resistor R4 is grounded.
The fourth resistor R4 may be used to control the voltage values at the output terminals of the first voltage divider 2011 and the second voltage divider 2012.
According to the connection relationship between the units and the ohm's law of the partial circuit, the sum of the current value of the first voltage division unit 2011 and the current value of the second voltage division unit 2012 is equal to the current value of the third voltage division unit 2013. That is, the sum of the voltage difference between the power voltage of the fixed power source at the input terminal of the first voltage division unit 2011 and the first voltage at the output terminal of the first voltage division unit 2011 and the voltage difference between the analog voltage of the first analog signal at the input terminal of the second voltage division unit 2012 and the first voltage at the output terminal of the second voltage division unit 2012 is equal to the first voltage value at the input terminal of the third voltage division unit 2013.
According to the above relationship, the variation of the voltage peak of the second analog signal output by the third voltage dividing unit 2013 with respect to the first analog signal can be calculated.
In the embodiment, the first analog signal is converted into the second analog signal with the same voltage fluctuation period but different voltage peak values through the voltage division of each unit in the voltage division bias unit, so that the comparator can generate the target digital signal according to the first analog signal. This way of generating the second analog signal is faster and has fewer peripheral devices.
Alternatively, as shown in fig. 9, the first partial pressure unit 2011 includes: a first resistor R1.
A first end of the first resistor R1 is electrically connected to the fixed power source 204, and a second end of the first resistor R1 is electrically connected to the second voltage dividing unit 2012, the third voltage dividing unit 2013, and the ground voltage dividing unit 2014, respectively.
The first resistor R1 may be a resistor with a resistance of 100K, and is connected to the fixed power source 204 for dividing the voltage of the second voltage dividing unit 2012.
Alternatively, with continued reference to fig. 9, the second pressure dividing unit 2012 includes: and a second resistor R2.
A first end of the second resistor R2 is electrically connected to the voltage sampling unit 10, and a second end of the second resistor R2 is electrically connected to the first voltage dividing unit 2011, the third voltage dividing unit 2013, and the ground voltage dividing unit 2014, respectively.
The second resistor R2, which may be a resistor with a resistance of 100K, is connected to the voltage sampling unit 10 for inputting the first analog signal.
Alternatively, as shown in fig. 9, the third voltage division unit 2013 includes: and a third resistor R3.
A first terminal of the third resistor R3 is electrically connected to the first voltage dividing unit 2011, the second voltage dividing unit 2012 and the ground voltage dividing unit 2014, respectively, and a second terminal of the third resistor R3 is connected to the first input terminal of the comparing unit 202.
The third resistor R3 may be a resistor with a resistance of 100K, and is used for dividing the voltage of the first resistor of the first voltage dividing unit 2011 and the voltage of the second resistor of the second voltage dividing unit 2012.
Since the first resistor R1, the second resistor R2, and the third resistor R3 are all linear devices, complying with thevenin theorem, as shown in fig. 9, when the resistance values of the resistors are equal, it can be obtained:
Figure BDA0003628720890000131
further, the method can be obtained as follows:
Figure BDA0003628720890000132
due to UiDirect current component of
Figure BDA0003628720890000133
From U2Partial pressure value of UiAc component of
Figure BDA0003628720890000134
From the filtering of the dc blocking capacitance, then the following can be obtained:
Figure BDA0003628720890000135
further, the method can be obtained as follows:
Figure BDA0003628720890000136
Figure BDA0003628720890000137
wherein, UiIs the voltage value, U, of the first analog signal output by the voltage sampling unit 101Is the voltage value at the junction of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4, U2For a fixed voltage value, U, output by the fixed power supply 204oIs the voltage value of the second analog signal output from the output terminal of the third resistor R3.
According to the calculation, the voltage value U of the second analog signal is obtainedoIs the voltage value U of the first analog signaliAc component of
Figure BDA0003628720890000141
One third of the result decays. Thus, the comparison unit attenuates by a factor of three in dependence on the first analog signal and the first analog signalThe resulting second analog signal can then output the square wave signal shown in fig. 6 as the target digital signal.
In this embodiment, the resistors with the same resistance constitute a voltage division bias circuit, and the input first analog signal can be processed into the second analog signal with the same voltage fluctuation value and attenuated voltage value by using fewer devices, so that the precision of the target digital signal is improved.
Alternatively, as shown in fig. 10, the comparison unit 202 includes: a comparator 2021.
A first input end of the comparator 2021 is connected to the voltage dividing bias circuit, a second input end of the comparator 2021 is configured to receive the first analog signal sent by the voltage sampling unit 10, and an output end of the comparator 2021 is connected to the processing unit 203.
The comparator 2021 is a device that can perform a voltage comparison function, and compares the input first analog signal and second analog signal to generate a target digital signal according to a magnitude relationship between the two signals.
Optionally, with continued reference to fig. 10, the processing unit 203 comprises: a micro control unit 2031.
A first terminal of the micro control unit 2031 is connected to the comparison unit 202, and a second terminal of the micro control unit 2031 is used for outputting target communication data.
The micro control Unit 2031 (MCU for short) may be a chip-level calculator capable of performing different combination controls according to different application scenarios. In the embodiment of the present application, the mcu 2031 is configured to convert the target digital signal output by the comparator 2021 into a binary string, and is further configured to decode the binary string according to QI protocol to generate target communication data.
In this embodiment, the comparator compares the first analog signal with the second analog signal, and the obtained target digital signal has a stronger anti-interference capability. And the MCU decodes the generated target communication data, so that the accuracy is higher.
Optionally, the comparing unit is specifically configured to: and comparing the first analog signal with the second analog signal to obtain a voltage comparison result, and determining a target digital signal according to the voltage comparison result.
As can be seen from the above description, the comparator in the comparing unit can compare the first analog signal and the second analog signal to output corresponding voltages according to the magnitudes of the first analog signal and the second analog signal, so as to obtain the target digital signal with a square wave waveform.
In this embodiment, the comparison unit can output the target digital signal in a manner of a smaller time delay, and compared with the first analog signal, the target digital signal is not difficult to analyze or data is lost due to a change in waveform, and the anti-interference capability is stronger.
Optionally, the processing unit is specifically configured to: determining the signal duration of the target digital signal according to the plurality of edge change time values of the target digital signal; and if the signal duration is longer than the preset signal period, decoding the target digital signal to obtain target communication data.
When the frequency of the input ASK signal is 2KHz, the duration of the preset signal cycle may be set to 500 microseconds, and further, when the acquisition error of the half-cycle signal is 30%, the duration of the half-cycle signal cycle may be set to [150, 350 ]. When the acquisition error of the full-period signal is 40%, the duration of the full period can be set to [350, 650 ].
It can be understood that, when the target digital signal is a square wave waveform shown in fig. 6, the processing unit may determine the time length of the target digital signal acquired this time according to the difference between the time values of the edge changes of two adjacent acquired edges, and then compare the time length of the target digital signal with the time length of the preset signal period, so as to obtain the number of signal periods included in the target digital signal acquired this time.
If the number of signal cycles is larger than the maximum duration of a preset signal cycle, which is 650 microseconds, the target digital signal can be considered as valid data, and the valid data is further decoded to obtain target communication data.
The processing unit is specifically configured to: when the edge of the target digital signal changes for the first time, collecting a first edge change time value; sequentially collecting edge change time values corresponding to edge changes of the target digital signal, and taking the edge change time value collected at the last time as a second edge change time value; and determining the signal duration of the target digital signal according to the difference value between the second edge change time value and the first edge change time value.
As can be understood by those skilled in the art, the target digital signal shown in fig. 6 has a rising edge change and a falling edge change in one cycle, so that the micro control unit of the processing unit can trigger an interrupt processing function each time an edge signal change occurs, and determine a difference between an edge change time value of the currently acquired target digital signal and an edge change time value of the first acquired target digital signal, so as to obtain the signal duration of the target digital signal.
In this way, after the difference is obtained through each calculation, the micro control unit judges the signal duration of the target digital signal, optionally, if the signal duration of the target digital signal is greater than the maximum duration of a preset signal period of 650 microseconds, the target digital signal can be further checked, and if the check is passed, the target digital signal can be decoded to obtain the target communication data. If the verification is not passed, the target digital signal can be deleted.
In this embodiment, the processing unit acquires and judges the edge variation value of the target digital signal, so as to determine whether the target digital signal is valid data, reduce the workload of the processing unit in decoding invalid data, and improve the processing efficiency.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. An apparatus for demodulating an amplitude-modulated signal, the apparatus comprising:
the voltage division biasing circuit comprises a voltage division biasing circuit, a comparison unit and a processing unit;
the voltage division biasing circuit is respectively electrically connected with the first input end of the comparison unit and the fixed power supply, and is used for carrying out voltage division biasing processing on the first analog signal sent by the voltage sampling unit to obtain a second analog signal;
the second input end of the comparison unit is used for accessing the first analog signal, the output end of the comparison unit is electrically connected with the processing unit, and the comparison unit is used for comparing the first analog signal with the second analog signal and outputting a target digital signal to the processing unit;
and the processing unit is used for decoding the target digital signal to obtain target communication data.
2. The amplitude-modulated signal demodulating apparatus according to claim 1, wherein the voltage-dividing bias circuit includes: the first voltage division unit, the second voltage division unit, the third voltage division unit and the ground voltage division unit are arranged in parallel;
the first voltage division unit is electrically connected with the second voltage division unit, the third voltage division unit, the fixed power supply and the ground voltage division unit respectively;
the second voltage division unit is electrically connected with the third voltage division unit, the voltage sampling unit and the ground voltage division unit respectively;
the third voltage division unit is electrically connected with the comparison unit and the ground voltage division unit.
3. The amplitude-modulated signal demodulating apparatus according to claim 2, wherein the first voltage dividing unit includes: a first resistor;
the first end of the first resistor is electrically connected with a fixed power supply, and the second end of the first resistor is electrically connected with the second voltage division unit, the third voltage division unit and the ground voltage division unit respectively.
4. The amplitude-modulated signal demodulation apparatus according to claim 2, wherein the second voltage division unit comprises: a second resistor;
the first end of the second resistor is electrically connected with the voltage sampling unit, and the second end of the second resistor is electrically connected with the first voltage division unit, the third voltage division unit and the ground voltage division unit respectively.
5. The amplitude-modulated signal demodulation apparatus according to claim 2, wherein said third voltage dividing unit comprises: a third resistor;
the first end of the third resistor is electrically connected with the first voltage division unit, the second voltage division unit and the ground voltage division unit respectively, and the second end of the third resistor is connected with the first input end of the comparison unit.
6. The amplitude-modulated signal demodulation apparatus of claim 1, wherein the comparing unit is specifically configured to:
and comparing the first analog signal with the second analog signal to obtain a voltage comparison result, and determining the target digital signal according to the voltage comparison result.
7. The amplitude-modulated signal demodulation apparatus of claim 1, wherein the processing unit is specifically configured to:
determining the signal duration of the target digital signal according to the plurality of edge change time values of the target digital signal; and if the signal duration is greater than a preset signal period, decoding the target digital signal to obtain target communication data.
8. The amplitude-modulated signal demodulation apparatus of claim 7, wherein the processing unit is specifically configured to:
when the target digital signal is subjected to edge change for the first time, acquiring a first edge change time value; sequentially collecting edge change time values corresponding to edge changes of the target digital signal, and taking the edge change time value collected at the last time as a second edge change time value; and determining the signal duration of the target digital signal according to the difference value between the second edge change time value and the first edge change time value.
9. The amplitude-modulated signal demodulation apparatus according to claim 1, wherein said comparison unit comprises: a comparator;
a first access end of the comparator is connected with the voltage division biasing circuit, a second access end of the comparator is used for receiving a first analog signal sent by the voltage sampling unit, and an output end of the comparator is connected with the processing unit;
the processing unit includes: a micro control unit;
the first end of the micro control unit is connected with the comparison unit, and the second end of the micro control unit is used for outputting target communication data.
10. A power supply apparatus characterized by comprising: a voltage sampling unit and an amplitude modulation signal demodulation apparatus according to any one of claims 1 to 9 electrically connected to the voltage sampling unit;
the voltage sampling unit is used for preprocessing an amplitude shift keying signal sent by the charging equipment to obtain a first analog signal.
CN202210484562.2A 2022-05-06 2022-05-06 Amplitude modulation signal demodulation device and power supply equipment Active CN114745241B (en)

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