CN114743875A - Gallium oxide diode device and preparation method thereof - Google Patents
Gallium oxide diode device and preparation method thereof Download PDFInfo
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 108
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 108
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000004642 Polyimide Substances 0.000 claims abstract description 50
- 229920001721 polyimide Polymers 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 238000004528 spin coating Methods 0.000 claims description 2
- 238000000227 grinding Methods 0.000 abstract description 11
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910015844 BCl3 Inorganic materials 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000009987 spinning Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
The application is applicable to the technical field of semiconductor device manufacturing, and provides a gallium oxide diode device and a preparation method thereof, wherein the preparation method comprises the following steps: preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer; rotating the gallium oxide substrate by a first inclination angle and a second inclination angle in two opposite directions respectively by taking a horizontal plane as a reference, and etching the gallium oxide epitaxial layer covered by the dielectric mask layer, wherein the first inclination angle and the second inclination angle are both smaller than 90 degrees; preparing a polyimide layer with a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer; removing the dielectric mask layer, and forming a NiO layer on the upper surface of the area, corresponding to the dielectric mask layer, on the gallium oxide epitaxial layer and the polyimide layer, and on the upper surface of the area, close to the dielectric mask layer, on the polyimide layer; forming a first electrode layer on the NiO layer; and forming a second electrode layer on the lower surface of the gallium oxide substrate. The gallium oxide positive angle-grinding terminal structure can be easily realized, and the pressure resistance of a device is improved.
Description
Technical Field
The application belongs to the technical field of semiconductor device manufacturing, and particularly relates to a gallium oxide diode device and a preparation method thereof.
Background
Ultra-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices in recent years, and are expected to replace traditional Si-based power devices in certain specific fields. However, the mirror-induced barrier lowering effect is a bottleneck problem limiting the characteristics of the gan schottky diode. The difficulty of gallium oxide P-type injection is very high, the requirements of a field plate structure on the quality of a medium are strict, the reliability of the medium is high, and the like, so that the development of a novel terminal structure is imperative.
The angle grinding terminal is one of important terminal technologies for improving the performance of a power diode device, and the conventional preparation method is to prepare a P-type layer by injection or epitaxy and then realize the angle grinding terminal by a small-angle inclination angle etching technology. However, gallium oxide lacks a P-type doping technology, and cannot be used for realizing an angle grinding terminal by using an etching technology after a P-type layer is prepared, so that a new preparation technology needs to be developed to realize an angle grinding terminal structure of gallium oxide, particularly a positive angle grinding terminal, and the pressure resistance of a device is improved.
Disclosure of Invention
In order to overcome the problems in the related art, the embodiment of the application provides a gallium oxide diode device and a preparation method thereof, which can easily realize a gallium oxide positive angle grinding terminal structure and effectively improve the pressure resistance of the diode device.
The application is realized by the following technical scheme:
in a first aspect, an embodiment of the present application provides a method for manufacturing a gallium oxide diode device, including:
preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer, wherein part of the gallium oxide epitaxial layer is not covered by the dielectric mask layer; the gallium oxide epitaxial layer is formed on the upper surface of the gallium oxide substrate;
rotating the gallium oxide substrate by a first inclination angle and a second inclination angle in two opposite directions respectively by taking a horizontal plane as a reference, and etching the gallium oxide epitaxial layer covered by the dielectric mask layer, wherein the first inclination angle and the second inclination angle are both smaller than 90 degrees;
preparing a polyimide layer in a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer, wherein part of the dielectric mask layer is not covered by the polyimide layer;
removing the medium mask layer, and forming a NiO layer on the area corresponding to the medium mask layer on the gallium oxide epitaxial layer and on the upper surface of the area close to the medium mask layer on the polyimide layer;
forming a first electrode layer on the NiO layer;
and forming a second electrode layer on the lower surface of the gallium oxide substrate.
In a possible implementation manner of the first aspect, the preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer includes:
preparing a dielectric mask layer on the gallium oxide epitaxial layer;
preparing a first photoresist layer on the medium mask layer;
etching the first photoresist layer to expose part of the dielectric mask layer;
preparing a metal mask layer on the first photoresist layer and the dielectric mask layer;
stripping the metal mask layer on the first photoresist layer, and removing the first photoresist layer to form a metal mask layer with a preset pattern;
and etching the exposed part of the dielectric mask layer to form the dielectric mask layer with the preset pattern.
In a possible implementation manner of the first aspect, the first inclination angle and the second inclination angle range are both: 30 to 60.
In one possible implementation manner of the first aspect, the first inclination angle is equal to the second inclination angle.
In a possible implementation manner of the first aspect, the preparing a polyimide layer in a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer includes:
and before the polyimide layer with the preset shape is prepared, removing the metal mask layer with the preset pattern on the medium mask layer.
Preparing a polyimide layer with a preset shape on the gallium oxide epitaxial layer and the medium mask layer, wherein the preparation method comprises the following steps:
spin-coating polyimide on the surfaces of the gallium oxide epitaxial wafer and the dielectric mask layer;
etching the polyimide to expose the dielectric mask layer;
and curing the polyimide at a high temperature to form a polyimide layer with a preset shape.
In one possible implementation manner of the first aspect, the forming a NiO layer on the gallium oxide epitaxial layer in a region corresponding to the dielectric mask layer and at an edge of an upper surface of the polyimide layer includes:
forming a second photoresist layer at an edge of an upper surface of the polyimide layer such that a portion of the upper surface of the polyimide layer is exposed;
preparing the NiO layer on the exposed upper surface of the polyimide layer and the gallium oxide epitaxial layer;
and removing the second photoresist layer.
In one possible implementation manner of the first aspect, the NiO layer is filled in a self-aligned manner.
In one possible implementation manner of the first aspect, the gallium oxide substrate is an N-type highly doped gallium oxide substrate;
the gallium oxide epitaxial wafer is an N-type low-doped gallium oxide epitaxial wafer
In a second aspect, embodiments of the present application provide a gallium oxide diode device comprising the gallium oxide diode device fabricated by the method of any one of claims 1 to 9.
It is understood that the beneficial effects of the second aspect can be referred to the related description of the first aspect, and are not described herein again.
Compared with the prior art, the embodiment of the application has the advantages that:
according to the embodiment of the application, the gallium oxide substrate is respectively rotated towards two opposite directions to etch the gallium oxide epitaxial layer, then the NiO layer is prepared, the NiO layer is used for replacing doped gallium oxide to form a P-type layer, the electrode layer is prepared at last, the gallium oxide positive angle grinding terminal structure is easily realized, and the pressure resistance of a diode device is effectively improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the specification.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic flow chart of a method for manufacturing a gallium oxide diode device according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a dielectric mask layer for preparing a predetermined pattern according to an embodiment of the present application;
fig. 3 is a schematic structural diagram after etching a gallium oxide epitaxial layer according to an embodiment of the present application;
FIG. 4 is a schematic structural diagram of an embodiment of the present disclosure for preparing a polyimide layer with a predetermined shape;
fig. 5 is a schematic structural diagram of forming a NiO layer according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of forming a first electrode layer according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of forming a second electrode layer according to an embodiment of the present disclosure.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The angle grinding terminal is one of important terminal technologies for improving the performance of a power diode device, and the conventional preparation method is to prepare a P-type layer by injection or epitaxy and then realize the angle grinding terminal by a small-angle inclination angle etching technology. However, gallium oxide lacks a P-type doping technology, and cannot realize corner grinding by using an etching technology after a P-type layer is prepared, so that a new preparation technology needs to be developed urgently.
Based on the above problems, in the method for manufacturing a gallium oxide diode device in the embodiment of the present application, a dielectric mask layer with a preset pattern is prepared on a gallium oxide epitaxial layer; rotating the gallium oxide substrate by a first inclination angle and a second inclination angle in two opposite directions respectively by taking a horizontal plane as a reference, and etching the gallium oxide epitaxial layer covered by the dielectric mask layer, wherein the first inclination angle and the second inclination angle are both smaller than 90 degrees; preparing a polyimide layer with a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer; removing the medium mask layer, and forming a NiO layer on the upper surface of the area, corresponding to the medium mask layer, on the gallium oxide epitaxial layer and the polyimide layer, and the area, close to the medium mask layer, on the polyimide layer; forming a first electrode layer on the NiO layer; and forming a second electrode layer on the lower surface of the gallium oxide substrate.
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic flow chart of a navigation method provided in an embodiment of the present application, and referring to fig. 1, details of a method for manufacturing the gallium oxide diode device are as follows:
in step 101, preparing a dielectric mask layer 3 with a preset pattern on a gallium oxide epitaxial layer 2, wherein part of the gallium oxide epitaxial layer 2 is not covered by the dielectric mask layer 3; the gallium oxide epitaxial layer 2 is formed on the upper surface of the gallium oxide substrate 1.
In a possible implementation manner, in step 101, preparing a dielectric mask layer 3 with a preset pattern on the gallium oxide epitaxial layer 2 includes:
step a1, preparing a dielectric mask layer 3 on the gallium oxide epitaxial layer 2, as shown in (a) of fig. 2;
after the gallium oxide epitaxial layer 2 is cleaned, a dielectric mask layer 3 is prepared on the gallium oxide epitaxial layer 2;
an exemplary rinse may be sequentially with acetone, isopropanol, and deionized water.
Illustratively, the dielectric mask layer 3 is SiO2Or SiN, the growth mode is a PECVD growth mode, and the growth temperature is 300 ℃.
Step a2, preparing a first photoresist layer 4 on the dielectric mask layer 3, as shown in (b) of fig. 2;
wherein, a photoresist is spin-coated on the dielectric mask layer 3 to form a first photoresist layer 4.
Step a3, etching the first photoresist layer 4 to expose part of the dielectric mask layer 3, as shown in (c) of fig. 2;
and etching the first photoresist layer 4, including photoetching, exposing and developing the first photoresist layer 4 to expose part of the dielectric mask layer 3.
Step a4, preparing a metal mask layer 5 on the first photoresist layer 4 and the dielectric mask layer 3, as shown in (d) of fig. 2;
illustratively, the metal mask layer 5 is prepared by electron beam evaporation or sputtering.
Step a5, the metal mask layer 5 on the first photoresist layer 4 is stripped, and the first photoresist layer 4 is removed, as shown in (e) of fig. 2.
Illustratively, the etching gas may be Ar and BCl3, and the power may be 100W.
Step a6, etching the exposed portion of the dielectric mask layer 3 to form a dielectric mask layer 3 with a predetermined pattern, as shown in (f) of fig. 2.
In step 102, referring to fig. 3, the gallium oxide substrate is rotated by a first inclination angle θ and a second inclination angle α in two opposite directions respectively on the basis of a horizontal plane, and the gallium oxide epitaxial layer 2 covered by the dielectric mask layer 3 is etched, where both the first inclination angle θ and the second inclination angle α are smaller than 90 °.
In some embodiments, the first inclination angle θ and the second inclination angle α may range from: 30 to 60.
Wherein the first inclination angle theta is equal to the second inclination angle alpha.
Illustratively, rotating the gallium oxide substrate 1 by a first inclination angle theta, and etching the gallium oxide epitaxial layer 2 by ICP etching along the etching direction A; rotating the gallium oxide substrate 1 by a second inclination angle alpha, and etching the gallium oxide epitaxial layer 2 along the etching direction B by ICP etching; etching gas is SF6 or Ar or BCl3Or other etching gases; the first inclination angle theta is more than 90 degrees and more than 0 degree, and the preferred range is more than or equal to 60 degrees and more than or equal to 30 degrees; the second inclination angle alpha is more than 90 degrees and more than 0 degree, the preferred range is more than or equal to 60 degrees and more than or equal to 30 degrees, alpha and theta can be equal or unequal, and the equal effect is better.
After the gallium oxide epitaxial layer 2 is etched, the metal mask layer 3 is removed, and the gallium oxide epitaxial layer 2 is cleaned.
Illustratively, the gallium oxide epitaxial layer 2 may be washed with acetone, isopropyl alcohol, and deionized water.
In step 103, a polyimide layer 6 with a preset shape is prepared on the gallium oxide epitaxial layer 2 and the dielectric mask layer 3, and part of the dielectric mask layer 3 is not covered by the polyimide layer 6.
Before the polyimide layer 6 with a preset shape is prepared, the metal mask layer 5 on the medium mask layer 3 is removed.
In one possible implementation, referring to fig. 4, in step 103, a polyimide layer 6 with a preset shape is prepared on the gallium oxide epitaxial layer 2 and the dielectric mask layer 3, and the method includes: polyimide is coated on the surfaces of the gallium oxide epitaxial wafer 2 and the dielectric mask layer 3 in a spinning mode; etching the polyimide to expose the dielectric mask layer 3; the polyimide is cured at a high temperature to form a polyimide layer 6 of a predetermined shape.
Wherein etching the polyimide comprises: the polyimide is subjected to photolithography, exposure, and development to expose the dielectric mask layer 3.
For example, the polyimide may be cured at a high temperature of 300 ℃ in a nitrogen atmosphere for half an hour.
In step 104, the dielectric mask layer 3 is removed, and a NiO layer 8 is formed on the gallium oxide epitaxial layer 2 in the region corresponding to the dielectric mask layer 3 and on the upper surface of the polyimide layer 6 near the region corresponding to the dielectric mask layer 3.
Illustratively, step 104 may include:
step B1, removing the dielectric mask layer 3, as shown in (a) of fig. 5;
wherein, the mode of removing the medium mask layer 3 is wet etching.
Illustratively, the wet etch may be HF acid ultrasonic removal for 5 minutes.
Step B2, a second photoresist layer 7 is formed at the edge of the upper surface of the polyimide layer 6 so that a part of the upper surface of the polyimide layer 6 is exposed, as shown in (B) of fig. 5.
Step B3, preparing NiO layer 8 on the exposed upper surface of polyimide layer 6 and gallium oxide epitaxial layer 2, as shown in (c) of fig. 5;
wherein, a self-aligned filling method can be used to form the NiO layer 8, and the second photoresist layer 7 is removed;
the thickness of the NiO layer 8 and the thickness of the removed area of the dielectric mask layer 3 may be equal or different.
For example, when NiO is filled in a self-aligned manner, the target purity may be 99.99%, and the sputtering power may be 150W.
In step 105, referring to fig. 6, a first electrode layer 9 is formed on NiO layer 8.
Wherein, the first electrode layer 9 is an anode layer; and (3) coating photoresist on the whole upper surface in a spinning mode, photoetching, exposing and developing to obtain an anode metal pattern area, evaporating anode metal by using an electron beam, stripping redundant metal, and cleaning to form an anode layer.
For example, the material of the first electrode layer 9 may be Ni or Au. When the material of the first electrode layer 9 is Ni, the thickness of the first electrode layer 9 may be 50 nm; when the material of the first electrode layer 9 is Au, the thickness of the first electrode layer 9 may be 400 nm.
In step 106, referring to fig. 7, a second electrode layer 10 is formed on the lower surface of the gallium oxide substrate 1.
Wherein the second electrode layer 10 is a cathode layer; the electron beam evaporates the anode metal to form a cathode layer.
For example, the material of the second electrode layer 10 may be Ti or Au. When the material of the second electrode layer 10 is Ti, the thickness of the second electrode layer 10 may be 20 nm; when the material of the second electrode layer 10 is Au, the thickness of the second electrode layer 10 may be 400 nm.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method for fabricating a gallium oxide diode device, comprising:
preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer, wherein part of the gallium oxide epitaxial layer is not covered by the dielectric mask layer; the gallium oxide epitaxial layer is formed on the upper surface of the gallium oxide substrate;
rotating the gallium oxide substrate by a first inclination angle and a second inclination angle in two opposite directions respectively by taking a horizontal plane as a reference, and etching the gallium oxide epitaxial layer covered by the dielectric mask layer, wherein the first inclination angle and the second inclination angle are both smaller than 90 degrees;
preparing a polyimide layer in a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer, wherein part of the dielectric mask layer is not covered by the polyimide layer;
removing the medium mask layer, and forming a NiO layer on the area corresponding to the medium mask layer on the gallium oxide epitaxial layer and on the upper surface of the area close to the medium mask layer on the polyimide layer;
forming a first electrode layer on the NiO layer;
and forming a second electrode layer on the lower surface of the gallium oxide substrate.
2. The method of manufacturing a gallium oxide diode device according to claim 1, wherein the step of manufacturing a dielectric mask layer with a predetermined pattern on the gallium oxide epitaxial layer comprises:
preparing a dielectric mask layer on the gallium oxide epitaxial layer;
preparing a first photoresist layer on the medium mask layer;
etching the first photoresist layer to expose part of the dielectric mask layer;
preparing a metal mask layer on the first photoresist layer and the dielectric mask layer;
stripping part of the metal mask layer on the first photoresist layer, and removing the first photoresist layer to form a metal mask layer with a preset pattern;
and etching the exposed part of the dielectric mask layer to form the dielectric mask layer with the preset pattern.
3. The method of manufacturing a gallium oxide diode device according to claim 1, wherein the first tilt angle and the second tilt angle range are both: 30 to 60.
4. The method according to claim 1 or 3, wherein the first inclination angle is equal to the second inclination angle.
5. The method of fabricating a gallium oxide diode device according to claim 1, wherein the fabricating a polyimide layer of a predetermined shape on the gallium oxide epitaxial layer and the dielectric mask layer comprises:
and before the polyimide layer with the preset shape is prepared, removing the metal mask layer with the preset pattern on the medium mask layer.
6. The method of fabricating a gallium oxide diode device according to claim 1, wherein fabricating a polyimide layer of a predetermined shape on the gallium oxide epitaxial layer and the dielectric mask layer comprises:
spin-coating polyimide on the surfaces of the gallium oxide epitaxial wafer and the dielectric mask layer;
etching the polyimide to expose the dielectric mask layer;
and curing the polyimide at a high temperature to form a polyimide layer with a preset shape.
7. The method of fabricating a gallium oxide diode device according to claim 1, wherein the forming a NiO layer on the gallium oxide epitaxial layer in a region corresponding to the dielectric mask layer and at an edge of an upper surface of the polyimide layer comprises:
forming a second photoresist layer at the edge of the upper surface of the polyimide layer, so that part of the upper surface of the polyimide layer is exposed;
preparing the NiO layer on the exposed upper surface of the polyimide layer and the gallium oxide epitaxial layer;
and removing the second photoresist layer.
8. The method of fabricating a gallium oxide diode device according to claim 5, wherein the NiO layer is filled using a self-aligned approach.
9. The method of manufacturing a gallium oxide diode device according to claim 1,
the gallium oxide substrate is an N-type highly doped gallium oxide substrate;
the gallium oxide epitaxial wafer is an N-type low-doped gallium oxide epitaxial wafer.
10. A gallium oxide diode device, wherein the gallium oxide diode device is prepared by the method of any one of claims 1 to 9.
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