CN114741248A - A spaceborne computer detection system - Google Patents

Abstract

The application provides a detection system of a spaceborne computer, which comprises the spaceborne computer and a single board test board card, wherein the single board test board card comprises a plurality of first data interfaces and a core controller; the core controller is used for simulating various environment state signals of the satellite borne computer in a working mode, sending the corresponding environment state signals to the satellite borne computer through the first data interface, and determining whether the satellite borne computer is abnormal or not based on received data feedback signals sent by the satellite borne computer; and the satellite-borne computer is used for processing the environmental state signal to obtain a data feedback signal. The on-board computer test system can simulate the whole on-board computer to test each application function of the on-board computer under different working states through the single-board test board card, improves the test efficiency, reduces the test cost, and quickens the progress of checking out wrong designs and abnormal states in the design process of the on-board computer.

Description

A spaceborne computer detection system

technical field

The present application relates to the technical field of space vehicles, and in particular, to an on-board computer detection system.

Background technique

The onboard computer usually refers to the core control system of the on-board electronic system of the satellite and other space vehicles. The tasks such as operation guarantee, task planning, and data scheduling during the satellite's in-orbit work are all completed by the onboard computer. Due to the variety of tasks and high data complexity of satellite electronic systems, onboard computers usually have complex data interfaces with multiple speed requirements and multiple signal types. In addition, the same data interface may include a variety of different data protocol conventions.

For the traditional testing method of the onboard computer, different external tools are usually used for testing according to the requirements of different interfaces and data conventions on the onboard computer. This testing method consumes more resources and equipment costs and has higher test efficiency. With the development of the current digital circuit, the integration of the circuit in the onboard computer has become higher and the area of the main board has been reduced, resulting in an increase in the density of the interface line of the onboard computer, and the difficulty of testing a single interface has also increased. When the onboard computer completes and processes onboard tasks, there will be various interface data linkages, so that the method of using traditional external tools to detect the connection of a single interface cannot completely simulate the work of the entire onboard computer. state.

SUMMARY OF THE INVENTION

In view of this, the purpose of this application is to provide an on-board computer detection system, which can simulate the entire on-board computer under different working states, and can test each application function of the on-board computer through a single-board test board. , while improving the test efficiency and reducing the test cost, it also speeds up the progress of checking out erroneous designs and abnormal states in the design process of the on-board computer.

An embodiment of the present application provides an on-board computer detection system, the on-board computer detection system includes an on-board computer and a single-board test board, and the single-board test board includes a plurality of first data interfaces and a core controller , the first data interface is connected to the second data interface of the onboard computer in a stack-type plug-and-socket manner; wherein,

The core controller is used to simulate various environmental status signals of the onboard computer in the working mode, and send the corresponding environmental status signals to the onboard computer through the first data interface, and Determine whether the application function of the onboard computer is abnormal based on the received data feedback signal sent by the onboard computer;

The onboard computer is configured to process the environmental state signal to obtain the data feedback signal, and send the data feedback signal to the core controller through the second data interface.

Further, the first data interface includes at least one of the following interfaces:

The first RS422 interface, the first CAN bus interface, the first AD interface, the DA interface, and the USB interface.

Further, the second data interface includes a second AD interface, the environmental state signal includes a temperature analog signal; the application function includes a temperature control function, wherein,

The core controller is configured to use the second AD interface to send the temperature analog signal to the onboard computer, and determine the temperature of the onboard computer based on the received temperature feedback signal sent by the onboard computer. Whether the temperature control function is abnormal;

The onboard computer is used for processing the temperature analog signal to obtain the temperature feedback signal.

Further, the core controller is configured to use the second AD interface to send the temperature simulation signal to the onboard computer, including:

The core controller is configured to send the temperature analog signal to the second AD interface of the onboard computer through the DA interface, and use the second AD interface to send the temperature analog signal to the onboard computer.

Further, the second data interface further includes a second CAN bus interface and a second RS422 interface, and the environmental status signal further includes a CAN bus analog signal; wherein,

The core controller is configured to use the second CAN bus interface to send the CAN bus analog signal to the onboard computer, and determine the satellite based on the received packaged feedback signal sent by the onboard computer. Whether the second CAN bus interface and the second RS422 interface of the onboard computer are abnormal;

The onboard computer is used to process the CAN bus analog signal to obtain a packaged feedback signal, and send the packaged feedback signal to the core controller through a serial port data interface.

Further, the core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the onboard computer are abnormal according to the following steps:

Subcontract and analyze the received packaged feedback signal sent by the onboard computer to generate an analysis feedback signal;

According to the label information of the analysis feedback signal and the label information of the CAN bus analog signal, determine whether the analysis feedback signal is consistent with the CAN bus analog signal;

If so, it is determined that both the second CAN bus interface and the second RS422 interface are normal.

Further, the environmental status signal further includes a voltage analog signal, and the application function includes a voltage detection function; wherein,

The core controller is configured to use the second AD interface to send the voltage analog signal to the onboard computer, and determine the voltage feedback signal of the onboard computer based on the received voltage feedback signal sent by the onboard computer. Whether the voltage detection function is abnormal;

The onboard computer is used for processing the voltage analog signal to obtain the voltage feedback signal.

Further, the voltage feedback signal is a voltage signal including a flag bit fed back by the onboard computer through the second CAN bus interface; the core controller is used to determine whether the voltage detection function is abnormal according to the following steps:

Whether the voltage detection function of the onboard computer is abnormal is determined according to the digital information and position information of the marker bit.

Further, the single-board test board also includes a resistance voltage divider circuit, the resistance voltage divider circuit is connected to the first AD interface, and the resistance voltage divider circuit is used to simulate the onboard computer in the working mode. Corresponding voltage analog signals of different voltage values.

Further, the USB interface is connected with an external terminal device; wherein,

The USB interface is used to send the data feedback signal to an external terminal device;

The external terminal device is configured to draw a detection waveform diagram based on the received data feedback signal sent by the USB interface.

Compared with the prior art, the on-board computer detection system provided by the embodiments of the present application can simulate the entire on-board computer under different working states, and can realize the detection of the on-board computer through a single-board test board. Testing each application function not only improves the test efficiency and reduces the test cost, but also speeds up the process of checking out the wrong design and abnormal state in the design process of the on-board computer.

In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following drawings will briefly introduce the drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

1 shows a structural block diagram of a detection system for on-board computing provided by an embodiment of the present application;

2 shows a structural block diagram of a USB interface design in a detection system for on-board computing provided by an embodiment of the present application;

3 shows a structural block diagram of a resistance voltage divider circuit in a detection system for on-board calculation provided by an embodiment of the present application;

FIG. 4 shows a structural block diagram of a single-board testing board in a detection system for on-board computing provided by an embodiment of the present application.

In the picture:

10- on-board computer detection system; 100- single-board test board; 110- core controller; 111- programmable control chip; 1111- microcontroller; 1112- logic resource processing sub-chip; 112- level matching chip; 120-first data interface; 130-resistor voltage divider circuit; R1-first resistance; R2-second resistance; U-power supply; 200-onboard computer; 210-second data interface.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only It is a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Thus, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, every other embodiment obtained by those skilled in the art without creative work falls within the protection scope of the present application.

First of all, after research, it is found that the traditional testing methods for on-board computers in the prior art usually use different external tools for testing according to the requirements of different interfaces and data conventions on the on-board computers. The cost of many resources and equipment is low and the test efficiency is low. With the current development of digital circuits, the integration of the circuit in the onboard computer has become higher and the area of the main board has been reduced, resulting in an increase in the density of the interface line of the onboard computer, resulting in a single interface. The difficulty of testing has also increased, and in the process of completing and processing on-board tasks, the onboard computer will have various interface data linkages, which makes it possible to use traditional external tools to detect the connection of a single interface. The working state of the entire onboard computer cannot be completely simulated.

Based on this, the embodiments of the present application provide an on-board computer detection system, which can simulate the entire on-board computer under different working states, and can test various application functions of the on-board computer through a single-board test board. While improving the test efficiency and reducing the test cost, it also speeds up the progress of troubleshooting the wrong design and abnormal state in the design process of the on-board computer.

Please refer to FIG. 1. FIG. 1 is a structural block diagram of an on-board computer detection system provided by an embodiment of the present application. Therefore, as shown in FIG. 1 , the onboard computer detection system 10 provided by the embodiment of the present application includes an onboard computer 200 and a single-board test board 100 , and the single-board test board 100 includes a plurality of first data interfaces 120 and In the core controller 110 , the first data interface 120 is connected to the second data interface 210 of the onboard computer 200 in a stacking manner.

In the above-mentioned specific embodiment, the on-board computer 200 in the on-board computer detection system 10 is the core control system on the spacecraft, and the single-board test board 100 included in the on-board computer detection system 10 is capable of detecting the on-board computer. The configuration data of each interface in 200 and the function data of each interface, as well as the processing configuration data of the onboard computer 200 when performing different flight tasks can be detected, and the single-board test board 100 itself has independent operation and programmable conditions. Compared with the onboard computer 200 , the single-board testing board 100 is equivalent to a lower-level computer inspection device actively controlled by on-board computing, and the specific connection method is: the on-board computer communicates with the single-board testing board 100 through the second data interface 210 The first data interface 120 is connected in a stacked manner, which is convenient for data interaction between the onboard computer and the single-board test board 100 .

In the above, the single-board test board 100 performs the corresponding data flow design according to the actual use scenario, and sends various environmental status signals simulating the onboard computer 200 in the working mode to the onboard through the various types of first data interfaces 120. The computer 200 is used to simulate the data interaction process between the real application subsystem and the onboard computer 200 during the satellite operation, and judge the onboard computer 200 according to the state performance of the onboard computer 200 and the task processing results during the above simulation process. Whether the configuration data of the computer 200 and the function data of the second interface are abnormal.

Here, the size of the single-board test board 100 is designed for stacking according to the actual size of the onboard computer 200. Therefore, the single-board test board 100 can simulate the actual installation conditions of the onboard computer 200, and can be compatible with the onboard computer 200. The on-board computer 200 carries out various related environmental tests together to facilitate acceptance testing.

Wherein, the onboard computer 200 is used to ensure the operation status, task planning and data scheduling of the spacecraft during the on-orbit operation, and the second data interface 210 in the onboard computer 200 at least includes a second RS422 interface, a second CAN bus interface and the second AD interface, etc., and the task working mode of the onboard computer 200 includes a variety of situations in which the second data interface 210 is linked.

Here, a specific embodiment is given to illustrate the task working modes of the linkage of various second data interfaces 210, as follows:

For example, after the second CAN bus interface packages the received task data and receives a data sending instruction, the packaged task data needs to be transmitted in a specific format from the second RS422 interface, and according to the second RS422 interface The analysis of the received data by the interface protocol of the interface protocol, in this way, the logical value of some OC ports will be changed, that is, the second RS422 interface in the embodiment provided by this application. Here, the OC port is an output comparison port. is the output. It can be set to count output high level or output low level, which is mainly used for output pulse.

The core controller is used to simulate various environmental status signals of the onboard computer 200 in the working mode, and send the corresponding environmental status signals to the satellite through the first data interface 120 The on-board computer 200 is used, and based on the received data feedback signal sent by the on-board computer 200, it is determined whether the application function of the on-board computer 200 is abnormal.

In the above specific implementation manner, the core controller 110 in the single-board test board 100 is implemented by using an FPGA SoC chip, the core controller has both FPGA logic resources and the processing resources of the microcontroller 1111, and the single-board test board 100 passes the The internal microcontroller 1111 handles resource design and simulates various environmental state signals of external application stand-alone devices in the working mode of the onboard computer 200, and designs functional algorithms corresponding to relevant environmental state signals, and will characterize various types of functional data. The various environmental status signals are sent by the microcontroller 1111 to the logic resource processing sub-chip 1112 inside the single-board test board 100, and the various environmental status signals are sent by the logic resource processing sub-chip 1112 via the first data interface 120 To the onboard computer 200.

The FPGA SoC chip can meet the logic implementation and data operation of many functions of the first data interface 120, and the parallel timing design capability of the FPGA can coordinate the data communication function and data flow of each first data interface 120, and the micro-controller in the core controller. The controller 1111 can operate on the data according to the algorithm, so that the on-board computer detection system 10 in the present application is more adaptable under the blessing of the core controller 110, and realizes a more specific control of each of the on-board computer 200 in the working mode. The simulation of an environmental state signal, wherein the microcontroller 1111 in the embodiment provided by the present application can select an ARM hard-core controller.

In the above, the core controller is also used to receive the data feedback signal sent by the onboard computer 200, and judge whether various application functions of the onboard computer 200 appear according to the data feedback signal and the function algorithm edited by the microcontroller 1111 inside the core controller. abnormal.

Preferably, the first data interface 120 includes at least one of the following interfaces: a first RS422 interface, a first CAN bus interface, a first AD interface, a DA interface, and a USB interface.

Here, the second data interface 210 of the onboard computer 200 includes a second RS422 interface, a second CAN bus interface and a second AD interface, and the first RS422 interface in the first data interface 120 of the single-board test board 100 is connected to the onboard The second RS422 interface in the second data interface 210 of the computer 200 is connected in a stack-type plug-and-socket manner, and the first CAN bus interface in the first data interface 120 of the single-board test board 100 is connected with the second data interface 210 of the onboard computer 200 The second CAN bus interface in the stack is connected by a stack, and the DA interface and the first AD interface in the first data interface 120 of the single-board test board 100 are both connected with the second data interface 210 of the onboard computer 200. The AD interface is connected by stacking plug-in, and the USB interface in the first data interface 120 of the single-board test board 100 is connected with the external terminal device, wherein the USB interface is used for sending the data feedback signal to the external terminal device; The external terminal device is configured to draw a detection waveform diagram based on the received data feedback signal sent by the USB interface.

In the above, in the process of designing the single-board test board 100, due to the consideration of the user's portability and the actual use of the equipment in the satellite (such as a spacecraft, etc.), the single-board test board 100 and the satellite are considered. The components of the on-board computer 200 adopt a stacking plug-in connection, and the stacking plug-in connection is also an installation method for electronic products in satellites.

Here, the connection nodes of part of the first data interface 120 of the single-board test board 100 are connected through the on-board plug-in contact, and the single-board installation method can fully contact the nodes used on the satellite, so as to achieve in addition to the above-mentioned In addition to functional coverage testing, comprehensive testing is also performed on physical interfaces and electrical standards.

Among them, the hardware design of the USB interface is realized by using the USB 2.0 communication protocol driver chip to realize the communication protocol. The embodiment provided in this application selects the FTDI FT232H controller chip as the communication protocol driver chip, and realizes the USB 2.0 high-speed data communication through the FTDIFT232H controller chip. , the controller supports up to 480Mbps.

As shown in FIG. 2 , FIG. 2 is a structural block diagram of a USB interface design in a detection system for on-board computing provided by an embodiment of the application. In FIG. 2 , the FT232H controller chip is provided with a 12MHz crystal oscillator to provide the chip running clock, and the communication The protocol used is determined by the external direct-connected electrified programmable read-only memory (EEPROM) pre-programmed. The data interface of USB 2.0 is drawn from the DP and DM pins of the FT232H controller chip, and these two signals are connected to the communication connector. You can complete the external connection to the USB 2.0 interface.

In this way, when using FT232H to drive USB 2.0, it is necessary to configure FT232H as a synchronous FIFO interface in FT245 mode, and convert USB 2.0 serial data into 8-bit bit-width encoded data. When using this mode, the main signals are shown in Table 1:

Table 1 FT232H and star sensor main control chip connection signal table

Here, the drive design for the read operation of the FT232H chip in Table 1 is as follows:

When the chip outputs RXF# to a low level, the read operation can be performed. Before the RD# signal becomes a low level, the FPGA SoC system can set the OE# to a low level, so that the signal direction of the data bus driver is output. The FPGA SoC side can read data; after OE# is low level, the first data byte begins to appear on the data, once all data is read, the chip will drive RXF# to high level, RXF# is After high, all data appearing on the data bus is invalid and should be ignored.

The FT232H chip write operation driver design is as follows:

When TXE# is low, the write operation can be started. When the write data operation is valid, WR# changes from high level to low level. As long as TXE# is always low, the write operation can be performed continuously on each clock. The FPGA SoC resource chip driver must monitor the TXE# and WR# signals to check whether the receiver has received data. When both are not low, the data cannot be received by the data bus, and all data appearing on the data bus is invalid. .

Here, the above-mentioned USB 2.0 drive signal is controlled by the core controller in the single-board test board 100, and the data signal is collected and read. After the design external terminal device receives the data feedback signal, after auxiliary analysis, the external terminal device is designed for The data feedback signal is used for auxiliary analysis, dynamic analysis data is given, and waveform diagrams are drawn, which is convenient for testers to view more intuitively.

The onboard computer 200 is configured to process the environmental state signal to obtain the data feedback signal, and send the data feedback signal to the core controller through the second data interface 210 .

In the above specific embodiment, the onboard computer 200 is used to process the environmental state signal simulated by the single-board test board, wherein the processing methods include but are not limited to judgment processing, calculation processing, packaging processing and design processing. After processing, The obtained data feedback signal is sent to the core controller through the second data interface 210 .

Preferably, the second data interface 210 includes a second AD interface, the environmental state signal includes a temperature analog signal; the application function includes a temperature control function, wherein the core controller is used to utilize the second AD interface. The AD interface sends the temperature simulation signal to the onboard computer 200 , and determines whether the temperature control function of the onboard computer 200 is abnormal based on the received temperature feedback signal sent by the onboard computer 200 .

The onboard computer 200 is configured to process the temperature analog signal to obtain the temperature feedback signal.

In the above, when the temperature control function of the onboard computer 200 needs to be detected in the embodiments provided by this application, at this time, the onboard computer detection system 10 needs to simulate an external temperature control application subsystem. The controller 1111 simulates the first temperature digital signal, and converts the first temperature digital signal into a first analog signal through the DA conversion controller in the logic resource processing sub-chip 1112, and converts the first temperature digital signal into a first analog signal. The first analog signal is sent to the second AD interface of the onboard computer 200 through the DA interface, and the onboard computer 200 converts the first analog signal into a first digital signal via AD, and the first analog signal is converted into first data via AD signal, at this time, the onboard computer 200 determines whether the first data signal is higher than the preset low temperature threshold, and if it is greater than the preset low temperature threshold, the onboard computer 200 starts heating, and outputs the heated temperature feedback signal through the second AD interface To the microcontroller 1111 in the detection system, the microcontroller 1111 simulates the second temperature digital signal (the second temperature digital signal is greater than the preset low temperature threshold of the onboard computer 200 and less than the preset high temperature threshold of the onboard computer 200 ) ), and send the second temperature digital signal to the onboard computer 200. If the onboard computer 200 continues to output a temperature feedback signal for continuous heating to the detection system after processing, it means that the temperature control function of the onboard computer 200 is running to Wu is abnormal at this time, and then the microcontroller 1111 of the core controller simulates the third temperature digital signal, and passes the third temperature digital signal through the DA conversion controller in the logic resource processing sub-chip 1112 to convert the third temperature digital signal Convert the third analog signal into a third analog signal, and send the third analog signal to the second AD interface of the onboard computer 200 through the DA interface, and the onboard computer 200 converts the third analog signal into a third digital signal via AD (the third analog signal). The digital signal is higher than the preset high temperature threshold), the third analog signal is converted into a third data signal through AD, and at this time, if the onboard computer 200 determines whether the third data signal is higher than the preset low temperature threshold, and outputs stop heating The temperature feedback signal is sent to the detection system, and the detection system determines that the temperature control function of the onboard computer 200 is normal according to the temperature feedback signal.

Here, the detection system performs time sequence analysis on the level of the temperature feedback signal and the PWM waveform. If the analysis result is different from the working state result represented by the temperature feedback signal sent by the onboard computer 200 to the detection system, the temperature control function of the onboard computer 200 is determined. An exception occurs.

The temperature control function of the onboard computer 200 is specifically: after the onboard computer 200 receives a temperature analog signal that is lower than the preset low temperature threshold, the temperature analog signal is heated, and the working mode of the onboard computer 200 is determined as: Heating state; if the temperature analog signal is higher than the preset high temperature threshold, the onboard computer 200 determines to stop heating the temperature analog signal, and determines that the working mode of the onboard computer 200 is the heating stop state.

Preferably, the second data interface 210 further includes a second CAN bus interface and a second RS422 interface, and the environmental status signal further includes a CAN bus analog signal; wherein,

The core controller is configured to use the second CAN bus interface to send the CAN bus analog signal to the onboard computer 200, and based on the received packaged feedback signal sent by the onboard computer 200, determine the Whether the second CAN bus interface and the second RS422 interface of the onboard computer 200 are abnormal; the onboard computer 200 is used to process the CAN bus analog signal, obtain a packaged feedback signal, and The packaging feedback signal is sent to the core controller through the serial port data interface.

In the above, when the second CAN bus interface and the second RS422 interface of the onboard computer 200 need to be detected in the embodiment provided by this application, the simplest situation is:

First, connect the first CAN bus interface of the first data interface 120 in the detection system with the first CAN bus interface of the second data interface 210 in the onboard computer 200, and connect the first RS422 interface of the first data interface 120 in the detection system with the first CAN bus interface of the second data interface 210 in the onboard computer 200. The second RS422 interface of the second data interface 210 in the onboard computer 200 is connected. If the second CAN bus interface or the second RS422 interface of the onboard computer 200 can successfully send the corresponding data feedback signal, it means that the second RS422 interface of the onboard computer 200 can successfully transmit the corresponding data feedback signal. There is no abnormality in the functional design of the second CAN bus interface or the second RS422 interface.

Here, in the process of the onboard computer 200 performing task processing, in addition to the basic data transmission and forwarding functions, the above-mentioned second CAN bus interface and the second RS422 interface also have interface linkage. For example, through the second CAN bus The received telemetry and remote control environment status signal is sent to a single ground device, and the second CAN bus and the second RS422 interface need to be connected in series for linkage detection. The following example illustrates:

For example, after the single-board test board 100 needs to send the simulated temperature measurement signals of 100 simulated thermal controllers to the on-board computer 200 through the second AD interface on the on-board computer 200, the on-board computer 200 performs some series of After processing and the calculation and judgment of the complex onboard computer 200, the processed data feedback signal will be sent to the data transmission system, and the signal channel between the onboard computer 200 and the data transmission system is strictly one-to-one. Therefore, At this time, the single-board test board 100 needs to simulate the data transmission system, and receive the corresponding type of data feedback signal one-to-one through the first RS422 interface on the single-board test board 100, and send it to the ground receiving station after receiving, In this way, the detection of linkage of the first data interface 120 in the onboard computer 200 is realized.

Preferably, the core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the onboard computer 200 are abnormal according to the following steps:

Perform packetization and analysis processing on the received packetized feedback signal sent by the onboard computer 200 to generate an analysis feedback signal.

In the above, the onboard computer 200 will package the received CAN bus analog signal, and send the packaged data feedback signal to the single-board test board 100, and the single-board test board 100 will then package the processed data. The data feedback signal is sub-packaged and analyzed to generate the analysis feedback signal, and analyze the specific content of the back of the analysis feedback signal.

According to the label information of the analysis feedback signal and the label information of the CAN bus analog signal, it is determined whether the analysis feedback signal and the CAN bus analog signal are consistent.

If so, it is determined that both the second CAN bus interface and the second RS422 interface are normal.

In the above, if the single-board test board 100 determines that the content of the analytical feedback signal is consistent with the content of the CAN bus analog signal after labeling the CAN bus analog signal and the analytical feedback signal, then determine that the second CAN bus interface and the analytical feedback signal are consistent. The second RS422 interface is normal.

Here, if the single-board test board 100 determines that the content of the analytical feedback signal is inconsistent with the content of the CAN bus analog signal after labeling the CAN bus analog signal and the analytical feedback signal, it is determined that the second CAN bus interface and the first CAN bus interface There is an abnormality in the second RS422 interface. At this time, according to the actual situation, the second CAN bus interface or the second RS422 interface should be reset, designed and tested.

Preferably, the environmental status signal further includes a voltage analog signal, and the application function includes a voltage detection function; wherein the core controller is configured to send the onboard computer 200 by using the second AD interface. voltage simulation signal, and determine whether the voltage detection function of the onboard computer 200 is abnormal based on the received voltage feedback signal sent by the onboard computer 200; the onboard computer 200 is used for simulating the voltage The signal is processed to obtain the voltage feedback signal.

In the above, the function of the onboard computer 200 to detect whether the power supply is abnormal is specifically:

The second AD interface of the onboard computer 200 usually collects the V reference voltage value, that is, when the second AD interface performs analog signal quantization and transmission, the full scale is 5V. Therefore, in the hardware design of the onboard computer 200, the above-mentioned various power supplies are The voltage value of the power supply (the voltage value of the power supply is usually 28V, 12V and 5V, etc.), through the voltage division of the first resistor and the second resistor, the 3V voltage is obtained, and the 3V voltage is connected to the input terminal of the second AD interface . When the second AD interface of the onboard computer 200 receives the 3V voltage, it is considered that the corresponding high voltage value is also correct, because the high voltage value used in the actual power supply and the collected voltage value are divided by resistors. When the absolute value of the difference between the voltage value and the 3V voltage value exceeds the preset voltage value calculated by the on-board computer, it is considered that the on-board computer 200 detects that the power supply is abnormal.

When the single-board test board 100 in the embodiment provided by this application needs to detect the stand-alone power supply function of the onboard computer 200, here, the single-board test board 100 first outputs the corresponding voltage of the 3V voltage analog signal through the DA interface according to the chip The analog signal is sent to the DA interface. At this time, the second AD interface of the onboard computer 200 obtains the quantized value of the analog signal. The onboard computer 200 will give whether the voltage conforms to the normal working state according to the threshold deviation judgment method, and send the voltage feedback signal through the second CAN bus interface. The single-board test board 100 determines that the voltage detection function of the onboard computer 200 is normal; and when the single-board test board 100 outputs a voltage analog signal with a large deviation of 3V, the onboard computer 200 The quantized voltage value corresponding to the voltage analog signal is also given according to the threshold deviation judgment method. If the voltage feedback signal is a preset mark symbol representing normal power supply at this time, the single-board test board 100 determines the onboard computer 200 The voltage detection function is abnormal.

Preferably, the voltage feedback signal is a voltage signal including a flag bit fed back by the onboard computer 200 through the second CAN bus interface; the core controller is configured to determine whether the voltage detection function is abnormal according to the following steps:

Whether the voltage detection function of the onboard computer 200 is abnormal is determined according to the digital information and position information of the marker bit.

In the above, the marker bit is the representation bit of the working condition of the power supply in the table, and the marker bit can be customized. For example, according to the digital information and position information, the marker bit is set as the last bit of the voltage feedback signal, as Use "0" to indicate that the voltage detection function is abnormal, use "1" to indicate that the voltage detection function is abnormal, and use "0" to indicate that the voltage detection function is normal.

Preferably, the single-board test board 100 further includes a resistance voltage divider circuit 130, the resistance voltage divider circuit 130 is connected to the first AD interface, and the resistance voltage divider circuit 130 is used to simulate the onboard computer 200 voltage analog signals corresponding to different voltage values in the working mode, as shown in FIG. 3 , which is a structural block diagram of a resistance voltage divider circuit in a detection system for on-board calculation provided by an embodiment of the present application. The resistor divider circuit 130 includes a first resistor R1, a second resistor R2 and a U power supply. The positive terminal of the power supply U is connected in series with the first resistor R1 and the second resistor R2 and then grounded. The negative terminal of the power supply U is grounded, and the end connected with the first resistor R1 and the second resistor R2 is connected with the first AD interface.

Compared with the prior art, the on-board computer detection system 10 provided by the embodiment of the present application simulates various environmental state signals of the on-board computer 200 in the working mode by using a single-board test board to realize In order to be able to simulate the entire onboard computer 200 in different working states, the test of each interface of the onboard computer 200 avoids the need to use different external tools to test a single interface, which improves the test efficiency and reduces the test cost. At the same time, the progress of checking out erroneous designs and abnormal states during the design process of the onboard computer 200 is accelerated.

Please refer to FIG. 4 , which is a structural block diagram of a single-board testing board 100 in a detection system for on-board computing provided by another embodiment of the present application. As shown in FIG. 4 , the single-board test board 100 provided by this embodiment of the present application includes:

The onboard computer detection system 10 includes an onboard computer 200 and a single-board test board 100. The single-board test board 100 includes a plurality of first data interfaces 120 and a core controller. The second data interface 210 of the onboard computer is connected in a stacking manner, the core controller includes a programmable control chip 111 and a level matching chip 112, and the programmable control chip 111 includes a microcontroller 1111 and logic resources The chiplet 1112 is processed.

The level matching chip 112 is used for matching the corresponding first data interface 120 to obtain various environmental state signals simulating the onboard computer 200 in the working mode from the programmable control chip 111 .

The microcontroller 1111 adopts an ARM hard-core microcontroller 1111, wherein the logic resource processing sub-chip 1112 includes a CAN controller, a serial port controller, an LVDS interface controller, a DA conversion controller, an AD conversion controller and a USB interface timing sequence, while The corresponding level matching chip 112 includes a CAN bus transceiver, a RE422 level matching chip 112, a DA conversion chip, an AD conversion chip and a USB protocol chip.

Among them, RE422 level matching chip 112 adopts MAX3488ESA RS422 differential level protocol chip, which converts single-ended serial communication interface into RS422 interface, CAN bus transceiver adopts TJA1040T type chip, AD conversion chip adopts ADS8344 type chip, and DA conversion chip adopts DAC80508 model chip.

Compared with the prior art, the single-board test board 100 in the embodiment provided by the present application can simulate the entire on-board computer 200 by simulating various environmental state signals of the on-board computer 200 in the working mode. In different working states, for the test of each interface of the onboard computer 200, the process of using different external tools to test a single interface is avoided, the test efficiency is improved and the test cost is reduced, and the onboard computer 200 is accelerated. The progress of troubleshooting design errors and abnormal states during the design process.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, for the specific working process of the system described above, reference may be made to the corresponding process in the foregoing system embodiments, which will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed system may be implemented in other manners. The system embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple subsystems or modules may be combined. Either it can be integrated into another system, or some features can be omitted, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some communication interfaces, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The above are only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed in the present application can easily think of changes or replacements, which should be covered within the scope of the present application. within the scope of protection of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A detection system of a spaceborne computer is characterized by comprising the spaceborne computer and a single board test board, wherein the single board test board comprises a plurality of first data interfaces and a core controller, and the first data interfaces are connected with a second data interface of the spaceborne computer in a stacked and inserted mode; wherein,

the core controller is used for simulating various environment state signals of the satellite borne computer in a working mode, sending the corresponding environment state signals to the satellite borne computer through the first data interface, and determining whether the application function of the satellite borne computer is abnormal or not based on the received data feedback signals sent by the satellite borne computer;

and the satellite-borne computer is used for processing the environment state signal to obtain the data feedback signal and sending the data feedback signal to the core controller through the second data interface.

2. The on-board computer detection system of claim 1, wherein the first data interface comprises at least one of:

the device comprises a first RS422 interface, a first CAN bus interface, a first AD interface, a DA interface and a USB interface.

3. The on-board computer detection system of claim 1, wherein the second data interface comprises a second AD interface, the environmental status signal comprises a temperature analog signal; the application function comprises a temperature control function; wherein,

the core controller is used for sending the temperature simulation signal to the satellite borne computer by utilizing the second AD interface and determining whether the temperature control function of the satellite borne computer is abnormal or not based on the received temperature feedback signal sent by the satellite borne computer;

and the satellite-borne computer is used for processing the temperature analog signal to obtain the temperature feedback signal.

4. The on-board computer detection system of claim 3, wherein the core controller is configured to send the temperature analog signal to the on-board computer using the second AD interface, and comprises:

and the core controller is used for sending the temperature analog signal to a second AD interface of the satellite borne computer through the DA interface and sending the temperature analog signal to the satellite borne computer by utilizing the second AD interface.

5. The on-board computer detection system of claim 3, wherein the second data interface further comprises a second CAN bus interface and a second RS422 interface, and the environmental status signal further comprises a CAN bus analog signal; wherein,

the core controller is configured to send the CAN bus analog signal to the on-board computer by using the second CAN bus interface, and determine whether the second CAN bus interface and the second RS422 interface of the on-board computer are abnormal based on the received packed feedback signal sent by the on-board computer;

and the satellite-borne computer is used for processing the CAN bus analog signal to obtain a packaging feedback signal and sending the packaging feedback signal to the core controller through a serial port data interface.

6. The on-board computer detection system of claim 5, wherein the core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the on-board computer are abnormal according to the following steps:

subpackaging and analyzing the received packaged feedback signals sent by the satellite-borne computer to generate analysis feedback signals;

judging whether the analysis feedback signal is consistent with the CAN bus analog signal or not according to the label information of the analysis feedback signal and the label information of the CAN bus analog signal;

and if so, determining that the second CAN bus interface and the second RS422 interface are normal.

7. The on-board computer detection system of claim 6, wherein the environmental status signal further comprises a voltage analog signal, the application function comprises a voltage detection function; wherein,

the core controller is used for sending the voltage analog signal to the satellite borne computer by utilizing the second AD interface and determining whether the voltage detection function of the satellite borne computer is abnormal or not based on the received voltage feedback signal sent by the satellite borne computer;

and the satellite-borne computer is used for processing the voltage analog signal to obtain the voltage feedback signal.

8. The on-board computer detection system of claim 7, wherein the voltage feedback signal is a voltage signal including a flag bit fed back by the on-board computer through a second CAN bus interface; the core controller is configured to determine whether the voltage detection function is abnormal according to the following steps:

and determining whether the voltage detection function of the satellite borne computer is abnormal or not according to the digital information and the position information of the marking bits.

9. The detection system of the on-board satellite computer according to claim 2, wherein the single board test board further includes a resistor divider circuit, the resistor divider circuit is connected to the first AD interface, and the resistor divider circuit is configured to simulate voltage analog signals with different voltage values corresponding to the on-board satellite computer in an operating mode.

10. The on-board computer detection system of claim 2, wherein the USB interface is connected to an external terminal device; wherein,

the USB interface is used for sending the data feedback signal to external terminal equipment;

and the external terminal equipment is used for drawing a detection oscillogram based on the received data feedback signal sent by the USB interface.

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