CN114741248A - Spaceborne computer detection system - Google Patents
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Abstract
The application provides a detection system of a spaceborne computer, which comprises the spaceborne computer and a single board test board card, wherein the single board test board card comprises a plurality of first data interfaces and a core controller; the core controller is used for simulating various environment state signals of the satellite borne computer in a working mode, sending the corresponding environment state signals to the satellite borne computer through the first data interface, and determining whether the satellite borne computer is abnormal or not based on received data feedback signals sent by the satellite borne computer; and the satellite-borne computer is used for processing the environmental state signal to obtain a data feedback signal. The on-board computer test system can simulate the whole on-board computer to test each application function of the on-board computer under different working states through the single-board test board card, improves the test efficiency, reduces the test cost, and quickens the progress of checking out wrong designs and abnormal states in the design process of the on-board computer.
Description
Technical Field
The application relates to the technical field of space vehicles, in particular to a satellite-borne computer detection system.
Background
The on-board computer generally refers to a core control system of an on-board electronic system of a space vehicle such as a satellite, and tasks such as operation guarantee, task planning and data scheduling in the in-orbit working process of the satellite are all completed by the on-board computer. Due to the multiple task types and high data complexity of the satellite electronic system, the on-board computers generally have multiple data interfaces with multiple signal types and multiple rate requirements, and moreover, the same data interface may include multiple different data protocol conventions.
The traditional test method of the spaceborne computer generally adopts different external tools to test according to the requirements and data conventions of different interfaces on the spaceborne computer, the test method can consume more resource and equipment cost and has lower test efficiency, along with the development of the current digital circuit, the integration level of a circuit in the spaceborne computer is higher, the area of a mainboard is reduced, the density of interface circuits of the spaceborne computer is improved, the difficulty of testing a single interface is improved, and various interface data linkage conditions exist in the process of completing and processing tasks on a satellite of the spaceborne computer, so that the method for detecting the connection of the single interface by using the traditional external tools cannot completely simulate the working state of the whole spaceborne computer.
Disclosure of Invention
In view of this, an object of the present application is to provide a detection system for a satellite borne computer, which can simulate the whole satellite borne computer to test each application function of the satellite borne computer through a single board test board under different working states, so that while the test efficiency is improved and the test cost is reduced, the progress of troubleshooting of a faulty design and an abnormal state in the design process of the satellite borne computer is accelerated.
The embodiment of the application provides a detection system of a spaceborne computer, which comprises the spaceborne computer and a single board test board, wherein the single board test board comprises a plurality of first data interfaces and a core controller, and the first data interfaces are connected with a second data interface of the spaceborne computer in a stacked and oppositely-inserted manner; wherein,
the core controller is used for simulating various environment state signals of the satellite borne computer in a working mode, sending the corresponding environment state signals to the satellite borne computer through the first data interface, and determining whether the application function of the satellite borne computer is abnormal or not based on the received data feedback signals sent by the satellite borne computer;
and the satellite-borne computer is used for processing the environment state signal to obtain the data feedback signal and sending the data feedback signal to the core controller through the second data interface.
Further, the first data interface includes at least one of:
the device comprises a first RS422 interface, a first CAN bus interface, a first AD interface, a DA interface and a USB interface.
Further, the second data interface comprises a second AD interface, and the environmental status signal comprises a temperature analog signal; the application function includes a temperature control function, wherein,
the core controller is used for sending the temperature simulation signal to the satellite borne computer by utilizing the second AD interface and determining whether the temperature control function of the satellite borne computer is abnormal or not based on the received temperature feedback signal sent by the satellite borne computer;
and the satellite-borne computer is used for processing the temperature analog signal to obtain the temperature feedback signal.
Further, the core controller is configured to send the temperature analog signal to the satellite-borne computer by using the second AD interface, and includes:
and the core controller is used for sending the temperature analog signal to a second AD interface of the satellite borne computer through the DA interface and sending the temperature analog signal to the satellite borne computer by utilizing the second AD interface.
Further, the second data interface further comprises a second CAN bus interface and a second RS422 interface, and the environmental status signal further comprises a CAN bus analog signal; wherein,
the core controller is configured to send the CAN bus analog signal to the on-board computer by using the second CAN bus interface, and determine whether the second CAN bus interface and the second RS422 interface of the on-board computer are abnormal based on the received packed feedback signal sent by the on-board computer;
and the satellite-borne computer is used for processing the CAN bus analog signal to obtain a packaging feedback signal and sending the packaging feedback signal to the core controller through a serial port data interface.
Further, the core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the on-board computer are abnormal according to the following steps:
performing subpackaging and analysis processing on the received packaged feedback signals sent by the spaceborne computer to generate analysis feedback signals;
judging whether the analysis feedback signal is consistent with the CAN bus analog signal or not according to the label information of the analysis feedback signal and the label information of the CAN bus analog signal;
and if so, determining that the second CAN bus interface and the second RS422 interface are normal.
Further, the environment state signal further comprises a voltage analog signal, and the application function comprises a voltage detection function; wherein,
the core controller is used for sending the voltage analog signal to the satellite-borne computer by utilizing the second AD interface and determining whether the voltage detection function of the satellite-borne computer is abnormal or not based on the received voltage feedback signal sent by the satellite-borne computer;
and the satellite-borne computer is used for processing the voltage analog signal to obtain the voltage feedback signal.
Further, the voltage feedback signal is a voltage signal which is fed back by the spaceborne computer through a second CAN bus interface and contains a mark bit; the core controller is configured to determine whether the voltage detection function is abnormal according to the following steps:
and determining whether the voltage detection function of the satellite borne computer is abnormal or not according to the digital information and the position information of the marking bits.
Furthermore, the board test board further includes a resistance voltage divider circuit, the resistance voltage divider circuit is connected to the first AD interface, and the resistance voltage divider circuit is configured to simulate voltage simulation signals of different voltage values corresponding to the satellite borne computer in a working mode.
Further, the USB interface is connected with external terminal equipment; wherein,
the USB interface is used for sending the data feedback signal to external terminal equipment;
and the external terminal equipment is used for drawing a detection oscillogram based on the received data feedback signal sent by the USB interface.
Compared with the prior art, the detection system of the spaceborne computer provided by the embodiment of the application can simulate the whole spaceborne computer to test each application function of the spaceborne computer through the single board test board card under different working states, improves the test efficiency, reduces the test cost and quickens the progress of troubleshooting wrong design and abnormal states in the design process of the spaceborne computer.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a block diagram illustrating a detection system for on-board computation according to an embodiment of the present application;
FIG. 2 shows a block diagram of a USB interface design in a detection system for on-board computing according to an embodiment of the present application;
fig. 3 shows a block diagram of a resistance voltage divider circuit in a detection system for satellite-borne computation according to an embodiment of the present application;
fig. 4 shows a block diagram of a single board test board in the detection system for on-board computing according to the embodiment of the present application.
In the figure:
10-a satellite-borne computer detection system; 100-testing the board card by the single board; 110-a core controller; 111-programmable control chip; 1111-a microcontroller; 1112-a logical resource processing sub-chip; 112-level matching chip; 120-a first data interface; 130-resistance voltage divider circuit; r1 — first resistance; r2 — second resistance; u-power supply; 200-an on-board computer; 210-second data interface.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. Every other embodiment that can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present application falls within the protection scope of the present application.
Firstly, it is found through research that, in the prior art, a conventional test method for an on-board computer generally adopts different external tools to perform testing according to requirements and data conventions of different interfaces on the on-board computer, and this test method consumes more resource and equipment costs and has lower test efficiency, and with the development of the current digital circuit, the integration level of a circuit in the on-board computer becomes higher, the area of a main board is reduced, so that the density of interface circuits of the on-board computer is improved, the difficulty of testing a single interface is also improved, and in the process of completing and processing on-board tasks of the on-board computer, various interface data linkage conditions exist, so that the method for detecting the connection of a single interface by using the conventional external tool cannot completely simulate the working state of the whole on-board computer.
Therefore, the detection system for the spaceborne computer can simulate the whole spaceborne computer to test each application function of the spaceborne computer under different working states through the single board test board card, improves the test efficiency, reduces the test cost and quickens the progress of checking out wrong designs and abnormal states in the design process of the spaceborne computer.
Referring to fig. 1, fig. 1 is a block diagram of a detection system of a satellite-borne computer according to an embodiment of the present disclosure. As shown in fig. 1, a system 10 for detecting a satellite borne computer provided in the embodiment of the present application includes a satellite borne computer 200 and a single board test board 100, where the single board test board 100 includes a plurality of first data interfaces 120 and a core controller 110, and the first data interfaces 120 are connected to second data interfaces 210 of the satellite borne computer 200 in a stacked and plugged manner.
In the foregoing specific embodiment, the on-board computer 200 in the on-board computer detection system 10 is a core control system on the spacecraft, and the single board test board 100 included in the on-board computer detection system 10 is a device that can detect configuration data of each interface and function data of each interface in the on-board computer 200, and can detect processing configuration data of the on-board computer 200 when executing different flight tasks, and the single board test board 100 itself has independent operation and programmable conditions, compared with the on-board computer 200, the single board test board 100 is equivalent to a lower computer detection device that is actively controlled by on-board computing, and the specific connection manner is: the on-board computer is connected to the first data interface 120 of the single board test board 100 in a stacked manner through the second data interface 210, so as to facilitate data interaction between the on-board computer and the single board test board 100.
In the above, the single board test board 100 performs corresponding data flow design according to an actual usage scenario, and sends various environmental status signals simulating the on-board computer 200 in a working mode to the on-board computer 200 through the multiple types of first data interfaces 120, so as to simulate a data interaction process between a real application subsystem and the on-board computer 200 in satellite work, and determine whether configuration data of the on-board computer 200 and functional data of the second interface are abnormal or not according to status performance and task processing results of the on-board computer 200 in the simulation process.
Here, the size of the single board test board 100 is designed to be stacked and inserted according to the actual size of the spaceborne computer 200, so that the single board test board 100 can simulate the actual installation conditions of the spaceborne computer 200, and can perform various related environmental tests together with the spaceborne computer 200, thereby facilitating the acceptance test.
The on-board computer 200 is configured to ensure an operation state, a mission planning, data scheduling, and the like of the space vehicle in the in-orbit working process, and the second data interface 210 of the on-board computer 200 at least includes a second RS422 interface, a second CAN bus interface, a second AD interface, and the like, and the mission working mode of the on-board computer 200 includes a plurality of situations where the second data interface 210 is linked.
Here, a specific embodiment illustrates a plurality of task operation modes of the second data interface 210 linkage, as follows:
for example, after the second CAN bus interface performs packet processing on the received task data, the second CAN bus interface receives a data sending instruction, and needs to transmit data in a specific format from the second RS422 interface to the packet-processed task data, and parse the received data according to an interface protocol of the second RS422 interface, so that a logic value of some OC ports, that is, the second RS422 interface in the embodiment provided in the present application, may be changed, where the OC port is an output comparison port and is an output for a pin. It may be set to count output high or output low, which is mainly used for outputting pulses.
The core controller is configured to simulate various environment state signals of the on-board computer 200 in a working mode, send the corresponding environment state signals to the on-board computer 200 through the first data interface 120, and determine whether an application function of the on-board computer 200 is abnormal based on a received data feedback signal sent by the on-board computer 200.
In the foregoing specific embodiment, the core controller 110 in the single board test board 100 is implemented by using an FPGA SoC chip, the core controller has FPGA logic resources and microcontroller 1111 processing resources at the same time, and the single board test board 100 designs and simulates various environment state signals of an external application stand-alone device in the working mode of the on-board computer 200 through the internal microcontroller 1111 processing resources, and designs a function algorithm corresponding to the relevant environment state signals, and sends various environment state signals representing various types of function data to the logic resource processing sub-chip 1112 in the single board test board 100 through the microcontroller 1111, and sends the various environment state signals to the on-board computer 200 through the logic resource processing sub-chip 1112 via the first data interface 120.
The FPGA SoC chip can satisfy logic implementation and data operation of a plurality of functions of the first data interface 120, and parallel timing design capability of the FPGA can coordinate data communication functions and data flows of each first data interface 120, and the microcontroller 1111 in the core controller can perform operation on data according to an algorithm, so that the detection system 10 of the spaceborne computer in the present application is more adaptive under the support of the core controller 110, and can more specifically simulate various environmental status signals of the spaceborne computer 200 in a working mode, wherein the microcontroller 1111 in the embodiment provided by the present application can be an ARM hard core controller.
In the above, the core controller is further configured to receive a data feedback signal sent by the on-board computer 200, and determine whether various application functions of the on-board computer 200 are abnormal according to the data feedback signal and a functional algorithm edited by the microcontroller 1111 inside the core controller.
Preferably, the first data interface 120 includes at least one of the following interfaces: the device comprises a first RS422 interface, a first CAN bus interface, a first AD interface, a DA interface and a USB interface.
Here, the second data interface 210 of the on-board computer 200 includes a second RS422 interface, a second CAN bus interface, and a second AD interface, the first RS422 interface in the first data interface 120 of the on-board test board 100 is connected to the second RS422 interface in the second data interface 210 of the on-board computer 200 in a stacked and plugged manner, the first CAN bus interface in the first data interface 120 of the on-board test board 100 is connected to the second CAN bus interface in the second data interface 210 of the on-board computer 200 in a stacked and plugged manner, both the DA interface and the first AD interface in the first data interface 120 of the on-board test board 100 are connected to the second AD interface in the second data interface 210 of the on-board computer 200 in a stacked and plugged manner, the USB interface in the first data interface 120 of the on-board test board 100 is connected to an external terminal device, the USB interface is used for sending a data feedback signal to external terminal equipment; and the external terminal equipment is used for drawing a detection oscillogram based on the received data feedback signal sent by the USB interface.
In the above description, in the process of designing the single board test board 100, due to consideration of portability of a user and consideration of actual situations of use of equipment (such as a space vehicle) in a satellite, the components of the single board test board 100 and the satellite computer 200 are connected in a stacked plug-in manner, and the stacked plug-in connection is also an installation method of electronic products in the satellite.
Here, part of the connection nodes of the first data interface 120 of the single board test board 100 are connected by plug-to-plug contact on the board, and various nodes used on the satellite can be fully contacted by adopting a single board type installation mode, so that the complete test on the physical interface and the electrical standard is realized except for the function coverage test.
The hardware design of the USB interface is realized by using a USB 2.0 communication protocol driving chip to realize a communication protocol, an FTDI FT232H controller chip is selected as the communication protocol driving chip in the embodiment provided by the application, the USB 2.0 high-speed data communication is realized by using the FTDI FT232H controller chip, and the controller supports 480Mbps at most.
As shown in fig. 2, fig. 2 is a block diagram of a USB interface design in a detection system for satellite-borne computing according to an embodiment of the present disclosure, in fig. 2, an FT232H controller chip is provided with a chip running clock by a 12MHz crystal oscillator, a protocol used in communication is determined by preprogramming an external directly-connected charged programmable read-only memory (EEPROM), a data interface of a USB 2.0 is led out from DP and DM pins of the FT232H controller chip, and the two signals are connected to a communication connector to complete external connection to the USB 2.0 interface.
Thus, when using FT232H to drive USB 2.0, FT232H needs to be configured as an FT245 mode synchronous FIFO interface, and USB 2.0 serial data is converted into encoded data with 8bit width. When this mode is used, the main signals are as shown in table 1:
TABLE 1 signal table for connecting FT232H with star sensor main control chip
Here, the chip read operation driver design for FT232H in table 1 is as follows:
when the chip outputs the RXF # to a low level, reading operation can be carried out, before the RD # signal becomes the low level, the FPGA SoC system can set the OE # to be the low level, the signal direction of the data bus driver is output, and the FPGA SoC end can read data; after OE # is low, the first data byte begins to appear on the data, once all data has been read, the chip will drive RXF # high, after RXF # is high, all data appearing on the data bus is invalid and should be ignored.
The FT232H chip write operation driver is designed as follows:
when the TXE # is low, the writing operation can be started, when the writing data operation is effective, the WR # is changed from high level to low level, as long as the TXE # is always low, the writing operation can be continuously carried out on each clock, the FPGA SoC resource chip driver has to monitor signals of the TXE # and the WR # so as to check whether a receiving party receives data, when the signals of the TXE # and the WR # are not low, the data cannot be received by a data bus, and all data appearing on the data bus are invalid.
Here, the USB 2.0 driving signal is controlled and data signal is collected and read by a core controller in the board test board 100, after the external terminal device is designed to receive the data feedback signal and perform auxiliary analysis, the external terminal device performs auxiliary analysis on the data feedback signal and provides dynamic analysis data to draw a waveform diagram, which is convenient for a tester to view more intuitively.
The on-board computer 200 is configured to process the environment state signal to obtain the data feedback signal, and send the data feedback signal to the core controller through the second data interface 210.
In the above embodiment, the spaceborne computer 200 is configured to process the environmental status signal simulated by the single board test board, wherein the processing mode includes, but is not limited to, determining, calculating, packaging, and designing, and after the processing, send the obtained data feedback signal to the core controller through the second data interface 210.
Preferably, the second data interface 210 comprises a second AD interface, and the environment status signal comprises a temperature analog signal; the application function comprises a temperature control function, wherein the core controller is configured to utilize the second AD interface to send the temperature simulation signal to the satellite borne computer 200, and determine whether the temperature control function of the satellite borne computer 200 is abnormal based on the received temperature feedback signal sent by the satellite borne computer 200.
And the satellite-borne computer 200 is used for processing the temperature analog signal to obtain the temperature feedback signal.
In the above description, when the temperature control function of the on-board computer 200 needs to be detected in the embodiment provided in the present application, at this time, the on-board computer detection system 10 needs to simulate an external temperature control application subsystem, at this time, the microcontroller 1111 of the core controller simulates a first temperature digital signal, and converts the first temperature digital signal into a first analog signal through the DA conversion controller in the logic resource processing sub-chip 1112, and sends the first analog signal to the second AD interface of the on-board computer 200 through the DA interface, the on-board computer 200 converts the first analog signal into a first digital signal through the AD, the first analog signal is converted into a first data signal through the AD, at this time, the on-board computer 200 determines whether the first data signal is higher than the preset low temperature threshold, if the first data signal is higher than the preset low temperature threshold, the on-board computer 200 starts to heat, outputting the heated temperature feedback signal to a microcontroller 1111 in the detection system through a second AD interface, wherein the microcontroller 1111 simulates a second temperature digital signal (the second temperature digital signal is greater than a preset low-temperature threshold of the on-board computer 200 and less than a preset high-temperature threshold of the on-board computer 200), and sends the second temperature digital signal to the on-board computer 200, if the on-board computer 200 continuously outputs the continuously heated temperature feedback signal to the detection system after processing, the temperature control function of the on-board computer 200 is proved to be abnormal at this time, then the microcontroller 1111 of the core controller simulates a third temperature digital signal, converts the third temperature digital signal into a third analog signal through a DA conversion controller in a logic resource processing sub-chip 1112, and sends the third analog signal to the second AD interface of the on-board computer 200 through the DA interface, the on-board computer 200 converts the third analog signal into a third digital signal (the third digital signal is higher than the preset high temperature threshold) via the AD, the third analog signal is converted into a third data signal via the AD, at this time, if the on-board computer 200 determines whether the third data signal is higher than the preset low temperature threshold, and outputs a temperature feedback signal for stopping heating to the detection system, the detection system determines that the temperature control function of the on-board computer 200 is abnormal according to the temperature feedback signal.
Here, the detection system performs timing analysis on the level and the PWM waveform of the temperature feedback signal, and if the analysis result is different from the operation state result represented by the temperature feedback signal sent to the detection system by the satellite computer 200, it is determined that the temperature control function of the satellite computer 200 is abnormal.
The temperature control function of the spaceborne computer 200 is specifically as follows: after the satellite borne computer 200 receives the temperature analog signal lower than the preset low-temperature threshold, heating the temperature analog signal, and determining that the working mode of the satellite borne computer 200 is a heating state; if the temperature analog signal is higher than the preset high temperature threshold, the on-board computer 200 determines to stop heating the temperature analog signal, and determines that the operating mode of the on-board computer 200 is a heating stop state.
Preferably, the second data interface 210 further includes a second CAN bus interface and a second RS422 interface, and the environmental status signal further includes a CAN bus analog signal; wherein,
the core controller is configured to send the CAN bus analog signal to the on-board computer 200 through the second CAN bus interface, and determine whether the second CAN bus interface and the second RS422 interface of the on-board computer 200 are abnormal based on the received packed feedback signal sent by the on-board computer 200; the on-board computer 200 is configured to process the CAN bus analog signal to obtain a packaging feedback signal, and send the packaging feedback signal to the core controller through a serial port data interface.
In the above, when the second CAN bus interface and the second RS422 interface of the on-board computer 200 need to be detected in the embodiment provided by the present application, the simplest case is:
the first CAN bus interface of the first data interface 120 in the detection system is connected with the first CAN bus interface of the second data interface 210 in the on-board computer 200, the first RS422 interface of the first data interface 120 in the detection system is connected with the second RS422 interface of the second data interface 210 in the on-board computer 200, and if the second CAN bus interface or the second RS422 interface of the on-board computer 200 CAN successfully send a corresponding data feedback signal, it is said that the functional design of the second CAN bus interface or the second RS422 interface of the on-board computer 200 is not abnormal.
Here, during the task processing of the on-board computer 200, besides the basic data transmission and forwarding functions, there is also a situation of interface linkage between the second CAN bus interface and the second RS422 interface, for example, if the telemetering remote control environment state signal received by the second CAN bus is sent to a single ground device, the second CAN bus and the second RS422 interface need to be subjected to serial linkage detection, which is illustrated below:
if the single board test board 100 needs to send the simulated temperature measurement simulation signals of 100 thermal controllers to the on-board computer 200 through the second AD interface on the on-board computer 200, after the on-board computer 200 performs some series of processing and calculation judgment processing of the complex on-board computer 200, the processed data feedback signals are sent to the data transmission system, and the signal channel between the on-board computer 200 and the data transmission system is strictly one-to-one, so that the single board test board 100 needs to simulate the data transmission system at this time, receive the corresponding type of data feedback signals one-to-one through the first RS422 interface on the single board test board 100, and send the received data feedback signals to the ground receiving station, thereby realizing the detection of the linkage of the first data interface 120 in the on-board computer 200.
Preferably, the core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the on-board computer 200 are abnormal according to the following steps:
and performing subpackaging and analysis processing on the received packaged feedback signals sent by the spaceborne computer 200 to generate analysis feedback signals.
In the above, the on-board computer 200 packages the received CAN bus analog signal, sends the packaged data feedback signal to the board test board 100, and the board test board 100 performs packetization and analysis on the packaged data feedback signal to generate an analysis feedback signal, and analyzes the specific content on the back of the analysis feedback signal.
And judging whether the analysis feedback signal is consistent with the CAN bus analog signal or not according to the label information of the analysis feedback signal and the label information of the CAN bus analog signal.
And if so, determining that the second CAN bus interface and the second RS422 interface are normal.
In the above, if the single board test board 100 determines that the content of the analysis feedback signal is consistent with the content of the CAN bus analog signal after the single board test board labels the CAN bus analog signal and the analysis feedback signal, it determines that the second CAN bus interface and the second RS422 interface are both normal.
Here, if the single board test board 100 determines that the content of the analysis feedback signal is inconsistent with the content of the CAN bus analog signal after labeling the CAN bus analog signal and the analysis feedback signal, it determines that there is an abnormality in the second CAN bus interface and the second RS422 interface, and at this time, redesign and debug tests are performed on the second CAN bus interface or the second RS422 interface according to actual conditions.
Preferably, the environmental status signal further includes a voltage analog signal, and the application function includes a voltage detection function; the core controller is configured to send the voltage analog signal to the on-board computer 200 through the second AD interface, and determine whether the voltage detection function of the on-board computer 200 is abnormal based on the received voltage feedback signal sent by the on-board computer 200; and the satellite borne computer 200 is used for processing the voltage analog signal to obtain the voltage feedback signal.
In the above, the function of the on-board computer 200 for detecting whether the power supply is abnormal specifically is:
the second AD interface of the on-board computer 200 usually collects a reference voltage value of V, that is, when the second AD interface performs quantization transmission of analog signals, the full range is 5V, so that the on-board computer 200 divides the voltage values of the above-mentioned various power supplies (the voltage values of the power supplies are usually 28V, 12V, 5V, and the like) by the first resistor and the second resistor to obtain a voltage of 3V, and accesses the accessed voltage of 3V to the input terminal of the second AD interface. When the second AD interface of the satellite borne computer 200 receives the 3V voltage, it is determined that the corresponding high voltage value is also correct, because the high voltage value used for actual power supply and the collected voltage value are divided by the resistor, and when the absolute value of the difference between the collected voltage value and the 3V voltage value exceeds the preset voltage value calculated by the satellite borne computer, it is determined that the satellite borne computer 200 detects that the power supply of the power supply is abnormal.
When the single board test board 100 in the embodiment provided by the application needs to detect the stand-alone power supply function of the on-board computer 200, here, the single board test board 100 first outputs a voltage analog signal corresponding to the 3V voltage analog signal according to the chip through the DA interface, and sends the value to the DA interface, and at this time, the second AD interface of the on-board computer 200 obtains a quantized value of the analog signal. The on-board computer 200 will give out whether the voltage meets the normal working state according to the threshold deviation judgment mode, and send a voltage feedback signal through the second CAN bus interface, if the voltage feedback signal is a preset mark symbol representing normal power supply at this time, the single-board test board 100 determines that the voltage detection function of the on-board computer 200 is normal; when the single board test board 100 outputs a voltage analog signal with a large deviation of 3V, the on-board computer 200 also provides a quantized voltage value corresponding to the voltage analog signal according to a threshold deviation determination method, and if the voltage feedback signal at this time is a preset mark symbol representing normal power supply, the single board test board 100 determines that the voltage detection function of the on-board computer 200 is abnormal.
Preferably, the voltage feedback signal is a voltage signal including a flag bit, which is fed back by the on-board computer 200 through a second CAN bus interface; the core controller is configured to determine whether the voltage detection function is abnormal according to the following steps:
and determining whether the voltage detection function of the satellite borne computer 200 is abnormal or not according to the digital information and the position information of the mark bit.
In the above, the flag bit is a representation bit of the working condition of the power supply in the table, and the flag bit can be set by user, for example, the flag bit can be set as the last bit of the voltage feedback signal according to the digital information and the position information, for example, "0" represents that the voltage detection function is abnormal, and "1" represents that the voltage detection function is abnormal, and "0" represents that the voltage detection function is normal.
Preferably, the single board test board 100 further includes a resistance voltage dividing circuit 130, the resistance voltage dividing circuit 130 is connected to the first AD interface, the resistance voltage dividing circuit 130 is configured to simulate voltage simulation signals of different voltage values corresponding to the satellite-borne computer 200 in a working mode, as shown in fig. 3, fig. 3 is a block diagram of a structure of the resistance voltage dividing circuit in the detection system for satellite-borne computation provided in the embodiment of the present application, the resistance voltage dividing circuit 130 includes a first resistor R1, a second resistor R2 and a U power supply source, a positive terminal of the power supply source U is connected to the first resistor R1 and the second resistor R2 in series and then is grounded, a negative terminal of the power supply source U is grounded, and one end of the first resistor R1 connected to the second resistor R2 is connected to the first AD interface.
Compared with the prior art, the on-board computer detection system 10 provided by the embodiment of the application simulates various environment state signals of the on-board computer 200 in a working mode through the single board test board, the whole on-board computer 200 can be simulated in different working states, the test of each interface of the on-board computer 200 is realized, the process of testing the single interface by using different external tools is avoided, the test efficiency is improved, the test cost is reduced, and meanwhile, the progress of checking out wrong designs and abnormal states in the design process of the on-board computer 200 is accelerated.
Referring to fig. 4, fig. 4 is a block diagram of a single board test board 100 in a detection system for satellite-borne computing according to another embodiment of the present application. As shown in fig. 4, a single board test board 100 provided in the embodiment of the present application includes:
the detection system 10 of the spaceborne computer comprises a spaceborne computer 200 and a single board test board 100, wherein the single board test board 100 comprises a plurality of first data interfaces 120 and a core controller, the first data interfaces 120 are connected with a second data interface 210 of the spaceborne computer in a stack-type plug-in manner, the core controller comprises a programmable control chip 111 and a level matching chip 112, and the programmable control chip 111 comprises a microcontroller 1111 and a logic resource processing sub-chip 1112.
The level matching chip 112 is configured to match the corresponding first data interface 120 to obtain various environment status signals of the analog on-board computer 200 in the operating mode from the programmable control chip 111.
The microcontroller 1111 employs an ARM hardcore microcontroller 1111, wherein the logic resource processing sub-chip 1112 includes a CAN controller, a serial port controller, an LVDS interface controller, a DA conversion controller, an AD conversion controller, and a USB interface timing, and the level matching chip 112 corresponding thereto includes a CAN bus transceiver, a RE422 level matching chip 112, a DA conversion chip, an AD conversion chip, and a USB protocol chip.
The RE422 level matching chip 112 adopts a MAX3488ESA RS422 differential level protocol chip, a single-end serial communication interface is converted into an RS422 interface, the CAN bus transceiver adopts a TJA1040T model chip, the AD conversion chip adopts an ADS8344 model chip, and the DA conversion chip adopts a DAC80508 model chip.
Compared with the prior art, the single board test board 100 in the embodiment provided by the application realizes that the test of each interface of the on-board computer 200 can be performed in different working states by simulating various environmental state signals of the on-board computer 200 in the working mode, so that the process of performing a single interface test by using different external tools is avoided, the test efficiency is improved, the test cost is reduced, and the progress of checking out wrong designs and abnormal states in the design process of the on-board computer 200 is accelerated.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the system described above may refer to the corresponding process in the foregoing system embodiment, and is not described herein again. In the several embodiments provided in the present application, it should be understood that the disclosed system may be implemented in other ways. The above-described system embodiments are merely illustrative, and for example, the division of the units into only one logical division may be implemented in other ways, and for example, multiple subsystems or modules may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some communication interfaces, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A detection system of a spaceborne computer is characterized by comprising the spaceborne computer and a single board test board, wherein the single board test board comprises a plurality of first data interfaces and a core controller, and the first data interfaces are connected with a second data interface of the spaceborne computer in a stacked and inserted mode; wherein,
the core controller is used for simulating various environment state signals of the satellite borne computer in a working mode, sending the corresponding environment state signals to the satellite borne computer through the first data interface, and determining whether the application function of the satellite borne computer is abnormal or not based on the received data feedback signals sent by the satellite borne computer;
and the satellite-borne computer is used for processing the environment state signal to obtain the data feedback signal and sending the data feedback signal to the core controller through the second data interface.
2. The on-board computer detection system of claim 1, wherein the first data interface comprises at least one of:
the device comprises a first RS422 interface, a first CAN bus interface, a first AD interface, a DA interface and a USB interface.
3. The on-board computer detection system of claim 1, wherein the second data interface comprises a second AD interface, the environmental status signal comprises a temperature analog signal; the application function comprises a temperature control function; wherein,
the core controller is used for sending the temperature simulation signal to the satellite borne computer by utilizing the second AD interface and determining whether the temperature control function of the satellite borne computer is abnormal or not based on the received temperature feedback signal sent by the satellite borne computer;
and the satellite-borne computer is used for processing the temperature analog signal to obtain the temperature feedback signal.
4. The on-board computer detection system of claim 3, wherein the core controller is configured to send the temperature analog signal to the on-board computer using the second AD interface, and comprises:
and the core controller is used for sending the temperature analog signal to a second AD interface of the satellite borne computer through the DA interface and sending the temperature analog signal to the satellite borne computer by utilizing the second AD interface.
5. The on-board computer detection system of claim 3, wherein the second data interface further comprises a second CAN bus interface and a second RS422 interface, and the environmental status signal further comprises a CAN bus analog signal; wherein,
the core controller is configured to send the CAN bus analog signal to the on-board computer by using the second CAN bus interface, and determine whether the second CAN bus interface and the second RS422 interface of the on-board computer are abnormal based on the received packed feedback signal sent by the on-board computer;
and the satellite-borne computer is used for processing the CAN bus analog signal to obtain a packaging feedback signal and sending the packaging feedback signal to the core controller through a serial port data interface.
6. The on-board computer detection system of claim 5, wherein the core controller is specifically configured to determine whether the second CAN bus interface and the second RS422 interface of the on-board computer are abnormal according to the following steps:
subpackaging and analyzing the received packaged feedback signals sent by the satellite-borne computer to generate analysis feedback signals;
judging whether the analysis feedback signal is consistent with the CAN bus analog signal or not according to the label information of the analysis feedback signal and the label information of the CAN bus analog signal;
and if so, determining that the second CAN bus interface and the second RS422 interface are normal.
7. The on-board computer detection system of claim 6, wherein the environmental status signal further comprises a voltage analog signal, the application function comprises a voltage detection function; wherein,
the core controller is used for sending the voltage analog signal to the satellite borne computer by utilizing the second AD interface and determining whether the voltage detection function of the satellite borne computer is abnormal or not based on the received voltage feedback signal sent by the satellite borne computer;
and the satellite-borne computer is used for processing the voltage analog signal to obtain the voltage feedback signal.
8. The on-board computer detection system of claim 7, wherein the voltage feedback signal is a voltage signal including a flag bit fed back by the on-board computer through a second CAN bus interface; the core controller is configured to determine whether the voltage detection function is abnormal according to the following steps:
and determining whether the voltage detection function of the satellite borne computer is abnormal or not according to the digital information and the position information of the marking bits.
9. The detection system of the on-board satellite computer according to claim 2, wherein the single board test board further includes a resistor divider circuit, the resistor divider circuit is connected to the first AD interface, and the resistor divider circuit is configured to simulate voltage analog signals with different voltage values corresponding to the on-board satellite computer in an operating mode.
10. The on-board computer detection system of claim 2, wherein the USB interface is connected to an external terminal device; wherein,
the USB interface is used for sending the data feedback signal to external terminal equipment;
and the external terminal equipment is used for drawing a detection oscillogram based on the received data feedback signal sent by the USB interface.
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| CN116795724A (en) * | 2023-08-23 | 2023-09-22 | 赛维航电科技有限公司 | Method, system, equipment and medium for testing unmanned aerial vehicle loading equipment software interface |
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| CN116795724A (en) * | 2023-08-23 | 2023-09-22 | 赛维航电科技有限公司 | Method, system, equipment and medium for testing unmanned aerial vehicle loading equipment software interface |
| CN116795724B (en) * | 2023-08-23 | 2023-11-14 | 赛维航电科技有限公司 | Method, system, equipment and medium for testing unmanned aerial vehicle loading equipment software interface |
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