CN114725268A - Miniature light-emitting diode, preparation method and display screen - Google Patents
Miniature light-emitting diode, preparation method and display screen Download PDFInfo
- Publication number
- CN114725268A CN114725268A CN202210382288.8A CN202210382288A CN114725268A CN 114725268 A CN114725268 A CN 114725268A CN 202210382288 A CN202210382288 A CN 202210382288A CN 114725268 A CN114725268 A CN 114725268A
- Authority
- CN
- China
- Prior art keywords
- layer
- improvement
- semiconductor layer
- semiconductor
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000010410 layer Substances 0.000 claims abstract description 599
- 239000004065 semiconductor Substances 0.000 claims abstract description 134
- 230000006872 improvement Effects 0.000 claims abstract description 101
- 239000011241 protective layer Substances 0.000 claims abstract description 80
- 238000005530 etching Methods 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 22
- 238000002955 isolation Methods 0.000 claims description 88
- 229910052751 metal Inorganic materials 0.000 claims description 65
- 239000002184 metal Substances 0.000 claims description 65
- 239000000463 material Substances 0.000 claims description 44
- 239000010936 titanium Substances 0.000 claims description 37
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 24
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 21
- 238000009413 insulation Methods 0.000 claims description 21
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 20
- 239000010931 gold Substances 0.000 claims description 18
- 229910052719 titanium Inorganic materials 0.000 claims description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052707 ruthenium Inorganic materials 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 5
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 230000004888 barrier function Effects 0.000 abstract description 4
- 239000003153 chemical reaction reagent Substances 0.000 abstract description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 19
- 230000000694 effects Effects 0.000 description 9
- 229910044991 metal oxide Inorganic materials 0.000 description 8
- 150000004706 metal oxides Chemical class 0.000 description 8
- 230000000149 penetrating effect Effects 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000002131 composite material Substances 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The present disclosure relates to a micro light emitting diode, a display screen and a preparation method in the technical field of light emitting display, wherein the micro light emitting diode comprises: the protective layer is arranged on one side, away from the second semiconductor layer, of the improvement layer; the protective layer includes at least an insulating protective layer. Therefore, the insulating protective layer is arranged on the improvement layer and serves as a hardware mask layer, plasma and chemical reagents can be isolated, and the improvement layer is prevented from being damaged or destroyed in the subsequent process; the insulating protective layer is used as an etching barrier layer, so that the etching depth of a subsequent film layer stays in the insulating protective layer to form a stable etching interval, and the uniformity and the accuracy of the etching depth are ensured; after the protective layer is additionally arranged, the device is protected, the process window is larger, and therefore the manufacturing yield is improved.
Description
Technical Field
The disclosure relates to the technical field of light emitting display, in particular to a micro light emitting diode, a preparation method and a display screen.
Background
Micro Light Emitting Diode (Micro-LED) Display screens are superior to currently used Liquid Crystal Displays (LCDs) and Organic Light Emitting Diode (OLED) Display screens in many aspects, for example, the screens are thinner, have higher efficiency, longer service life, higher brightness, and have faster response speed, so the Micro LED displays are receiving more and more attention.
In the related art, it is difficult to make a low-resistivity P-GaN ohmic contact in a micro light emitting diode, and on one hand, it is difficult to grow heavily-doped P-GaN material (P-type concentration)>1018cm-3) (ii) a Another aspect is the lack of suitable contact metal materials, the work function of P-GaN materials is large, about 7.5eV, and the metal with the largest work function, platinum (Pt), is also only 5.65 eV. In addition, the conditions of the metallization process (including surface treatment, metal deposition, and alloying) can also affect the resistivity of the P-GaN ohmic contact.
Aiming at the problems, metal or metal oxide is used for forming ohmic contact with the P-GaN material, and contact materials such as metal or metal oxide are arranged between the P-GaN material and the wire metal; although the thickness of the contact material is thin, the resistivity of the device can be effectively reduced. However, the contact material is vulnerable to plasma and various chemicals during the subsequent process, thereby affecting the effect of improving the contact resistivity, and further causing the overall performance of the device to be degraded.
Disclosure of Invention
In order to solve the technical problem, the present disclosure provides a micro light emitting diode, a manufacturing method thereof, and a display screen.
The present disclosure provides a micro light emitting diode, including:
an epitaxial layer; the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked; wherein, the edge of the first semiconductor layer forms a mesa;
the improvement layer is arranged on one side, away from the light emitting layer, of the second semiconductor layer, and forms ohmic contact with the second semiconductor layer;
the protective layer is arranged on one side, away from the second semiconductor layer, of the improvement layer; the protective layer at least comprises an insulating protective layer;
the isolation layer is arranged on one side, away from the improvement layer, of the insulation protection layer and completely covers the exposed surfaces of the epitaxial layer, the improvement layer and the insulation protection layer;
the anode metal layer is arranged on one side, away from the insulating protection layer, of the isolation layer and penetrates through the insulating protection layer and a first through hole in the thickness of the isolation layer;
and the cathode metal layer is arranged on one side of the isolation layer, which is deviated from the first semiconductor layer, and in a second through hole which penetrates through the thickness of the isolation layer and is connected with the first semiconductor layer.
Optionally, the protective layer further comprises a conductive protective layer.
Optionally, the conductive protection layer is disposed between the insulating protection layer and the improvement layer.
Optionally, the material of the insulating protection layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
Optionally, the material of the conductive protection layer includes at least one of titanium, titanium nitride, and indium tin oxide.
Optionally, the material of the improvement layer comprises at least one of gold, nickel, platinum, palladium, titanium, ruthenium, tantalum, indium tin oxide, and indium zinc oxide.
Optionally, the light emitting layer is a multiple quantum well light emitting layer.
The present disclosure also provides a method for manufacturing a micro light emitting diode, including:
forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked; forming a mesa at the edge of the first semiconductor layer by an etching process;
forming an improvement layer on one side of the second semiconductor layer, which is far away from the light-emitting layer; the improvement layer and the second semiconductor layer form ohmic contact;
forming a protective layer on one side of the improvement layer, which is far away from the second semiconductor layer; wherein the protective layer at least comprises an insulating protective layer;
forming an isolation layer on one side of the insulation protection layer, which is far away from the improvement layer, on the table top at the edge of the first semiconductor layer and on the side surfaces of the epitaxial layer, the improvement layer and the insulation protection layer;
etching the isolation layer and the insulating protection layer above the improvement layer in a layered manner until the improvement layer is exposed, and forming a first through hole; wherein the isolation layer and the insulation protection layer adopt different etching selection ratios;
etching the isolation layer on the table top at the edge of the first semiconductor layer until the first semiconductor layer is exposed, and forming a second through hole;
forming an anode metal layer on one side of the isolation layer, which is far away from the insulating protection layer, and in the first through hole; and forming a cathode metal layer on one side of the isolation layer, which is far away from the edge table-board of the first semiconductor layer, and in the second through hole.
Optionally, the protective layer further comprises a conductive protective layer; the forming of the protective layer on the side of the improvement layer away from the second semiconductor layer includes:
forming the conductive protection layer on one side of the improvement layer, which faces away from the second semiconductor layer;
and forming the insulating protection layer on one side of the conductive protection layer, which is far away from the improvement layer.
The present disclosure also provides a display screen, including: any of the above micro light emitting diodes.
Compared with the prior art, the technical scheme provided by the disclosure has the following advantages:
the invention provides a miniature light-emitting diode, a preparation method and a display screen, wherein the miniature light-emitting diode comprises: an epitaxial layer; the epitaxial layer comprises a first semiconductor layer, a second semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked; wherein, the edge of the first semiconductor layer forms a mesa; the improvement layer is arranged on one side, away from the light emitting layer, of the second semiconductor layer, and forms ohmic contact with the second semiconductor layer; the protective layer is arranged on one side, away from the second semiconductor layer, of the improvement layer; the protective layer at least comprises an insulating layer insulating protective layer; the isolation layer is arranged on one side of the insulation protection layer, which is far away from the improvement layer, and completely covers the exposed surfaces of the epitaxial layer, the improvement layer and the insulation protection layer; the anode metal layer is arranged on one side, away from the insulating protection layer, of the isolation layer and in a first through hole penetrating the insulating protection layer and the thickness of the isolation layer; and the cathode metal layer is arranged on one side of the isolation layer, which is deviated from the first semiconductor layer, and in the second through hole which penetrates through the thickness of the isolation layer and is connected with the first semiconductor layer. Therefore, the insulating protection layer is arranged above the improvement layer, on one hand, the insulating protection layer is used as a hardware mask layer, plasma and chemical reagents can be isolated, the improvement layer is prevented from being damaged or destroyed in the subsequent process, the ohmic contact effect formed by the improvement layer and the second semiconductor layer is ensured, and the overall performance of the device is ensured; on the other hand, the etching conditions of the insulating protection layer and the subsequent metal layer are different, and when the metal layer is etched, the insulating protection layer can be used as an etching barrier layer, so that the etching depth stays in the insulating protection layer, a stable etching interval is formed, and the uniformity and the accuracy of the etching depth are guaranteed. Meanwhile, after the protective layer is added, the device is well protected, and subsequent steps of etching, cleaning and the like are carried out without considering damage to ohmic contact, so that the process window is larger, and the effect of improving the manufacturing yield is realized.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a micro light emitting diode according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural view of the micro light emitting diode shown in FIG. 1 after an electrode layer is mounted thereon;
fig. 3 is a schematic structural diagram of another micro light emitting diode provided in the embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a display screen according to an embodiment of the present disclosure.
Wherein, 1, a display screen; 10. a micro light emitting diode; 11. an epitaxial layer; 111. a first semiconductor layer; 112. a second semiconductor layer; 113. a light emitting layer; 12. an improvement layer; 13. a protective layer; 131. an insulating protective layer; 132. a conductive protective layer; 14. an anode metal layer; 15. a cathode metal layer; 16. an isolation layer 17, a first via hole; 18. a second via.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
In combination with the background art, metal or metal oxide is usually used as a contact material to form ohmic contact with a P-GaN material, so as to achieve the purpose of reducing the resistivity of the device. However, in the device manufacturing process, the contact material is exposed to the plasma and various chemicals in the following processes, such as pixel etching, photoresist removal, and cleaning before and after exposure, and the contact material is easily damaged or destroyed in these processes, so that the effect of improving the contact resistivity is affected, and the overall performance of the device is reduced.
In order to solve the above technical problem, an embodiment of the present disclosure provides a micro light emitting diode, a manufacturing method thereof, and a display screen, where the micro light emitting diode includes: an epitaxial layer; the epitaxial layer comprises a first semiconductor layer, a second semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked; wherein, the edge of the first semiconductor layer forms a mesa; the improvement layer is arranged on one side, away from the light emitting layer, of the second semiconductor layer, and forms ohmic contact with the second semiconductor layer; the protective layer is arranged on one side, away from the second semiconductor layer, of the improvement layer; the protective layer at least comprises an insulating protective layer; the isolation layer is arranged on one side of the insulation protection layer, which is far away from the improvement layer, and completely covers the exposed surfaces of the epitaxial layer, the improvement layer and the insulation protection layer; the anode metal layer is arranged on one side, away from the insulating protection layer, of the isolation layer and in a first through hole penetrating the insulating protection layer and the thickness of the isolation layer; and the cathode metal layer is arranged on one side of the isolation layer, which is far away from the first semiconductor layer, and is connected with the first semiconductor layer in a second through hole penetrating through the thickness of the isolation layer. Therefore, the insulating protection layer is arranged above the improvement layer, on one hand, the insulating protection layer is used as a hardware mask layer, plasma and chemical reagents can be isolated, the improvement layer is prevented from being damaged or destroyed in the subsequent process, the ohmic contact effect formed by the improvement layer and the second semiconductor layer is ensured, and the overall performance of the device is ensured; on the other hand, the etching conditions of the insulating protection layer and the subsequent metal layer are different, and when the metal layer is etched, the insulating protection layer can be used as an etching barrier layer, so that the etching depth stays in the insulating protection layer, a stable etching interval is formed, and the uniformity and the accuracy of the etching depth are guaranteed. Meanwhile, after the protective layer is added, the device is well protected, and damage to ohmic contact is not considered when subsequent steps such as etching and cleaning are carried out, so that the process window is larger, and the effect of improving the manufacturing yield is achieved.
The micro light emitting diode, the manufacturing method and the display screen provided by the embodiment of the disclosure are exemplarily described below with reference to fig. 1 to 4.
Fig. 1 is a schematic structural diagram of a micro light emitting diode according to an embodiment of the present disclosure, and fig. 2 is a schematic structural diagram of the micro light emitting diode shown in fig. 1 after an electrode layer is mounted. Referring to fig. 1 and 2, the micro light emitting diode includes: an epitaxial layer 11; the epitaxial layer 11 includes a first semiconductor layer 111, a first semiconductor layer 112, a light emitting layer 113 and a first semiconductor layer 112 stacked in this order; wherein, the edge of the first semiconductor layer 111 forms a mesa; the improvement layer 12 is arranged on one side of the first semiconductor layer 112, which is far away from the light-emitting layer 113, and the improvement layer 12 and the first semiconductor layer 112 form ohmic contact; the protective layer 13 is arranged on one side of the improvement layer 12, which is far away from the first semiconductor layer 112; the protective layer 13 includes at least an insulating protective layer 131; the isolation layer 16 is arranged on one side of the insulation protection layer 131, which is far away from the improvement layer 12, and completely covers the exposed surfaces of the epitaxial layer 11, the improvement layer 12 and the insulation protection layer 131; the anode metal layer is arranged on one side, away from the insulating protection layer 131, of the isolation layer 16 and in the first through hole 17 penetrating through the insulating protection layer 131 and the thickness of the isolation layer 16; the cathode metal layer 15 is disposed on a side of the isolation layer 16 away from the first semiconductor layer 111, and in the second through hole 18 penetrating through a thickness of the isolation layer 16, and is connected to the first semiconductor layer 111.
The first semiconductor layer 111 is an N-type semiconductor layer, such as N-GaN; the second semiconductor layer 112 is a P-type semiconductor layer, such as P-GaN; the light-emitting layer 113 is provided between the first semiconductor layer 111 and the first semiconductor layer 112; the light-emitting layer 113 is a Multiple Quantum Well (MQWs) light-emitting layer.
The material of the improving layer 12 may be selected from metal or metal oxide, including at least one of gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), titanium (Ti), ruthenium (Ru), tantalum (Ta), Indium Tin Oxide (ITO), and Indium Zinc Oxide (IZO). The thickness of the film layer of the improving layer 12 is set to 5nm to 10 nm. The modified layer 12 forms ohmic contact with the second semiconductor layer 112, so as to reduce resistivity.
Here, the protective layer 13 may be provided as a single-layer structure including only the insulating protective layer 131; the protective layer 13 may also be provided as a composite structure, and may further include other film layers in addition to the insulating protective layer 131, such as an insulating protective layer-conductive protective layer composite structure or an insulating protective layer-insulating protective layer composite structure. The material of the insulating protective layer 131 includes silicon oxide (SiO)x) Silicon nitride (SiN)x) Silicon oxynitride and aluminum oxide (Al)2O3) At least one of (1).
Wherein the material of the isolation layer 16 comprises silicon (Si), silicon oxide (SiO)X) Or silicon nitride (SiN)X) At least one of them, e.g. silicon dioxide (SiO)2). The isolation layer 16 is disposed on a side of the insulating protection layer 131 away from the improvement layer 12, a mesa at an edge of the first semiconductor layer 111, and side surfaces of the epitaxial layer 11, the improvement layer, and the insulating protection layer 131. So set up, isolation layer 16 isolates most structure and dust, water, heat etc. in the external environment of miniature emitting diode, has reduced the influence of these factors to the device, has guaranteed the device performance, can also prolong the life of device.
Wherein the material of the anode metal layer 14 and the cathode metal layer 15 includes at least one of chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), or a gold-based alloy.
Wherein, a first through hole 17 is arranged at the corresponding insulating protection layer 131 and the isolation layer 16 at the improvement layer 12, and the first through hole penetrates through the thickness of the isolation layer 16 and the insulating protection layer 131; the anode metal layer 15 is disposed on a side of the isolation layer 16 away from the insulating protection layer 131 and in the first through hole 17, and is electrically connected to the improvement layer 12. A second through hole 18 is formed in the isolation layer 16 corresponding to the mesa position at the edge of the first semiconductor layer 111, and the second through hole 18 penetrates through the thickness of the isolation layer 16; the cathode metal layer 15 is disposed on a side of the isolation layer 16 away from the first semiconductor layer 111 and in the second via hole 18, and is electrically connected to the first semiconductor layer 111. So configured, the separator 16 separates the anode metal layer 14 and the cathode metal layer 15 from each other, preventing the device from short-circuiting.
Wherein the first via hole 17 is formed by etching the isolation layer 16 and the insulating protection layer 131 above the improvement layer in layers to expose the improvement layer 12; wherein, the isolation layer 16 and the insulation protection layer 131 use different etching selection ratios. During the etching process, due to the difference between the materials of the isolation layer 16 and the insulating protection layer 131, the etching conditions may have a large difference, and the etching rates corresponding to the same etching selectivity ratio have a large difference, for example, setting the etching selectivity ratio as condition a, the etching rate of the isolation layer 16 is relatively high, and the etching rate of the edge protection layer 131 is relatively low, even the etching rate is zero; if the etching selection ratio is set as condition B, the etching rate of the edge protection layer 131 is relatively high, and the etching rate of the isolation layer 16 is relatively low or even zero. Thus, by using the different etching conditions of the insulating protection layer 131 and the isolation layer 16, the insulating protection layer 131 can be used as an etching stop layer, so that the etching depth can be stopped at the insulating protection layer 131, a stable etching interval is formed, and the uniformity and accuracy of the etching depth are ensured. After the subsequent processes such as film etching and cleaning are completed, the etching conditions are adjusted, the insulating protection layer 131 is etched independently, and the etching depth is controlled to penetrate through the insulating protection layer 131 without damaging the ohmic contact between the improvement layer 12 and the second semiconductor layer 112; a first via hole 17 is formed through the film thickness of the insulating protective layer 131 and the isolation layer 16 on the improvement layer 12, and the first via hole 17 is used to electrically interconnect the anode metal layer 14 and the improvement layer 12.
In which the spacer layer 16 and the electrode layers (the anode metal layer 14 and the cathode metal layer 15) are stacked to form a mirror, thereby improving the light extraction efficiency.
Illustratively, as shown in fig. 1, the micro light emitting diode includes: an epitaxial layer 11, an improvement layer 12, a protection layer 13, an isolation layer 14, an anode metal layer 15 and a cathode metal layer 16; the epitaxial layer 11 includes a first semiconductor layer 111, a light emitting layer 113, and a second semiconductor layer 112 stacked in this order; the edge of the first semiconductor layer 111 forms a mesa; the improvement layer 12 is arranged on the side of the second semiconductor layer 112 away from the light-emitting layer 113, and the improvement layer 12 and the second semiconductor layer 112 form ohmic contact; the protective layer 13 is disposed on a side of the improvement layer 12 away from the second semiconductor layer 112, and the protective layer 13 only includes the insulating protective layer 131; the isolation layer 16 is arranged on one side of the insulating protection layer 131, which is far away from the improvement layer 12, the mesa at the edge of the first semiconductor layer 111, and the side surfaces of the epitaxial layer 11, the improvement layer and the insulating protection layer 131; arranging a first through hole 17 on the insulating protection layer 131 and the isolation layer 16 corresponding to the improvement layer 12, wherein the first through hole penetrates through the isolation layer 16 and the insulating protection layer 131, and the anode metal layer 15 is arranged on one side of the isolation layer 16, which is far away from the insulating protection layer 131, and in the first through hole 17 and is electrically connected with the improvement layer 12; a second through hole 18 is formed in the isolation layer 16 corresponding to the mesa position at the edge of the first semiconductor layer 111, and the second through hole 18 penetrates through the thickness of the isolation layer 16; the cathode metal layer 15 is disposed on a side of the isolation layer 16 away from the first semiconductor layer 111 and in the second via hole 18, and is electrically connected to the first semiconductor layer 111.
It should be noted that fig. 1 only exemplarily shows that the protection layer 13 is provided as a single-layer structure, and only includes the insulating protection layer 131, but does not constitute a limitation on the micro light emitting diode provided by the embodiment of the present disclosure. In other embodiments, the protection layer 13 may also be provided as a composite structure, and the number of the protection layer 13 including the film layer may be set according to the requirement of the micro light emitting diode, which is not limited herein.
The embodiment of the present disclosure provides a micro light emitting diode, which includes: an epitaxial layer 11; the epitaxial layer 11 includes a first semiconductor layer 111, a first semiconductor layer 112, a light emitting layer 113 and a first semiconductor layer 112 stacked in this order; wherein, the edge of the first semiconductor layer 111 forms a mesa; the improvement layer 12 is arranged on one side of the first semiconductor layer 112, which is far away from the light-emitting layer 113, and the improvement layer 12 and the first semiconductor layer 112 form ohmic contact; the protective layer 13 is arranged on one side of the improvement layer 12, which is far away from the first semiconductor layer 112; the protective layer 13 includes at least an insulating protective layer 131; the isolation layer 16 is arranged on one side of the insulation protection layer 131, which is far away from the improvement layer 12, and completely covers the exposed surfaces of the epitaxial layer 11, the improvement layer 12 and the insulation protection layer 131; the anode metal layer is arranged on one side, away from the insulating protection layer 131, of the isolation layer 16 and in the first through hole 17 penetrating through the insulating protection layer 131 and the thickness of the isolation layer 16; the cathode metal layer 15 is disposed on a side of the isolation layer 16 away from the first semiconductor layer 111, and in the second through hole 18 penetrating through a thickness of the isolation layer 16, and is connected to the first semiconductor layer 111. Therefore, by arranging the insulating protection layer 131 above the improvement layer 12, on one hand, the insulating protection layer 131 serves as a hardware mask layer, plasma and chemical reagents can be isolated, the improvement layer 12 is prevented from being damaged or destroyed in subsequent processes, the ohmic contact effect formed by the improvement layer 12 and the second semiconductor layer 112 is ensured, and the overall performance of the device is ensured; on the other hand, the etching conditions of the insulating protection layer 131 and the subsequent metal layer are different, and when the metal layer is etched, the insulating protection layer 131 can be used as an etching barrier layer, so that the etching depth stays in the insulating protection layer 131, a stable etching interval is formed, and the uniformity and accuracy of the etching depth are ensured. Meanwhile, after the protective layer 13 is added, the device is well protected, and subsequent steps of etching, cleaning and the like are carried out without considering damage to ohmic contact, so that the process window is larger, and the effect of improving the manufacturing yield is realized.
In some embodiments, as shown in fig. 3, a schematic structural diagram of another micro light emitting diode provided in the embodiments of the present disclosure is shown. Referring to fig. 3, in the micro light emitting diode, the protective layer 13 further includes a conductive protective layer 132.
The protective layer 13 has a composite structure including an insulating protective layer 131 and a conductive protective layer 132. The material of the insulating protective layer 131 includes silicon oxide (SiO)x) Silicon nitride (SiN)x) Silicon oxynitride (SiO)xNy) And alumina (Al)2O3) At least one of; the material of the conductive protection layer 132 includes at least one of titanium (Ti), titanium nitride (TiN), and Indium TiN Oxide (ITO); such as titanium/silicon oxide (Ti/SiO)x) Titanium/silicon nitride (Ti/SiN)x) Titanium/silicon oxynitride (Ti/SiO)xNy) Titanium/alumina (Ti/Al)2O3) Titanium nitride/silicon oxide (TiN/SiO)x) Titanium nitride/silicon nitride (TiN/SiN)x) Titanium nitride/silicon oxynitride (TiN/SiO)xNy) Or titanium nitride/alumina (TiN/Al)2O3) And so on.
It should be noted that the embodiments of the present disclosure only exemplarily show the material types of the insulating protection layer 131 and the conductive protection layer 132, but do not constitute a limitation on the micro light emitting diode provided by the embodiments of the present disclosure. In other embodiments, the insulating protection layer 131 and the conductive protection layer 132 may also be made of other materials known to those skilled in the art, and are not limited herein.
In some embodiments, the material of the insulating protective layer comprises silicon oxide (SiO)x) Silicon nitride (SiN)x) Silicon oxynitride (SiO)xNy) And alumina (Al)2O3) At least one of (1).
In some embodiments, the material of the conductive protection layer includes at least one of titanium (Ti), titanium nitride (TiN), and Indium TiN Oxide (ITO).
In some embodiments, as shown in fig. 3, in the micro light emitting diode, the conductive protection layer 132 is disposed between the insulating protection layer 131 and the improvement layer 12.
Wherein, the conductive protection layer 132 is disposed between the insulating protection layer 131 and the improvement layer 12, and when the insulating protection layer 131 is etched, the etching depth only penetrates through the insulating protection layer 131 and stays in the conductive protection layer 132; with the arrangement, the electrical interconnection of the two film layers on the two sides of the insulating protection layer 131 is realized, the damage and the damage of the subsequent process to the improvement layer 12 are completely avoided, and the ohmic contact effect formed by the improvement layer 12 and the second semiconductor layer 112 is ensured, so that the overall performance of the device is ensured.
It can be understood that fig. 3 only exemplarily illustrates that the micro light emitting diode includes the first semiconductor layer 111, the second semiconductor layer 112, the light emitting layer 113, the improvement layer 12, the insulating protection layer 131, the conductive protection layer 132, the anode metal layer 14, the cathode metal layer 15, and the isolation layer 16, but does not constitute a limitation to the micro light emitting diode provided by the embodiment of the present disclosure. In other embodiments, the micro light emitting diode further includes other film structures known to those skilled in the art, such as a buffer layer, an electron blocking layer, a mirror layer, and a metal connection layer, which are not limited herein.
In some embodiments, the material of the amelioration layer includes at least one of gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), titanium (Ti), ruthenium (Ru), tantalum (Ta), Indium Tin Oxide (ITO), and Indium Zinc Oxide (IZO).
The material of the improvement layer is metal or metal oxide, and the metal or metal oxide is in contact with the second semiconductor layer so as to achieve the purpose of reducing the resistivity; such as using gold-based materials (Ni/Au, Pd/Au, Ni/Pt/Au) in contact with the P-GaN material; using Ta/Ti in contact with P-GaN material, the resulting device resistivity was about 3X 10-5Ω·cm2(ii) a The device resistivity obtained by contacting Pt/Ru with P-GaN material is about 2.2 x 10-6Ω·cm2(ii) a The device resistivity obtained by using Ni/ITO in contact with P-GaN material is about 1 × 10-3Ω·cm2。
In some embodiments, the light emitting layer is a multiple quantum well light emitting layer.
The light emitting layer is configured as a multiple quantum well light emitting layer, and the multiple quantum well material can be selected from all materials known to those skilled in the art, such as InGaN/GaN, ZnCdSe/ZnSe, and InGaAsP/InP, which is not limited herein.
On the basis of the foregoing embodiments, embodiments of the present disclosure further provide a method for manufacturing a micro light emitting diode, and the steps of executing the method can manufacture the micro light emitting diode provided in the foregoing embodiments, which has corresponding beneficial effects, and are not described herein again to avoid repeated descriptions.
Specifically, the method comprises the following steps:
forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially overlapped; wherein, a mesa is formed at an edge of the first semiconductor layer by an etching process.
Wherein, step one includes:
(1) a first semiconductor layer is formed on one side of a substrate.
(2) A mesa is formed at an edge of the first semiconductor layer by an etching process.
(3) And forming a light-emitting layer on the side of the first semiconductor layer middle area, which is far away from the substrate.
(4) And forming a second semiconductor layer on the side of the light-emitting layer, which is far away from the first semiconductor layer.
Step two, forming an improved layer on one side of the second semiconductor layer, which is far away from the light-emitting layer; the improvement layer forms an ohmic contact with the second semiconductor layer.
Wherein, the material of the improving layer is selected from metal or metal oxide, such as at least one of gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), titanium (Ti), ruthenium (Ru), tantalum (Ta), Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO); and contacting the metal or metal oxide layer with the second semiconductor layer to reduce the resistivity.
And step three, forming a protective layer on one side of the improvement layer, which is far away from the second semiconductor layer.
Wherein the protective layer comprises at least an insulating protective layer.
Optionally, the protective layer further includes a conductive protective layer, and in this case, when the protective layer is a composite structure of an insulating protective layer and a conductive protective layer, "forming the protective layer on a side of the improvement layer away from the second semiconductor layer" includes:
(1) and forming a conductive protective layer on one side of the improvement layer, which is far away from the second semiconductor layer.
(2) And forming an insulating protective layer on one side of the conductive protective layer, which is far away from the improvement layer.
Wherein the material of the insulating protective layer comprises silicon oxide (SiO)x) Silicon nitride (SiN)x) Silicon oxynitride (SiO)xNy) And alumina (Al)2O3) At least one of; the material of the conductive protection layer comprises at least one of titanium (Ti), titanium nitride (TiN) and Indium TiN Oxide (ITO); the protective layer comprises titanium/silicon oxide (Ti/SiO)x) Titanium/silicon nitride (Ti/SiN)x) Titanium/silicon oxynitride (Ti/SiO)xNy) Titanium/alumina (Ti/Al)2O3) Titanium nitride/silicon oxide (TiN/SiO)x) Titanium nitride/silicon nitride (TiN/SiN)x) Titanium nitride/silicon oxynitride (TiN/SiO)xNy) Or titanium nitride/alumina (TiN/Al)2O3) At least one of (1).
And fourthly, forming an isolation layer on one side of the insulation protection layer, which is far away from the improvement layer, the table board at the edge of the first semiconductor layer, and the side surfaces of the epitaxial layer, the improvement layer and the insulation protection layer.
Wherein the material of the isolation layer comprises silicon (Si) and silicon oxide (SiO)X) Or silicon nitride (SiN)X) At least one of (1).
As shown in fig. 2, the isolation layer 16 completely covers a side of the insulating protection layer 131 facing away from the improvement layer 12, the mesa at the edge of the first semiconductor layer 111, and side surfaces of the epitaxial layer 11, the improvement layer 12, and the insulating protection layer 131. Therefore, the isolation layer 16 isolates most structures of the micro light-emitting diode from dust, water, heat and the like in the external environment, the influence of the factors on the device is reduced, the performance of the device is ensured, and the service life of the device can be prolonged.
Step five, etching the isolation layer and the insulating protection layer above the improvement layer in a layered manner until the improvement layer is exposed, and forming a first through hole; wherein the isolation layer and the insulating protection layer use different etching selection ratios.
Wherein, in conjunction with fig. 2, the isolation layer 16 and the insulating protection layer 131 are made of different materials, for example, the isolation layer 16 is made of silicon oxide (SiO)X) The insulating protection layer 131 is made of silicon nitride (SiN)X) The two materials are different, the etching selection ratio has larger difference, and the time speeds shown by the same etching condition are different; therefore, when the isolation layer 16 is etched, the etching conditions are set to be etching selection ratios that the etching speed of the isolation layer 16 is high and the etching speed of the insulating protection layer 131 is low, so that the etching depth stays in the insulating protection layer 131, a stable etching interval is formed, and the uniformity and accuracy of the etching depth are ensured; after the isolation layer 16 is etched, the etching conditions are adjusted to be the etching selection ratio that the etching speed of the insulating protection layer 131 is high, the etching depth is controlled to penetrate through the insulating protection layer 131 without damaging the ohmic contact between the improvement layer 12 and the second semiconductor layer 112, a first through hole 17 penetrating the thicknesses of the insulating protection layer 131 and the isolation layer 16 is formed in the improvement layer 12, and the first through hole 17 is used for realizing the electrical interconnection between the anode metal layer 14 and the improvement layer 12.
And sixthly, etching the isolation layer on the table top at the edge of the first semiconductor layer until the first semiconductor layer is exposed, and forming a second through hole.
With reference to fig. 2, a second through hole 18 is formed in the isolation layer on the mesa at the edge of the first semiconductor layer 111, and the second through hole 18 penetrates through the thickness of the isolation layer 16 to expose the first semiconductor layer 111.
Forming an anode metal layer on one side of the isolation layer, which is far away from the insulation protection layer, and in the first through hole; and forming a cathode metal layer on one side of the isolation layer, which is far away from the edge table-board of the first semiconductor layer, and in the second through hole.
Wherein the material of the anode metal layer and the cathode metal layer includes at least one of chromium (Cr), aluminum (Al), titanium (Ti), platinum (Pt), gold (Au), or gold-based alloy.
With reference to fig. 2, the anode metal layer 14 is disposed on a side of the isolation layer 16 away from the insulating protection layer 131 and in the first through hole 17, and the anode metal layer 14 is electrically connected to the improvement layer 12; the cathode metal layer 15 is disposed on a side of the isolation layer 16 facing away from the mesa at the edge of the first semiconductor layer 11 and in the second via 18, and the cathode metal layer 15 is electrically connected to the first semiconductor layer 111.
With reference to fig. 3, the anode metal layer 14 is disposed on a side of the isolation layer 16 away from the insulating protection layer 131 and in the first through hole 17, and the anode metal layer 14 is electrically connected to the conductive protection layer 132; the cathode metal layer 15 is disposed on a side of the isolation layer 16 facing away from the mesa at the edge of the first semiconductor layer 11 and in the second via 18, and the cathode metal layer 15 is electrically connected to the first semiconductor layer 111.
The isolating layer is made of transparent material and is superposed with the anode metal layer and the cathode metal layer to form a reflector and raise light extraction rate.
On the basis of the foregoing embodiment, an embodiment of the present disclosure further provides a display screen, and as shown in fig. 4, a schematic structural diagram of the display screen provided in the embodiment of the present disclosure is provided. Referring to fig. 4, the display screen 1 includes: any of the above-mentioned micro light emitting diodes 10 has corresponding beneficial effects, and is not described herein again to avoid repeated descriptions.
Illustratively, as shown in fig. 4, the display screen 1 includes an array of micro-leds 10.
It should be noted that fig. 4 only exemplarily shows that the display screen 1 includes six micro light emitting diodes 10, but does not constitute a limitation of the display screen provided by the embodiment of the present disclosure. In other embodiments, the number and the type of the micro light emitting diodes are set according to the requirement of the display screen, which is not limited herein.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A micro light emitting diode, comprising:
an epitaxial layer; the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked; wherein, the edge of the first semiconductor layer forms a mesa;
the improvement layer is arranged on one side, away from the light emitting layer, of the second semiconductor layer, and forms ohmic contact with the second semiconductor layer;
the protective layer is arranged on one side, away from the second semiconductor layer, of the improvement layer; the protective layer at least comprises an insulating protective layer;
the isolation layer is arranged on one side, away from the improvement layer, of the insulation protection layer and completely covers the exposed surfaces of the epitaxial layer, the improvement layer and the insulation protection layer;
the anode metal layer is arranged on one side, away from the insulating protection layer, of the isolation layer and penetrates through the insulating protection layer and a first through hole in the thickness of the isolation layer;
and the cathode metal layer is arranged on one side of the isolation layer, which is deviated from the first semiconductor layer, and in a second through hole which penetrates through the thickness of the isolation layer and is connected with the first semiconductor layer.
2. The micro led of claim 1, wherein the protective layer further comprises a conductive protective layer.
3. The micro light-emitting diode of claim 2, wherein the conductive protection layer is disposed between the insulating protection layer and the improvement layer.
4. The micro light-emitting diode of any one of claims 1 to 3, wherein the material of the insulating protective layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.
5. The micro light-emitting diode according to any one of claims 2 or 3, wherein the material of the conductive protection layer comprises at least one of titanium, titanium nitride and indium tin oxide.
6. The micro light-emitting diode of any of claims 1 to 3, wherein the material of the improvement layer comprises at least one of gold, nickel, platinum, palladium, titanium, ruthenium, tantalum, indium tin oxide, and indium zinc oxide.
7. The micro light-emitting diode according to any one of claims 1 to 3, wherein the light-emitting layer is a multiple quantum well light-emitting layer.
8. A method for preparing a micro light-emitting diode is characterized by comprising the following steps:
forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked; forming a mesa at the edge of the first semiconductor layer by an etching process;
forming an improvement layer on one side of the second semiconductor layer, which is far away from the light-emitting layer; the improvement layer and the second semiconductor layer form ohmic contact;
forming a protective layer on one side of the improvement layer, which is far away from the second semiconductor layer; wherein the protective layer comprises at least an insulating protective layer;
forming an isolation layer on one side of the insulation protection layer, which is far away from the improvement layer, on the table top at the edge of the first semiconductor layer and on the side surfaces of the epitaxial layer, the improvement layer and the insulation protection layer;
etching the isolation layer and the insulating protection layer above the improvement layer in a layered manner until the improvement layer is exposed, and forming a first through hole; wherein, the isolating layer and the insulating protection layer adopt different etching selection ratios;
etching the isolation layer on the table top at the edge of the first semiconductor layer until the first semiconductor layer is exposed to form a second through hole;
forming an anode metal layer on one side of the isolation layer, which is far away from the insulating protection layer, and in the first through hole; and forming a cathode metal layer on one side of the isolation layer, which is far away from the edge table-board of the first semiconductor layer, and in the second through hole.
9. The method of claim 8, wherein the protective layer further comprises a conductive protective layer; the forming of the protective layer on the side of the improvement layer away from the second semiconductor layer includes:
forming the conductive protection layer on one side of the improvement layer, which faces away from the second semiconductor layer;
and forming the insulating protection layer on one side of the conductive protection layer, which is far away from the improvement layer.
10. A display screen, comprising: the micro light-emitting diode of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210382288.8A CN114725268A (en) | 2022-04-13 | 2022-04-13 | Miniature light-emitting diode, preparation method and display screen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210382288.8A CN114725268A (en) | 2022-04-13 | 2022-04-13 | Miniature light-emitting diode, preparation method and display screen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114725268A true CN114725268A (en) | 2022-07-08 |
Family
ID=82244019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210382288.8A Pending CN114725268A (en) | 2022-04-13 | 2022-04-13 | Miniature light-emitting diode, preparation method and display screen |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114725268A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916029A (en) * | 2012-10-18 | 2013-02-06 | 北京工业大学 | High-voltage light emitting diode |
| CN208385440U (en) * | 2018-07-18 | 2019-01-15 | 安徽三安光电有限公司 | A kind of light emitting diode |
| CN109755359A (en) * | 2019-01-15 | 2019-05-14 | 江西兆驰半导体有限公司 | A kind of manufacturing method of light-emitting diode chip for backlight unit |
| CN112993112A (en) * | 2021-02-02 | 2021-06-18 | 华灿光电(苏州）有限公司 | Preparation method of light-emitting diode chip |
| CN113659051A (en) * | 2021-07-16 | 2021-11-16 | 厦门三安光电有限公司 | Flip-chip semiconductor light-emitting element, semiconductor light-emitting device and display device |
| CN113903842A (en) * | 2021-09-24 | 2022-01-07 | 厦门三安光电有限公司 | Flip-chip light emitting diode and light emitting device |
-
2022
- 2022-04-13 CN CN202210382288.8A patent/CN114725268A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916029A (en) * | 2012-10-18 | 2013-02-06 | 北京工业大学 | High-voltage light emitting diode |
| CN208385440U (en) * | 2018-07-18 | 2019-01-15 | 安徽三安光电有限公司 | A kind of light emitting diode |
| CN109755359A (en) * | 2019-01-15 | 2019-05-14 | 江西兆驰半导体有限公司 | A kind of manufacturing method of light-emitting diode chip for backlight unit |
| CN112993112A (en) * | 2021-02-02 | 2021-06-18 | 华灿光电(苏州）有限公司 | Preparation method of light-emitting diode chip |
| CN113659051A (en) * | 2021-07-16 | 2021-11-16 | 厦门三安光电有限公司 | Flip-chip semiconductor light-emitting element, semiconductor light-emitting device and display device |
| CN113903842A (en) * | 2021-09-24 | 2022-01-07 | 厦门三安光电有限公司 | Flip-chip light emitting diode and light emitting device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8383438B2 (en) | Method for fabricating InGaAIN light-emitting diodes with a metal substrate | |
| CN108878468B (en) | Display substrate, manufacturing method thereof, display panel and display device | |
| CN103140947B (en) | Group iii nitride semiconductor light-emitting device and manufacture method thereof | |
| WO2016122725A1 (en) | Micro-light emitting diode with metal side mirror | |
| CN1905225A (en) | Nitride-based compound semiconductor light emitting device and method of fabricating the same | |
| US8022430B2 (en) | Nitride-based compound semiconductor light-emitting device | |
| US9024342B2 (en) | Semiconductor light emitting element | |
| WO2008084956A1 (en) | Method of manufacturing a flexible device and method of manufacturing a flexible display | |
| CN102047454A (en) | Light-emitting device and fabricating method thereof | |
| CN100585893C (en) | LED and manufacturing method thereof | |
| CN101084583A (en) | Gan compound semiconductor light emitting element and method of manufacturing the same | |
| CN104022204A (en) | Light-emitting element | |
| EP2257997A1 (en) | Semiconductor light-emitting device with double-sided passivation | |
| CN115498088B (en) | Miniature light-emitting diode and preparation method thereof | |
| US7335519B2 (en) | Method for manufacturing a light-emitting diode | |
| CN110600597A (en) | Micro LED chip, display panel and preparation method of display panel | |
| CN116565103B (en) | Micro LED micro display chip and manufacturing method thereof | |
| KR101690508B1 (en) | Light emitting device | |
| CN114530534A (en) | LED chip and preparation method thereof | |
| JP4170138B2 (en) | Organic electroluminescent device and manufacturing method thereof | |
| US20200403119A1 (en) | Semiconductor light emitting device and display apparatus | |
| CN114725268A (en) | Miniature light-emitting diode, preparation method and display screen | |
| US20200303593A1 (en) | Semiconductor light emitting device and method of manufacturing the same | |
| KR100675202B1 (en) | Vertically structured gan type light emitting diode device and method of manufacturing the same | |
| CN115020440A (en) | Manufacturing method of small-spacing high-brightness LED display screen and LED display screen |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |