CN114725107A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN114725107A CN114725107A CN202210445327.4A CN202210445327A CN114725107A CN 114725107 A CN114725107 A CN 114725107A CN 202210445327 A CN202210445327 A CN 202210445327A CN 114725107 A CN114725107 A CN 114725107A
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- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
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- H10B12/00—Dynamic random access memory [DRAM] devices
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- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
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Abstract
The invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of grooves which are arranged in parallel at intervals in a substrate; forming a word line structure in the groove, wherein the word line structure comprises a conductive layer and a dielectric layer for coating the bottom surface and the side wall of the conductive layer, the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer; and forming a sealing layer, wherein the sealing layer covers the upper surfaces of the conducting layer and the dielectric layer. According to the preparation method of the semiconductor structure, the upper surface of the conducting layer is lower than or flush with the upper surface of the dielectric layer, so that the conducting layer is prevented from being exposed by the dielectric layer to cause electric leakage; moreover, because the dielectric layer is lower than the surface of the substrate, the conducting layer and the dielectric layer can be completely sealed in the substrate after the sealing layer is formed, and the dielectric layer in the word line structure is prevented from being lost by a subsequent etching process.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof.
Background
In a conventional embedded word line structure, a gate oxide layer usually covers the sidewall of a word line trench and is flush with the upper surface of a substrate. In a subsequent cleaning process or a wet etching process, the gate oxide layer is easily damaged, so that a conductive layer in a word line structure is exposed in air, and the performance of a device is seriously influenced.
In order to solve the above problems, the conventional method is to reduce the height of the gate oxide layer after the conductive layer is formed, so that the top surface of the gate oxide layer is flush with the top surface of the conductive layer, and finally, form an isolation layer on the top of the word line structure to isolate the word line structure from the outside. Then, the method has the problem of low process margin, when the height of the gate oxide layer is reduced, the etching precision is difficult to control accurately, the situation that the gate oxide layer is lower than the conducting layer due to over etching is easy to occur, and the gate oxide layer cannot completely cover the surface of the conducting layer.
Disclosure of Invention
Therefore, it is necessary to provide a semiconductor structure and a method for manufacturing the same, aiming at the problems of low process margin and incomplete coverage of the gate oxide layer on the surface of the conductive layer in the conventional method.
One embodiment of the present application discloses a semiconductor structure, comprising: the device comprises a substrate, a first substrate and a second substrate, wherein the substrate is provided with a plurality of grooves which are arranged in parallel at intervals; the word line structure is positioned in the groove and comprises a conductive layer and a dielectric layer for coating the bottom surface and the side wall of the conductive layer, wherein the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer; and the sealing layer covers the upper surfaces of the conducting layer and the dielectric layer.
In the semiconductor structure, the upper surface of the conducting layer is lower than or flush with the upper surface of the dielectric layer, and the dielectric layer can completely separate the conducting layer from an active region in the substrate; the sealing layer covers the upper surfaces of the conducting layer and the dielectric layer, seals the word line structure in the substrate and completely separates the word line structure from the outside, and ensures that the dielectric layer is not damaged in a subsequent wet etching process or a subsequent cleaning process.
In one embodiment, the conductive layer comprises a first conductive layer and a second conductive layer which are sequentially stacked from bottom to top, and the upper surface of the second conductive layer is lower than or flush with the upper surface of the dielectric layer.
In one embodiment, the first conductive layer comprises a metal layer and the second conductive layer comprises a polysilicon layer.
In one embodiment, the sealing layer is located at the upper part of the groove, the upper surface of the sealing layer is flush with the upper surface of the substrate, and the lower surface of the sealing layer is in direct contact with the upper surfaces of the second conducting layer and the dielectric layer.
In one embodiment, the width of the capping layer is equal to the width of the trench.
In one embodiment, the width of the capping layer is greater than the width of the trench.
Above-mentioned semiconductor structure sets up the width that is greater than the slot through the width that will seal the layer, can improve the guard action of seal layer to the word line structure, protects the word line structure inside the substrate better, prevents that the word line structure from being destroyed by the etching gas or the etching liquid in other technologies.
In one embodiment, the dielectric layer comprises a layer of high dielectric constant material and the capping layer comprises a layer of insulating material.
An embodiment of the present application also discloses a method for manufacturing a semiconductor structure, including: providing a substrate; forming a plurality of grooves which are arranged in parallel at intervals in a substrate; forming a word line structure in the groove, wherein the word line structure comprises a conductive layer and a dielectric layer for coating the bottom surface and the side wall of the conductive layer, the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer; and forming a sealing layer, wherein the sealing layer covers the upper surfaces of the conducting layer and the dielectric layer.
According to the preparation method of the semiconductor structure, the upper surface of the conducting layer is lower than or flush with the upper surface of the dielectric layer, so that the conducting layer is prevented from being exposed by the dielectric layer to cause electric leakage; and because the dielectric layer is lower than the surface of the substrate, the conducting layer and the dielectric layer can be completely sealed in the substrate after the sealing layer is formed, and the dielectric layer in the word line structure is prevented from being lost by the subsequent etching process.
In one embodiment, forming a word line structure in a trench includes: forming a dielectric layer on the side wall and the bottom of the groove; forming a first conductive layer in the groove, wherein the upper surface of the first conductive layer is lower than the upper surface of the substrate; reducing the heights of the dielectric layer and the first conductive layer to enable the upper surface of the dielectric layer to be lower than the upper surface of the substrate and higher than the upper surface of the first conductive layer; and forming a second conductive layer on the first conductive layer, wherein the upper surface of the second conductive layer is lower than or flush with the upper surface of the dielectric layer.
According to the preparation method of the semiconductor structure, the height of the first conducting layer and the height of the dielectric layer are reduced, and then the second conducting layer is formed on the first conducting layer, so that the upper surface of the second conducting layer is flush with or lower than the upper surface of the dielectric layer by controlling the height of the second conducting layer, the process margin is improved, and the situation of over-etching is not needed to be worried about.
In one embodiment, the dielectric layer comprises a high dielectric constant material layer, the first conductive layer comprises a metal layer, and the second conductive layer comprises a polysilicon layer.
In one embodiment, forming a dielectric layer on the sidewalls and bottom of the trench includes: forming a dielectric material layer, wherein the dielectric material layer covers the upper surface of the substrate and the side wall and the bottom surface of the groove; and removing the dielectric layer material layer on the upper surface of the substrate.
In one embodiment, forming a first conductive layer in the trench includes: forming a first conductive material layer, wherein the first conductive material layer fills the groove and covers the upper surface of the substrate; and removing the first conductive material layer on the upper surface of the substrate, and reducing the height of the first conductive material layer in the groove until the side wall of part of the dielectric layer is exposed to obtain the first conductive layer.
In one embodiment, reducing the height of the dielectric layer and the first conductive layer comprises: reducing the height of the dielectric layer to enable the upper surface of the dielectric layer to be flush with the upper surface of the first conducting layer; and reducing the height of the first conductive layer to enable the upper surface of the first conductive layer to be lower than the upper surface of the dielectric layer.
In the preparation method of the semiconductor structure, the dielectric layer is etched and the height of the dielectric layer is adjusted in the process of preparing the first conducting layer; after the height of the dielectric layer is determined, the height of the first conducting layer is adjusted and the second conducting layer is prepared, so that the process margin is improved, and the dielectric layer is prevented from being over-etched to expose the conducting layer.
In one embodiment, forming a second conductive layer over the first conductive layer includes: forming a second conductive material layer which covers the substrate, the dielectric layer and the first conductive layer and fills the groove; and removing the second conductive material layer on the upper surface of the substrate, and reducing the height of the second conductive material layer in the groove until the side wall of part of the dielectric layer is exposed to obtain a second conductive layer.
In one embodiment, forming a second conductive layer over the first conductive layer includes: forming a second conductive material layer, wherein the second conductive material layer covers the substrate, the dielectric layer and the first conductive layer and fills the groove; and removing the second conductive material layer on the upper surface of the substrate, and reducing the height of the second conductive material layer in the groove until the upper surface of the second conductive material layer is flush with the upper surface of the dielectric layer to obtain a second conductive layer.
In one embodiment, forming a seal layer comprises: forming a sealing material layer, wherein the sealing material layer covers the substrate, the dielectric layer and the second conductive layer and fills the groove; and removing the sealing material layer on the upper surface of the substrate.
In one embodiment, the layer of sealing material comprises a layer of insulating material.
According to the preparation method of the semiconductor structure, the sealing layer is formed above the dielectric layer and the second conducting layer, so that the conducting layer and the dielectric layer can be completely separated from each other, and the conducting layer is prevented from being exposed due to loss of etching liquid or gas in other processes, and the performance of a device is prevented from being influenced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
FIG. 1 is a block flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIG. 2 is a cross-sectional view of a semiconductor structure after forming a dielectric layer and a first conductive material layer in a trench according to an embodiment of the present disclosure;
FIG. 3 is a cross-sectional view of a semiconductor structure after forming a first conductive layer according to an embodiment of the present application;
FIG. 4 is a cross-sectional view of a semiconductor structure after reducing the height of a dielectric layer in an embodiment of the present application;
FIG. 5 is a cross-sectional view of a semiconductor structure after reducing the height of a first conductive layer in an embodiment of the present application;
FIG. 6 is a cross-sectional view of a semiconductor structure after forming a second conductive layer in an embodiment of the present application;
FIG. 7 is a cross-sectional structure of a semiconductor structure after forming a second conductive layer in another embodiment of the present application;
FIG. 8 is a cross-sectional view of a semiconductor structure after forming a capping layer in accordance with an embodiment of the present application;
FIG. 9 is a cross-sectional view of a semiconductor structure after forming a sealing layer according to another embodiment of the present application;
FIG. 10 is a cross-sectional view of a semiconductor structure after reducing the height of a dielectric layer in another embodiment of the present application;
FIG. 11 is a cross-sectional view of a semiconductor structure after forming a sealing layer in accordance with yet another embodiment of the present application;
FIG. 12 is a cross-sectional view of a semiconductor structure after forming a sealing layer according to yet another embodiment of the present application.
The reference numbers illustrate:
10. a substrate; 11. a trench; 20. a word line structure; 21. a conductive layer; 211. a first conductive layer; 211' a first layer of conductive material; 212. a second conductive layer; 22. a dielectric layer; 30. and (7) a sealing layer.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In describing positional relationships, unless otherwise specified, when an element such as a layer, film or substrate is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may also be present. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.
In a conventional embedded word line structure, a gate oxide layer usually covers the sidewall of a word line trench and is flush with the upper surface of a substrate. In a subsequent cleaning process or a wet etching process, the gate oxide layer is easily damaged, so that a conductive layer in a word line structure is exposed in air, and the performance of a device is seriously influenced. The traditional solution is to reduce the height of the gate oxide layer after the conductive layer is formed in the word line trench, so that the top surface of the gate oxide layer is lower than the upper surface of the substrate and is flush with the top surface of the conductive layer, and finally, an isolation layer is formed on the top of the word line structure to completely isolate the word line structure from the outside. Then, the method has the problem of low process margin, because when the height of the gate oxide layer is reduced, the etching precision is difficult to control accurately, the situation that the gate oxide layer is lower than the conducting layer due to over etching is easy to occur, the gate oxide layer cannot completely cover the side wall of the conducting layer, and the yield of products is influenced.
In order to solve the above problem, as shown in fig. 1, an embodiment of the present application discloses a method for manufacturing a semiconductor structure, including:
s10: providing a substrate;
s20: forming a plurality of grooves which are arranged in parallel at intervals in the substrate;
s30: forming a word line structure in the groove, wherein the word line structure comprises a conductive layer and a dielectric layer wrapping the bottom surface and the side wall of the conductive layer, the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer;
s40: and forming a sealing layer, wherein the sealing layer covers the upper surfaces of the conducting layer and the dielectric layer.
According to the preparation method of the semiconductor structure, the upper surface of the conducting layer is lower than or flush with the upper surface of the dielectric layer, so that the conducting layer is prevented from being exposed by the dielectric layer to cause electric leakage; and because the dielectric layer is lower than the surface of the substrate, the conducting layer and the dielectric layer can be completely sealed in the substrate after the sealing layer is formed, and the dielectric layer in the word line structure is prevented from being lost by the subsequent etching process.
Specifically, the substrate provided in step S10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator substrate.
In step S20, a plurality of trenches are formed in the substrate and spaced apart in parallel, for example, a Self-Aligned double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process may be used to form trenches in the substrate as the word line trenches. In some embodiments, active regions may also be formed between adjacent word line trenches. The active region may include a first source drain region near the surface of the substrate, a second source drain region far from the surface of the substrate, and a channel region between the first source drain region and the second source drain region.
In step S30, referring to fig. 2-7, a word line structure 20 is formed in the trench 11, wherein the word line structure 20 includes a conductive layer 21 and a dielectric layer 22 covering a bottom surface and sidewalls of the conductive layer 21. Specifically, the step of forming the word line structure 20 includes:
s31: forming a dielectric layer 22 on the sidewall and the bottom of the trench 11;
s32: forming a first conductive layer 211 in the trench 11, wherein an upper surface of the first conductive layer 211 is lower than an upper surface of the substrate 10;
s33: reducing the heights of the dielectric layer 22 and the first conductive layer 211 so that the upper surface of the dielectric layer 22 is lower than the upper surface of the substrate 10 and higher than the upper surface of the first conductive layer 211;
s34: a second conductive layer 212 is formed on the first conductive layer 211, and the top surface of the second conductive layer 212 is lower than or flush with the top surface of the dielectric layer 22.
Illustratively, in step S31, the step of forming the dielectric layer 22 includes:
s311: a dielectric material layer is formed covering the upper surface of the substrate 10 and the sidewalls and bottom surface of the trench 11.
Illustratively, the dielectric layer 22 material layer may be a high dielectric constant material layer, such as a silicon oxide layer or a silicon oxynitride layer. The dielectric material layer may be formed to cover the upper surface of the substrate 10 and the sidewalls and bottom surface of the trench 11 by using a chemical vapor deposition process, an atomic layer deposition process, a plasma vapor deposition process, an In-Situ water vapor Generation (ISSG) process, or a Rapid Thermal Oxidation (RTO) process.
S312: the dielectric layer 22 material layer on the upper surface of the substrate 10 is removed.
By way of example, a Chemical Mechanical Polishing (CMP) process or an etching process may be used to remove the dielectric material layer on the upper surface of the substrate 10, expose the upper surface of the substrate 10, and form the dielectric layer 22 covering the sidewalls and the bottom of the trench 11. Wherein the upper surface of the dielectric layer 22 is flush with the upper surface of the substrate 10.
After the dielectric layer 22 is formed, a first conductive layer 211 is formed in the trench 11. In step S32, the step of forming the first conductive layer 211 in the trench 11 includes:
s321: a first conductive material layer 211' is formed to fill the trench 11 and cover the upper surface of the substrate 10, as shown in fig. 2.
Illustratively, the first conductive material layer 211' may be a metal layer having a small resistivity, such as Ge (germanium), W (tungsten), Cu (copper), or Au (gold), for example. As an example, a deposition process may be employed to deposit a metal material in the trench 11 to form a metal layer that fills the trench 11 and covers the upper surface of the substrate 10.
S322: the first conductive material layer 211 'on the upper surface of the substrate 10 is removed, and the height of the first conductive material layer 211' in the trench 11 is reduced until the sidewall of a portion of the dielectric layer 22 is exposed, so as to obtain the first conductive layer 211, as shown in fig. 3.
Illustratively, the first conductive material layer 211 ' may be etched by a plasma etching process to remove the first conductive material layer 211 ' on the upper surface of the substrate 10, and the height of the first conductive material layer 211 ' in the trench 11 is reduced appropriately to expose a portion of the sidewall of the dielectric layer 22. The reason for forming the first conductive layer 211 and exposing a portion of the sidewall on the top of the dielectric layer 22 is to remove the exposed portion of the dielectric layer 22 in a subsequent process, so that the upper surface of the dielectric layer 22 is lower than the upper surface of the substrate 10.
S33: the heights of the dielectric layer 22 and the first conductive layer 211 are lowered so that the upper surface of the dielectric layer 22 is lower than the upper surface of the substrate 10 and higher than the upper surface of the first conductive layer 211. The method comprises the following specific steps:
s331, the height of the dielectric layer 22 is reduced so that the upper surface of the dielectric layer 22 is flush with the upper surface of the first conductive layer 211, as shown in fig. 4.
Illustratively, the exposed dielectric layer 22 may be etched in a horizontal direction by using an anisotropic plasma etching process, and the height of the dielectric layer 22 is reduced so that the upper surface of the dielectric layer 22 is flush with the upper surface of the first conductive layer 211. By etching the dielectric layer 22 by using the anisotropic plasma etching process, the etching direction can be mainly concentrated in the horizontal direction, and the etching of the dielectric layer 22 in the vertical direction is reduced to the maximum extent, so that the dielectric layer 22 is flush with the upper surface of the first conductive layer 211 after being etched.
Optionally, in some other embodiments, a wet etching process may be further used to remove the exposed dielectric layer 22, so as to reduce the height of the dielectric layer 22. In this step, the requirement on the etching accuracy of the dielectric layer 22 is not high, and the upper surface of the dielectric layer 22 is only required to be lowered to be close to the upper surface of the first conductive layer 211. Even if the dielectric layer 22 is excessively etched to be lower than the upper surface of the first conductive layer 211, the quality of the final device is not affected.
S332: the height of the first conductive layer 211 is reduced so that the upper surface of the first conductive layer 211 is lower than the upper surface of the dielectric layer 22, as shown in fig. 5.
For example, the first conductive layer 211 may be etched using a plasma etching process or a wet etching process to lower the first conductive layer 211 to a target height. The target height may be a height value of the first conductive layer 211 preset in the product design, and when the first conductive layer 211 is lowered to the target height, the upper surface of the first conductive layer 211 is lower than the upper surface of the dielectric layer 22, as shown in fig. 5.
In the preparation method of the semiconductor structure, the etching of the dielectric layer 22 is arranged before the height of the first conductive layer 211 is reduced, and the final product quality is not affected even if a certain degree of over-etching occurs in the process of etching the dielectric layer 22, because the step of reducing the height of the first dielectric layer 22 is carried out after the dielectric layer 22 is etched, the dielectric layer 22 can be ensured to cover the side wall of the first conductive layer 211. Compared with a method for etching the dielectric layer after the conductive layer is formed in the traditional process, the method has larger process margin.
In S34, a second conductive layer 212 is formed on the first conductive layer 211, and the top surface of the second conductive layer 212 is lower than or flush with the top surface of the dielectric layer 22, as shown in fig. 6 or 7.
For example, in some embodiments, the step of forming the second conductive layer 212 on the first conductive layer 211 includes:
s341: a second conductive material layer is formed, which covers the substrate 10, the dielectric layer 22 and the first conductive layer 211 and fills the trench 11.
For example, the second conductive material layer may be a material layer with better conductivity, such as a polysilicon layer. Specifically, a second conductive material layer may be deposited on the first conductive layer 211, wherein the second conductive material layer fills the trench 11 and covers the dielectric layer 22, the first conductive layer 211 and the surface of the substrate 10.
S342: the second conductive material layer on the upper surface of the substrate 10 is removed, and the height of the second conductive material layer in the trench 11 is reduced until the sidewall of a portion of the dielectric layer 22 is exposed, so as to obtain a second conductive layer 212, as shown in fig. 6.
For example, the second conductive material layer may be etched back by using a plasma etching process or a wet etching process until a portion of the sidewall of the dielectric layer 22 is exposed, so as to obtain the second conductive layer 212. Wherein the upper surface of second conductive layer 212 is lower than the upper surface of dielectric layer 22.
Optionally, in some other embodiments, the step of forming the second conductive layer 212 on the first conductive layer 211 includes:
s341': forming a second conductive material layer which covers the substrate 10, the dielectric layer 22 and the first conductive layer 211 and fills the trench 11;
and S342': the second conductive material layer on the upper surface of the substrate 10 is removed, and the height of the second conductive material layer in the trench 11 is reduced until the upper surface of the second conductive material layer is flush with the upper surface of the dielectric layer 22, so as to obtain a second conductive layer 212, as shown in fig. 7.
According to the preparation method of the semiconductor structure, after the dielectric layer 22 is formed, the second conductive layer 212 is formed above the first conductive layer 211, so that the process difficulty is reduced on the whole, the process margin is improved, the first conductive layer 211 and the second conductive layer 212 can be ensured to be coated by the dielectric layer 22, and the high-quality word line structure 20 is formed.
In step S40, a capping layer 30 is formed covering the upper surfaces of the conductive layer and the dielectric layer, as shown in fig. 8 or 9. Specifically, the step of forming the sealing layer 30 includes:
s41: a sealing material layer is formed, covering the substrate 10, the dielectric layer 22 and the second conductive layer 212, and filling the trench 11.
Illustratively, the layer of sealing material comprises a layer of insulating material, such as a layer of silicon nitride. An atomic layer deposition process or a chemical vapor deposition process may be used to deposit a sealing material layer on the surface of the resulting structure to cover the substrate 10, the dielectric layer 22, and the second conductive layer 212 and fill the trench 11.
S42: and removing the sealing material layer on the upper surface of the substrate 10 to obtain the sealing layer 30.
Illustratively, the sealing material layer may be etched back by an etching process to remove the sealing material layer from the upper surface of the substrate 10, so that the upper surface of the sealing layer 30 is flush with the upper surface of the substrate 10. When the upper surface of the second conductive layer 212 is lower than the upper surface of the dielectric layer 22, a cross-sectional structure of the semiconductor structure obtained after forming the sealing layer 30 is schematically shown in fig. 8. When the top surface of the second conductive layer 212 is flush with the top surface of the dielectric layer 22, the cross-sectional structure of the semiconductor structure obtained after forming the sealing layer 30 is schematically shown in fig. 9.
In the semiconductor structure prepared by the method, the word line structure 20 is sealed inside the substrate 10 by the sealing layer 30, so that the top end of the dielectric layer 22 is not exposed on the surface of the substrate 10, the dielectric layer 22 is prevented from being lost in other processes, and a good protection effect can be formed on the word line structure 20.
Optionally, in some embodiments, when the height of the dielectric layer 22 is reduced in step S331, the substrate 10 on both sides of the dielectric layer 22 may also be etched to a certain extent, so as to widen the width of the upper portion of the trench 11, and obtain the structure shown in fig. 10.
For example, the process steps of reducing the height of the first conductive layer 211, forming the second conductive layer 212, and forming the sealing layer 30 may refer to the related descriptions in the foregoing embodiments, and are not described herein again. The resulting semiconductor structure is shown in fig. 11 or fig. 12.
In the above method for manufacturing a semiconductor structure, by forming an opening having a large width in the upper portion of trench 11, sealing layer 30 having a larger width can be manufactured. The width of the sealing layer 30 is greater than the width of the trench 11, so that the sealing layer 30 can completely cover the upper surface of the dielectric layer 22 and the upper surface of the conductive layer 21 in the trench 11, and the protection effect of the sealing layer 30 on the word line structure 20 is improved.
As shown in fig. 8, the present application further discloses a semiconductor structure comprising: a substrate 10, wherein the substrate 10 is provided with a plurality of parallel grooves 11 arranged at intervals; the word line structure 20 is positioned in the trench 11, the word line structure 20 comprises a conductive layer 21 and a dielectric layer 22 for coating the bottom surface and the side wall of the conductive layer 21, wherein the upper surface of the dielectric layer 22 is lower than the upper surface of the substrate 10, and the upper surface of the conductive layer 21 is lower than or flush with the upper surface of the dielectric layer 22; and a sealing layer 30 covering the upper surfaces of the conductive layer 21 and the dielectric layer 22.
In the semiconductor structure, the upper surface of the conductive layer 21 is lower than or flush with the upper surface of the dielectric layer 22, so that the dielectric layer 22 can completely separate the conductive layer 21 from other conductive structures, and electric leakage is prevented; in addition, the sealing layer 30 covers the upper surfaces of the conductive layer 21 and the dielectric layer 22, so that the dielectric layer 22 can be isolated from the external environment, and when other processes are performed, the dielectric layer 22 is not damaged, and the word line structure 20 is well protected.
In some embodiments, the conductive layer 21 includes a first conductive layer 211 and a second conductive layer 212 stacked in sequence from bottom to top, and an upper surface of the second conductive layer 212 is lower than or flush with an upper surface of the dielectric layer 22.
Illustratively, the word line structure 20 may be a hybrid gate, and the conductive layer 21 includes two or more conductive materials. Illustratively, as shown in fig. 8, the conductive layer 21 includes a first conductive layer 211 and a second conductive layer 212 stacked in sequence from bottom to top, wherein the first conductive layer 211 may be a metal layer, such as Ge (germanium), W (tungsten), Cu (copper), or Au (gold). The second conductive layer 212 may be a polysilicon layer. The upper surface of second conductive layer 212 is below or flush with the upper surface of dielectric layer 22. Dielectric layer 22 may include, but is not limited to, a layer of high dielectric constant material, such as a silicon dioxide layer.
Optionally, in some embodiments, the conductive layer 21 further includes a metal barrier layer between the first conductive layer 211 and the second conductive layer 212 to separate the first conductive layer 211 from the second conductive layer 212. The metal barrier layer may be, for example, a titanium layer or a titanium nitride layer.
Alternatively, in some other embodiments, the word line structure 20 may be a metal gate. The conductive layer 21 includes a first conductive layer 211 and a metal barrier layer covering the bottom and sidewalls of the first conductive layer 211. The upper surface of the first conductive layer 211 is flush with the upper surface of the metal barrier layer. The metal barrier layer may be, for example, a titanium layer or a titanium nitride layer.
In some embodiments, with continued reference to fig. 8, sealing layer 30 is located on top of trench 11, and the upper surface of sealing layer 30 is flush with the upper surface of substrate 10, and the lower surface of sealing layer 30 is in direct contact with second conductive layer 212 and the upper surface of dielectric layer 22. Illustratively, the capping layer 30 may include, but is not limited to, an insulating material layer, such as a silicon nitride layer, a silicon oxynitride layer, or the like.
In some embodiments, the width of sealing layer 30 is equal to the width of trench 11, as shown in fig. 8 and 9.
In some embodiments, the width of sealing layer 30 is greater than the width of trench 11, as shown in fig. 11 and 12. By setting the width of the sealing layer 30 to be greater than the width of the trench 11, the protective effect of the sealing layer 30 on the word line structure 20 can be improved, the word line structure 20 can be better protected inside the substrate 10, and the word line structure 20 is prevented from being damaged by etching gas or etching liquid in other processes to affect the performance of the device.
The semiconductor structure in any of the embodiments can be applied to a DRAM device, and can improve the yield and stability of the semiconductor device.
The application also discloses a semiconductor device comprising the semiconductor structure in any one of the embodiments. Illustratively, the semiconductor device further includes a transistor element, a capacitance structure, and a bit line structure. The semiconductor device may be, for example, a Dynamic Random Access Memory (DRAM).
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in FIG. 1 may include multiple steps or stages. These steps or phases are not necessarily performed at the same time, but may be performed at different times, and the order of performing these steps or phases is not necessarily sequential, but may be performed alternately or at least partially with other steps or steps among other steps.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (17)
1. A semiconductor structure, comprising:
the device comprises a substrate, a first substrate and a second substrate, wherein the substrate is provided with a plurality of grooves which are arranged in parallel at intervals;
the word line structure is positioned in the groove and comprises a conductive layer and a dielectric layer wrapping the bottom surface and the side wall of the conductive layer, wherein the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer;
and the sealing layer covers the upper surfaces of the conducting layer and the dielectric layer.
2. The semiconductor structure of claim 1, wherein the conductive layer comprises a first conductive layer and a second conductive layer stacked in sequence from bottom to top, and an upper surface of the second conductive layer is lower than or flush with an upper surface of the dielectric layer.
3. The semiconductor structure of claim 2, wherein the first conductive layer comprises a metal layer and the second conductive layer comprises a polysilicon layer.
4. The semiconductor structure of claim 2, wherein the capping layer is located at an upper portion of the trench, an upper surface of the capping layer is flush with an upper surface of the substrate, and a lower surface of the capping layer is in direct contact with the second conductive layer and an upper surface of the dielectric layer.
5. The semiconductor structure of claim 4, wherein a width of the capping layer is equal to a width of the trench.
6. The semiconductor structure of claim 4, wherein a width of the capping layer is greater than a width of the trench.
7. The semiconductor structure of any of claims 2-6, wherein the dielectric layer comprises a layer of high dielectric constant material and the capping layer comprises a layer of insulating material.
8. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of grooves which are arranged in parallel at intervals in the substrate;
forming a word line structure in the groove, wherein the word line structure comprises a conductive layer and a dielectric layer coating the bottom surface and the side wall of the conductive layer, the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer;
and forming a sealing layer, wherein the sealing layer covers the upper surfaces of the conducting layer and the dielectric layer.
9. The method of claim 8, wherein forming a word line structure in the trench comprises:
forming a dielectric layer on the side wall and the bottom of the groove;
forming a first conductive layer in the groove, wherein the upper surface of the first conductive layer is lower than the upper surface of the substrate;
reducing the heights of the dielectric layer and the first conductive layer to enable the upper surface of the dielectric layer to be lower than the upper surface of the substrate and higher than the upper surface of the first conductive layer;
and forming a second conducting layer on the first conducting layer, wherein the upper surface of the second conducting layer is lower than or flush with the upper surface of the dielectric layer.
10. The method of claim 9, wherein the dielectric layer comprises a high-k material layer, the first conductive layer comprises a metal layer, and the second conductive layer comprises a polysilicon layer.
11. The method of claim 9, wherein forming a dielectric layer on sidewalls and bottom of the trench comprises:
forming a dielectric material layer covering the upper surface of the substrate and the side walls and the bottom surface of the groove;
and removing the dielectric layer material layer on the upper surface of the substrate.
12. The method of claim 9, wherein forming a first conductive layer in the trench comprises:
forming a first conductive material layer, wherein the first conductive material layer fills the groove and covers the upper surface of the substrate;
and removing the first conductive material layer on the upper surface of the substrate, and reducing the height of the first conductive material layer in the groove until the side wall of part of the dielectric layer is exposed to obtain the first conductive layer.
13. The method of claim 9, wherein said reducing the height of said dielectric layer and said first conductive layer comprises:
reducing the height of the dielectric layer to enable the upper surface of the dielectric layer to be flush with the upper surface of the first conducting layer;
and reducing the height of the first conducting layer to enable the upper surface of the first conducting layer to be lower than the upper surface of the dielectric layer.
14. The method of claim 9, wherein forming a second conductive layer over the first conductive layer comprises:
forming a second conductive material layer which covers the substrate, the dielectric layer and the first conductive layer and fills the groove;
and removing the second conductive material layer on the upper surface of the substrate, and reducing the height of the second conductive material layer in the groove until the side wall of part of the dielectric layer is exposed to obtain the second conductive layer.
15. The method of claim 9, wherein forming a second conductive layer over the first conductive layer comprises:
forming a second conductive material layer which covers the substrate, the dielectric layer and the first conductive layer and fills the groove;
and removing the second conductive material layer on the upper surface of the substrate, and reducing the height of the second conductive material layer in the groove until the upper surface of the second conductive material layer is flush with the upper surface of the dielectric layer to obtain the second conductive layer.
16. The method of claim 9, wherein the forming the capping layer comprises:
forming a sealing material layer, wherein the sealing material layer covers the substrate, the dielectric layer and the second conductive layer and fills the groove;
and removing the sealing material layer on the upper surface of the substrate.
17. The method of claim 16, wherein the sealing material layer comprises an insulating material layer.
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