CN114710453B - High-broadband low-delay store-and-forward control device and control method thereof - Google Patents
High-broadband low-delay store-and-forward control device and control method thereof Download PDFInfo
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- CN114710453B CN114710453B CN202210261915.2A CN202210261915A CN114710453B CN 114710453 B CN114710453 B CN 114710453B CN 202210261915 A CN202210261915 A CN 202210261915A CN 114710453 B CN114710453 B CN 114710453B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/52—Queue scheduling by attributing bandwidth to queues
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/56—Queue scheduling implementing delay-aware scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
- H04L47/6275—Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
Abstract
The invention discloses a high-broadband low-delay store-and-forward control device and a control method thereof, wherein the device comprises an interface data processing unit, a high-speed memory read-write control unit and a forward control unit; the interface data processing unit is used for carrying out port time sequence conversion, priority classification, frame delimiter insertion and packet loss operation on the physical port; the high-speed memory read-write control unit is used for determining the burst data structure of the high-speed memory, and performing byte interleaving and read-write scheduling on the data packet of the physical port; the forwarding control unit is used for performing interleaved byte recovery, frame delimiter removal and forwarding the data packet to the corresponding physical port. The high-broadband low-delay store-and-forward control device of the invention well improves the bandwidth of the high-speed memory, reduces the port forwarding delay, increases the priority queue control of the data packet, and better adapts to the actual application scene.
Description
Technical Field
The invention belongs to the technical field of electronic information, and particularly relates to a high-broadband low-delay store-and-forward control device and a control method thereof.
Background
In a communication device controlled by multi-port storage forwarding, it is generally required to buffer bursts as much as possible when multi-port data packets burst, which has a higher bandwidth control requirement for a high-speed memory, in the current multi-port forwarding control device, when the bandwidth of the high-speed memory is increased, port forwarding delay is increased, and a compromise scheme is generally adopted to control the bandwidth of the high-speed memory and the port forwarding delay, and priority scheduling is rarely performed on the data packets.
Disclosure of Invention
The invention aims to solve the problem of the existing multiport store-and-forward device and provides a high-broadband low-delay store-and-forward control device and a control method thereof.
The technical scheme of the invention is as follows: the high-broadband low-delay storage forwarding control device comprises an interface data processing unit, a high-speed memory read-write control unit and a forwarding control unit;
the interface data processing unit is used for carrying out port time sequence conversion, priority classification, frame delimiter insertion and packet loss operation on the physical port;
the high-speed memory read-write control unit is used for determining the burst data structure of the high-speed memory, and performing byte interleaving and read-write scheduling on the data packet of the physical port;
the forwarding control unit is used for performing interleaved byte recovery, frame delimiter removal and forwarding the data packet to the corresponding physical port.
Further, the interface data processing unit comprises an interface processing module, a priority scheduling module, a frame delimiter inserting module and a packet-level queue memory packet loss control module;
the interface processing module is used for performing time sequence conversion on the data packet of the physical port, deleting and adding bytes corresponding to the physical port, and converting the bytes into time sequences required by other modules; according to the type of the physical port, the time sequence required by other modules is converted into a corresponding physical port time sequence;
the priority scheduling module is used for classifying the priorities of the data packets of the physical ports;
the frame delimiter insertion module is used for respectively adding frame delimiters at the head and the tail of the data packet, and performing byte escape on the data serving as the frame delimiters in the data packet to escape the data as non-delimiters;
and the packet loss control module of the packet level queue memory is used for carrying out whole packet loss when the memory space of the packet level queue memory reaches a threshold value.
Further, the high-speed memory read-write control unit comprises a byte inserting parameter configuration table module, a multi-channel data byte inserting module and a high-speed memory read-write scheduling module;
the byte interleaving parameter configuration table module is used for configuring the data bit width of the high-speed memory, the meaning of overhead byte bit width and byte bit width according to the number of the physical ports, calculating the bit number a of any physical port, the interleaving effective byte number b and the burst transmission data bit width c according to the high-speed memory, and determining the burst data structure of the high-speed memory according to the bit number a of any physical port, the interleaving effective byte number b and the burst transmission data bit width c;
the multi-channel data byte inserting module is used for checking whether a data packet exists in a packet-level queue memory in the interface data processing unit, if so, inserting the data into a data structure of the high-speed memory according to the physical port sequence, otherwise, inserting the data into the data structure of the high-speed memory in a bit supplementing mode;
the high-speed memory read-write scheduling module is used for circularly carrying out continuous write operation and continuous read operation.
Further, the forwarding control unit comprises a multi-channel interleaved byte recovery module, a frame delimiter removal module, a physical port forwarding table module and a forwarding control module;
the multichannel interleaved byte recovery module is used for recovering the data packets read out from the high-speed memory according to the physical port sequence;
the frame delimiter removing module is used for removing frame delimiters of the recovered data packet;
the physical port forwarding table module is used for static learning table items and dynamic learning table items;
and the forwarding control module is used for forwarding the data packet with the frame delimiter removed to the corresponding physical port according to the table entry.
Further, the physical port forwarding table module performs a specific method of dynamically learning table entries, which comprises the following steps: analyzing the source MAC address of the data packet, writing the source MAC address and the physical port into an item which takes the source MAC address as an address, updating an aging timer of the item, and deleting the corresponding item when the updated aging timer is overtime.
Further, in the forwarding control module, the specific method for forwarding the data packet with the frame delimiter removed to the corresponding physical port is as follows: extracting a destination MAC address of a data packet, inquiring a physical port forwarding table according to the destination MAC address to obtain corresponding data, analyzing a physical port number, and forwarding the corresponding data to the analyzed corresponding physical port.
The beneficial effects of the invention are as follows: the high-broadband low-delay store-and-forward control device of the invention well improves the bandwidth of the high-speed memory, reduces the port forwarding delay, increases the priority queue control of the data packet, and better adapts to the actual application scene.
Based on the system, the invention also provides a high-broadband low-delay store-and-forward control method, which comprises the following steps:
s1: performing port time sequence conversion, priority classification, frame delimiter insertion and packet loss operation on data of a physical port by using an interface data processing unit;
s2: performing byte insertion and read-write scheduling on the data packet processed by the interface data processing unit by utilizing the read-write control unit of the high-speed memory;
s3: and performing byte interleaved recovery, frame delimiter removal and forwarding control on the data packet processed by the high-speed memory read-write control unit by using the forwarding control unit.
Further, step S1 comprises the sub-steps of:
s11: according to the type of the physical port, utilizing an interface processing module to perform time sequence conversion on the data packet of the physical port;
s12: the priority scheduling module is used for extracting priority information of the data packets after time sequence conversion, generating a priority queue, storing the data packets in a corresponding packet queue memory according to the priority queue, and sequentially scheduling the data packets of the physical ports through the priority queue;
s13: and inserting frame delimiters from head to tail in the scheduled data packets by using a frame delimiter inserting module, storing the frame delimiters in a packet-level queue memory, and discarding the whole packets by using a packet-level queue memory packet loss control module when the storage space of the packet-level queue memory reaches a threshold value.
Further, step S2 comprises the sub-steps of:
s21: according to the number of the physical ports, a byte interleaving parameter configuration table is configured by utilizing a byte interleaving parameter configuration table module;
s22: performing byte interleaving on the data packet processed by the interface data processing unit according to the byte interleaving parameter configuration table;
s23: and uniformly scheduling the read operation and the write operation by using a read-write scheduling module of the high-speed memory.
Further, step S3 comprises the sub-steps of:
s31: performing interleaved byte recovery on the data packets read out from the high-speed memory by utilizing a multichannel interleaved byte recovery module to obtain data packets of a plurality of physical ports;
s32: removing frame delimiters from the recovered data packets by using a frame delimiter removing module;
s33: determining a physical port forwarding table by using a physical port forwarding table module;
s34: and inquiring a physical port forwarding table according to the destination MAC address of the data packet with the frame delimiter removed to obtain corresponding data, analyzing the physical port number, and forwarding the corresponding data to the analyzed corresponding physical port.
The beneficial effects of the invention are as follows:
(1) The invention can realize the functions of data packet priority scheduling and data packet burst storage forwarding of a plurality of physical channels, and the data packets of all the channels are stored in the high-speed memory for reading out for forwarding control after being processed in parallel, thereby providing higher bandwidth and lower delay, providing the data packet priority scheduling function and being better adapted to the actual application scene;
(2) The method supports a plurality of physical ports, can determine the number of the ports to be used according to actual application conditions, and has strong applicability;
(3) The priority of various data packets is supported, and a priority queue is configured according to the current supported service condition by adopting a scheduling mode of the priority queue;
(4) The data packets of a plurality of physical channels are written into the high-speed memory in parallel in a byte inserting mode, the opportunities of writing the data packets of each channel into the high-speed memory are equal and uniform, and the forwarding delay among ports can be reduced to a great extent;
(5) The frame delimiter and byte inserting mode is adopted to make the data of several physical ports uniformly written into the high-speed memory and uniformly read out from the high-speed memory, so that the scheduling control of high-speed memory for reading and writing data of several physical ports can be simplified.
Drawings
FIG. 1 is a block diagram of a high-bandwidth low-latency store-and-forward control device;
FIG. 2 is a flow chart of a high-bandwidth low-latency store-and-forward control method;
FIG. 3 is a schematic diagram of enqueued packet priority;
FIG. 4 is a diagram of dequeuing priority after queue reorganization;
fig. 5 is a data structure diagram of one burst of the high-speed memory.
Detailed Description
Embodiments of the present invention are further described below with reference to the accompanying drawings.
As shown in FIG. 1, the invention provides a high-broadband low-delay store-and-forward control device, which comprises an interface data processing unit, a high-speed memory read-write control unit and a forward control unit;
the interface data processing unit is used for carrying out port time sequence conversion, priority classification, frame delimiter insertion and packet loss operation on the physical port;
the high-speed memory read-write control unit is used for determining the burst data structure of the high-speed memory, and performing byte interleaving and read-write scheduling on the data packet of the physical port;
the forwarding control unit is used for performing interleaved byte recovery, frame delimiter removal and forwarding the data packet to the corresponding physical port.
In the embodiment of the invention, the interface data processing unit comprises an interface processing module, a priority scheduling module, a frame delimiter inserting module and a packet-level queue memory packet loss control module; there are n interface data processing units for n physical ports.
The interface processing module is used for performing time sequence conversion on the data packet of the physical port, deleting and adding bytes corresponding to the physical port, and converting the bytes into time sequences required by other modules; according to the type of the physical port, the time sequence required by other modules is converted into a corresponding physical port time sequence;
the priority scheduling module is used for classifying the priorities of the data packets of the physical ports;
the number and division of the priorities can be processed according to the practical application situation, and the 8 priorities are used for illustration, and are respectively 0-7, and the smaller the numerical value is, the higher the priority is. Each priority corresponds to a packet level queue memory, the data packets are written into the corresponding packet level queue memory, priority information is stored in the priority queue, information with higher priority in the queue is read out from the queue, and fig. 3 and fig. 4 illustrate the priority of the enqueued data packets and the priority of dequeuing after the queue is reorganized.
The priority queue always uses the enqueuing priority information to refresh the queue order, 8 times of priority dequeuing or enqueuing is defined as a cycle, when the dequeuing is completed for 3 times, the queue priority is not refreshed in the next enqueuing cycle, and when the enqueuing cycle is completed, the enqueuing order is started, so that the data packet with lower priority can have the opportunity of transmission. Of course, the window time of the low priority transmission can be configured according to the actual application situation.
The frame delimiter insertion module is used for respectively adding frame delimiters at the head and the tail of the data packet, and performing byte escape on the data serving as the frame delimiters in the data packet to escape the data as non-delimiters;
the frame delimiter insertion module is responsible for separating the data packets by using frame delimiters, so that the frame can be conveniently and quickly fixed when the data packets of the following multiple ports are inserted into and read from the high-speed memory, and an additional frame delimiter indication bit is not required to be stored in the high-speed memory, thereby reducing the read-write bandwidth consumption of the high-speed memory and increasing the effective bandwidth of the data packets;
and the packet loss control module of the packet level queue memory is used for carrying out whole packet loss when the memory space of the packet level queue memory reaches a threshold value.
The packet-level queue memory packet loss control module is responsible for back-pressing the packet-level queue memory when the high-speed memory is about to be fully written when the burst flow of the data packets of each port is large, and performing packet loss operation when the storage space of the packet-level queue memory is about to be fully filled.
In the embodiment of the invention, the read-write control unit of the high-speed memory comprises a byte inserting parameter configuration table module, a multi-channel data byte inserting module and a read-write scheduling module of the high-speed memory;
the byte interleaving parameter configuration table module is used for configuring the data bit width of the high-speed memory, the meaning of overhead byte bit width and byte bit width according to the number of the physical ports, calculating the bit number a of any physical port, the interleaving effective byte number b and the burst transmission data bit width c according to the high-speed memory, and determining the burst data structure of the high-speed memory according to the bit number a of any physical port, the interleaving effective byte number b and the burst transmission data bit width c;
the bit number a, the number b of the interleaved effective bytes and the data bit width c of burst transmission of any physical port have the following relation:
2^a＝n；(a+`b)/8+`b＝c； the symbols represent rounding down, e.g. +.>
Taking a certain type of high-speed memory as an example, the length of one burst is 8, namely 128 bits (16 bytes), and the number of physical ports is 8, which is described as follows: 2^3 =8, i.e. a=3; (16+ ' b)/8+ ' b=16, ' b≡ 13.88888;i.e. b=13. Based on the calculated parameters, a data structure of one burst of the high-speed memory can be obtained, as shown in fig. 5.
The port order corresponding to Byte13-Byte0 is cycled according to the port number order indicated by Byte14 and Bit15-Bite13 of Byte13, such as port number 000, the port order corresponding to Byte13-Byte0 is 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, if the port number is 010, the port order corresponding to Byte13-Byte0 is 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, and if the corresponding port has no data, the next port with data will be shifted forward by the patch.
For example: if there is data from all 8 physical ports at this time, then Byte14 and Byte13 have Bit15-Bit 13 of 000, indicating Byte12 as one Byte of port 0, and the subsequent Byte11-Byte0 ports 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, and Byte14 and Byte13 have Bit12-Bit 0 of 1111111111, respectively.
For another example: if only ports 2, 4, 7 have data at this time, then Bit15-Bit 13 of Byte14 and Byte13 is 010, indicating that Byte12 is one Byte of port 2, and the subsequent Byte11-Byte0 is ports 4, 7, 2, and Bit12-Bit 0 of Byte14 and Byte13 is 1010010010100, respectively.
The multi-channel data byte inserting module is used for checking whether a data packet exists in a packet-level queue memory in the interface data processing unit, if so, inserting the data into a data structure of the high-speed memory according to the physical port sequence, otherwise, inserting the data into the data structure of the high-speed memory in a bit supplementing mode;
if it is not empty, the data is interleaved into the data structure written into the high-speed memory according to port order 0-7, and if 8 ports all have data, the 13Byte structure is interleaved sequentially according to port order 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4. If only ports 2, 4, 7 have data to come, then the 13Byte structure is interleaved sequentially with ports 2, 4, 7, 2 in order of ports.
The high-speed memory read-write scheduling module is used for circularly carrying out continuous write operation and continuous read operation.
Because the data written into the high-speed memory is interleaved by all port bytes, and because frame delimiters are added between data packets, the problem of data packet boundaries is not needed to be considered, only the scheduling between reading and writing is needed to be considered simply, in order to increase the bandwidth of the high-speed memory, a continuous writing and continuous reading mode is adopted, a uniform reading and writing scheduling mode is adopted, the parameter m is set, the data are continuously written for m times, then continuously read for m times, and the reading and writing are sequentially and circularly scheduled.
In the embodiment of the invention, the forwarding control unit comprises a multi-channel interleaved byte recovery module, a frame delimiter removal module, a physical port forwarding table module and a forwarding control module;
the multichannel interleaved byte recovery module is used for recovering the data packets read out from the high-speed memory according to the physical port sequence;
for example: if the data read out from the high-speed memory are Bit15-Bit 13 of Byte14 and Byte13 is 000 and Bit12-Bit 0 is 1111111111111, it indicates that Byte12-Byte0 is ports 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, respectively.
Also for example: if Bit15-Bit 13 of data Byte14 and Byte13 read out from the high-speed memory is 010 and Bit12-Bit 0 is 1010010010100, then it indicates that Byte12-Byte0 is ports 2, 4, 7, 2, respectively.
And after determining the port sequence corresponding to the interleaved bytes in the read data of the high-speed memory, respectively recovering the data packets according to the ports.
The frame delimiter removing module is used for removing frame delimiters of the recovered data packet;
after receiving the first frame delimiter, the data packet is considered to be started, and the frame delimiter existing in the data is changed into the data with an escape mark through escape operation, so that after the two types of data are detected in the data, the data are converted into the original data, and after one frame delimiter is received, the data packet is considered to be ended.
The physical port forwarding table module is used for static learning table items and dynamic learning table items;
and the forwarding control module is used for forwarding the data packet with the frame delimiter removed to the corresponding physical port according to the table entry.
In the embodiment of the invention, the physical port forwarding table module performs the specific method of dynamically learning the table entry: analyzing the source MAC address of the data packet, writing the source MAC address and the physical port into an item which takes the source MAC address as an address, updating an aging timer of the item, and deleting the corresponding item when the updated aging timer is overtime.
The physical port forwarding table in the invention has relatively simple function, uses the destination MAC address as the address of the table, and the data part adopts the form of the destination MAC address plus the port number. The table can automatically learn the table entry, the data packet is received through the physical port, the source MAC address is analyzed, the source MAC address and the physical port are written into the table entry taking the source MAC address as the address, the aging timer of the table entry is updated, and when the aging timer of the table entry is overtime, the corresponding table entry is automatically deleted. The table can also be manually written into the table entry, the manual writing is called static table entry, the automatic learning is called dynamic table entry, the static table entry cannot be aged, and the table can always exist unless the table is actively deleted.
In the embodiment of the invention, in the forwarding control module, a specific method for forwarding the data packet with the frame delimiter removed to the corresponding physical port is as follows: extracting a destination MAC address of a data packet, inquiring a physical port forwarding table according to the destination MAC address to obtain corresponding data, analyzing a physical port number, and forwarding the corresponding data to the analyzed corresponding physical port.
The forwarding control module is responsible for determining to which physical port the data packet with the frame delimiter removed should be forwarded.
Based on the above system, the invention also provides a high-broadband low-delay store-and-forward control method, as shown in fig. 2, comprising the following steps:
s1: performing port time sequence conversion, priority classification, frame delimiter insertion and packet loss operation on data of a physical port by using an interface data processing unit;
s2: performing byte insertion and read-write scheduling on the data packet processed by the interface data processing unit by utilizing the read-write control unit of the high-speed memory;
s3: and performing byte interleaved recovery, frame delimiter removal and forwarding control on the data packet processed by the high-speed memory read-write control unit by using the forwarding control unit.
In an embodiment of the present invention, step S1 comprises the following sub-steps:
s11: according to the type of the physical port, utilizing an interface processing module to perform time sequence conversion on the data packet of the physical port;
s12: the priority scheduling module is used for extracting priority information of the data packets after time sequence conversion, generating a priority queue, storing the data packets in a corresponding packet queue memory according to the priority queue, and sequentially scheduling the data packets of the physical ports through the priority queue;
s13: and inserting frame delimiters from head to tail in the scheduled data packets by using a frame delimiter inserting module, storing the frame delimiters in a packet-level queue memory, and discarding the whole packets by using a packet-level queue memory packet loss control module when the storage space of the packet-level queue memory reaches a threshold value.
The storage in the package-level queue memory can be read by a read-write control unit of the high-speed memory, and when the high-speed memory is fully written, back-pressure package losing processing can be performed at the package-level queue memory.
In an embodiment of the present invention, step S2 comprises the sub-steps of:
s21: according to the number of the physical ports, a byte interleaving parameter configuration table is configured by utilizing a byte interleaving parameter configuration table module;
s22: performing byte interleaving on the data packet processed by the interface data processing unit according to the byte interleaving parameter configuration table;
s23: and uniformly scheduling the read operation and the write operation by using a read-write scheduling module of the high-speed memory.
In an embodiment of the present invention, step S3 comprises the sub-steps of:
s31: performing interleaved byte recovery on the data packets read out from the high-speed memory by utilizing a multichannel interleaved byte recovery module to obtain data packets of a plurality of physical ports;
s32: removing frame delimiters from the recovered data packets by using a frame delimiter removing module;
s33: determining a physical port forwarding table by using a physical port forwarding table module;
s34: and inquiring a physical port forwarding table according to the destination MAC address of the data packet with the frame delimiter removed to obtain corresponding data, analyzing the physical port number, and forwarding the corresponding data to the analyzed corresponding physical port.
The beneficial effects of the invention are as follows:
(1) The high-broadband low-delay store-and-forward control device of the invention well improves the bandwidth of the high-speed memory, reduces the port forwarding delay, increases the priority queue control of the data packet, and better adapts to the actual application scene.
(2) The invention can realize the functions of data packet priority scheduling and data packet burst storage forwarding of a plurality of physical channels, and the data packets of all the channels are stored in the high-speed memory for reading out for forwarding control after being processed in parallel, thereby providing higher bandwidth and lower delay, providing the data packet priority scheduling function and being better adapted to the actual application scene;
(3) The method supports a plurality of physical ports, can determine the number of the ports to be used according to actual application conditions, and has strong applicability;
(4) The priority of various data packets is supported, and a priority queue is configured according to the current supported service condition by adopting a scheduling mode of the priority queue;
(5) The data packets of a plurality of physical channels are written into the high-speed memory in parallel in a byte inserting mode, the opportunities of writing the data packets of each channel into the high-speed memory are equal and uniform, and the forwarding delay among ports can be reduced to a great extent;
(6) The frame delimiter and byte inserting mode is adopted to make the data of several physical ports uniformly written into the high-speed memory and uniformly read out from the high-speed memory, so that the scheduling control of high-speed memory for reading and writing data of several physical ports can be simplified.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (4)
1. The high-broadband low-delay storage forwarding control device is characterized by comprising an interface data processing unit, a high-speed memory read-write control unit and a forwarding control unit;
the interface data processing unit is used for carrying out port time sequence conversion, priority classification, frame delimiter insertion and packet loss operation on the physical port;
the high-speed memory read-write control unit is used for determining the burst data structure of the high-speed memory, and performing byte insertion and read-write scheduling on the data packet of the physical port;
the forwarding control unit is used for performing interleaved byte recovery, frame delimiter removal and forwarding the data packet to a corresponding physical port;
the interface data processing unit comprises an interface processing module, a priority scheduling module, a frame delimiter inserting module and a packet-level queue memory packet loss control module;
the interface processing module is used for performing time sequence conversion on the data packet of the physical port, deleting and adding bytes corresponding to the physical port, and converting the bytes into time sequences required by other modules; according to the type of the physical port, the time sequence required by other modules is converted into a corresponding physical port time sequence;
the priority scheduling module is used for classifying the priority of the data packet of the physical port;
the frame delimiter insertion module is used for respectively adding frame delimiters at the head and the tail of the data packet, and performing byte escape on the data serving as the frame delimiters in the data packet to escape the data as non-delimiters;
the packet-level queue memory packet loss control module is used for performing whole packet loss when the memory space of the packet-level queue memory reaches a threshold value;
the high-speed memory read-write control unit comprises a byte inserting parameter configuration table module, a multichannel data byte inserting module and a high-speed memory read-write scheduling module;
the byte-interleaved parameter configuration table module is used for configuring the data bit width of the high-speed memory, the meaning of the overhead byte bit width and the byte bit width according to the number of the physical ports, calculating the bit number a of any physical port, the interleaved effective byte number b and the burst-transmitted data bit width c according to the high-speed memory, and determining the burst data structure of the high-speed memory according to the bit number a of any physical port, the interleaved effective byte number b and the burst-transmitted data bit width c;
the multi-channel data byte inserting module is used for checking whether a data packet exists in a packet-level queue memory in the interface data processing unit, if so, inserting the data into a data structure of the high-speed memory according to the physical port sequence, otherwise, inserting the data into the data structure of the high-speed memory in a bit-supplementing mode;
the high-speed memory read-write scheduling module is used for circularly performing continuous write operation and continuous read operation;
the forwarding control unit comprises a multi-channel interleaved byte recovery module, a frame delimiter removal module, a physical port forwarding table module and a forwarding control module;
the multi-channel interleaved byte recovery module is used for recovering the data packets read out from the high-speed memory according to the physical port sequence;
the frame delimiter removing module is used for removing frame delimiters of the recovered data packet;
the physical port forwarding table module is used for static learning table items and dynamic learning table items;
and the forwarding control module is used for forwarding the data packet with the frame delimiter removed to a corresponding physical port according to the table entry.
2. The high-broadband low-delay store-and-forward control device according to claim 1, wherein the specific method for the physical port forwarding table module to dynamically learn table entries is as follows: analyzing the source MAC address of the data packet, writing the source MAC address and the physical port into an item which takes the source MAC address as an address, updating an aging timer of the item, and deleting the corresponding item when the updated aging timer is overtime.
3. The high-broadband low-latency store-and-forward control device according to claim 1, wherein the specific method for forwarding the data packet from which the frame delimiter is removed to the corresponding physical port in the forwarding control module is as follows: extracting a destination MAC address of a data packet, inquiring a physical port forwarding table according to the destination MAC address to obtain corresponding data, analyzing a physical port number, and forwarding the corresponding data to the analyzed corresponding physical port.
4. The high-broadband low-delay store-and-forward control method is characterized by comprising the following steps of:
s1: performing port time sequence conversion, priority classification, frame delimiter insertion and packet loss operation on data of a physical port by using an interface data processing unit;
s2: performing byte insertion and read-write scheduling on the data packet processed by the interface data processing unit by utilizing the read-write control unit of the high-speed memory;
s3: performing byte interleaved recovery, frame delimiter removal and forwarding control on the data packet processed by the high-speed memory read-write control unit by using the forwarding control unit;
said step S1 comprises the sub-steps of:
s11: according to the type of the physical port, utilizing an interface processing module to perform time sequence conversion on the data packet of the physical port;
s12: the priority scheduling module is used for extracting priority information of the data packets after time sequence conversion, generating a priority queue, storing the data packets in a corresponding packet queue memory according to the priority queue, and sequentially scheduling the data packets of the physical ports through the priority queue;
s13: the frame delimiter inserting module is used for inserting frame delimiters from head to tail of the scheduled data packets, the frame delimiters are stored in the packet-level queue memory, and when the storage space of the packet-level queue memory reaches a threshold value, the packet-level queue memory packet loss control module is used for carrying out whole packet discarding;
said step S2 comprises the sub-steps of:
s21: according to the number of the physical ports, a byte interleaving parameter configuration table is configured by utilizing a byte interleaving parameter configuration table module;
s22: performing byte interleaving on the data packet processed by the interface data processing unit according to the byte interleaving parameter configuration table;
s23: uniformly scheduling the read operation and the write operation by utilizing a read-write scheduling module of the high-speed memory;
said step S3 comprises the sub-steps of:
s31: performing interleaved byte recovery on the data packets read out from the high-speed memory by utilizing a multichannel interleaved byte recovery module to obtain data packets of a plurality of physical ports;
s32: removing frame delimiters from the recovered data packets by using a frame delimiter removing module;
s33: determining a physical port forwarding table by using a physical port forwarding table module;
s34: and inquiring a physical port forwarding table according to the destination MAC address of the data packet with the frame delimiter removed to obtain corresponding data, analyzing the physical port number, and forwarding the corresponding data to the analyzed corresponding physical port.
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