CN114710142A - High-frequency signal peak value detection circuit - Google Patents
High-frequency signal peak value detection circuit Download PDFInfo
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- CN114710142A CN114710142A CN202210316705.9A CN202210316705A CN114710142A CN 114710142 A CN114710142 A CN 114710142A CN 202210316705 A CN202210316705 A CN 202210316705A CN 114710142 A CN114710142 A CN 114710142A
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- 238000005259 measurement Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1532—Peak detectors
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Abstract
The invention discloses a high-frequency signal peak value detection circuit which comprises an operational amplifier U1A, an operational amplifier U1B, a triode Q1 and an MOSFET. The peak detection circuit of the traditional low-frequency circuit is improved, and 1) the operational amplifier U1A and the diodes D1 and D2 are structurally matched, so that the performance requirement on the device is reduced, and the cost is saved; 2) the current is amplified through the triode, so that the charging speed of the capacitor is increased, and the detection rate of the system is increased; 3) the diode D6 is added and a reverse loop is provided, so that the capacitor is fully protected, and the safety and the stability of the system are improved; 4) through the discharge circuit, the capacitor is discharged quickly when the low-voltage peak value is detected, and the accuracy of system detection is improved.
Description
Technical Field
The invention relates to a peak detection circuit, in particular to a peak detection circuit for high-frequency signals in an ultrasonic processing process.
Background
In the ultrasonic processing process, the electrical behavior characteristic of the piezoelectric transducer changes along with the change of the radiation acoustic impedance of the front cover plate, so that the resonant frequency of the piezoelectric transducer can drift, and the system processing performance is greatly reduced. Therefore, it is necessary to perform the real-time tracking of the resonant frequency during the machining process, which not only can realize the high efficiency of the machining system, but also can ensure the safety performance.
An important basis for distinguishing the positive and negative resonant frequency points and judging the frequency tracking condition of the actual processing system in the resonant frequency tracking is the peak value of the current and the voltage at the two ends of the transducer. Common detection methods for detecting signal peaks include an analog peak detection method and a digital peak detection method: the analog peak detection method is usually used by a peak holding circuit, the operational amplifier is not subjected to necessary structural compensation, the performance requirement on the operational amplifier is high, the measurement speed mainly depends on the performance of the operational amplifier, the design cost is high, the method is not suitable for detecting high-frequency signals, and in addition, a discharge loop is not well designed, so that the detection of the peak value when the amplitude of the signal is reduced cannot be detected. Digital peak detection methods generally use a high-speed ADC to directly sample a pulse signal and then perform data processing with a controller to obtain a peak value. The circuit structure is simple, but is limited by sampling time intervals, the requirement on the smoothness of a peak part of a pulse signal is high, if the peak part of the pulse is too steep, the situation that data near the peak can be collected by the ADC is difficult to ensure, and meanwhile, the requirement on the sampling speed of the ADC is high.
The peak detection circuit designed by Lecong and other people of Donghua theory of technology university mainly comprises four parts of a preposed main amplifier, a discriminator circuit, a control circuit and a peak holding circuit. The detected signal is amplified and shaped by the main amplifier, the change of the pulse amplitude is compensated, the noise is removed by the discrimination circuit, the signal time sequence is detected, and finally the analog switch and the ADC are controlled by the control circuit according to the time sequence of the discrimination circuit, so that the task of peak value detection is completed.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a peak value detection circuit for a high-frequency signal in an ultrasonic processing process.
The invention comprises an operational amplifier U1A, an operational amplifier U1B, a triode Q1 and a MOSFET.
The 2 pin of the two-port pin header P2 is grounded, and the 1 pin is connected with the input signal to be detected; one end of the resistor R11 is grounded, and the other end is connected with a pin 1 of the two-port pin header P2; one end of the resistor R10 is connected with the other end of the resistor R11, and the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U1A and the cathode of the diode D2.
The anode of the diode D2 is connected with one end of the resistor R1; the other end of the resistor R1 is connected with one end of a resistor R2, the other end of the resistor R2 is connected with the anode of a diode D2, the fixed end of a slide rheostat R7 and the inverting input end of an operational amplifier U1A, the sliding end of the slide rheostat R7 is connected with one end of a resistor R6, and the other end of the resistor R6 is connected with a-12V power supply.
The cathode of the diode D2 is connected with the output end of the operational amplifier U1A and one end of the resistor R8; the other end of the resistor R8 is connected with the cathode of the diode D3 and the base of the triode Q1, the collector of the triode Q1 is connected with a +12V power supply through a resistor R3, and the emitter of the triode Q1 is respectively connected with the anode of the diode D4, the anode of the diode D5, the cathode of the diode D7 and one end of the resistor R14.
The cathode of the diode D4 is connected with the anode of the diode D3, the anode of the diode D7 is connected with one end of the resistor R17, and the other ends of the resistor R17 and the resistor R14 are grounded; the cathode of the diode D5 is connected to one end of the resistor R4 and the anode of the diode D6, the anode of the diode D6 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the capacitor C1, one end of the resistor R16, one end of the resistor R13 and the non-inverting input terminal of the operational amplifier U1B, the inverting input terminal of the operational amplifier U1A is connected to one end of the resistor R5, the other end of the resistor R4 and the other end of the resistor R5 are connected to the output terminal of the operational amplifier U1B, the output terminal of the operational amplifier U1B is connected to pin 1 of the two-port pin bank P1 through the resistor R9, and pin 2 of the two-port pin bank P1 is grounded.
The other end of the capacitor C1 and the other end of the resistor R16 are grounded, the other end of the resistor R13 is connected with the drain electrode of the MOSFET, the grid electrode of the MOSFET is grounded, the source electrode of the MOSFET is connected with one end of the resistor R15, the other end of the resistor R15, one end of the resistor R18 is connected with one end of the capacitor C2, the other end of the capacitor C2 and one end of the resistor R19 are connected with the 1 pin of the dual-port pin bank P3, the 2 pin of the dual-port pin bank P3 is grounded, and the other end of the resistor R19 is grounded.
A signal to be detected is input by a two-port pin header P2, when a voltage signal rises, a diode D2 is cut off, a diode D1 is conducted, and an operational amplifier U1A forms a voltage follower output; the diodes D5 and D6 are conducted, the small current output by the operational amplifier U1A drives the triode Q1 to amplify the current, so that the capacitor C1 is charged quickly, the electric quantity of the capacitor C1 is discharged slowly through a loop formed by the capacitor C1 and the resistor R16, and finally the operational amplifier U1B outputs the amplitude of the signal to be detected; when the next signal to be measured comes, the actual operating point of the operational amplifier U1A is limited to be near the peak value of the signal to be measured due to the high potential generated at the output end of the operational amplifier U1b, the voltage is divided by the resistor R1 and the voltage drop is conducted by the D2.
The invention has the beneficial effects that: the peak detection circuit of the traditional low-frequency circuit is improved, and 1) the operational amplifier U1A and the diodes D1 and D2 are structurally matched, so that the performance requirement on the device is reduced, and the cost is saved; 2) the current is amplified through the triode, so that the charging speed of the capacitor is increased, and the detection rate of the system is increased; 3) the diode D6 is added and a reverse loop is provided, so that the capacitor is fully protected, and the safety and the stability of the system are improved; 4) through the discharge circuit, the capacitor is discharged quickly when the low-voltage peak value is detected, and the accuracy of system detection is improved. In summary, the invention uses the resonant frequency tracking technology in ultrasonic processing as the background, is suitable for peak detection of high-frequency signals in the ultrasonic processing process, and has strong system stability and high measurement precision.
Drawings
Fig. 1 shows a peak detection core circuit in the prior art.
Fig. 2 is a fast high-precision peak detection circuit.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the main principle of the circuit for measuring the peak value is that when the voltage of the input terminal increases, the voltage of the output terminal increases through a voltage follower formed by an operational amplifier U1A, and simultaneously, a capacitor C1 charges, so that the capacitor C1 discharges at the moment when the voltage of the input terminal decreases, a high-voltage signal of the output terminal is maintained, and the purpose of detecting the peak value of the signal is achieved. The traditional peak value detection circuit is not suitable for detecting high-frequency signals, has low measurement precision and low measurement speed, is only suitable for detecting the peak value in the process of increasing the voltage amplitude, and cannot accurately detect the voltage peak value when the amplitude is gradually reduced, so that the detection is limited in the practical application process.
The embodiment improves and compensates the original circuit structure. In the embodiment, the discharging circuit is added for detecting the voltage peak value when the amplitude is gradually reduced, when a step signal is given to the position P3, the gate-source voltage of the MOSFET is greater than the conduction threshold voltage, the MOSFET is conducted, and the R13 with a small series resistance value and the capacitor C1 form a discharging loop, so that the peak voltage of the input end is quickly discharged, and the next voltage signal peak value with a small amplitude is detected.
Meanwhile, in order to increase the driving capability of the system, an operational amplifier U1B is added at the output end, and load matching of the positive and negative input ends is carried out. Secondly, when the input signal is a negative voltage, the diode D1 in fig. 1 cannot be turned off immediately, and a reverse turn-off current is generated at the turn-off time, which affects the stability of the capacitor C1 and causes a safety hazard to the system, therefore, in this embodiment, a loop in which the diode D6 and the resistor R4 are located is added, so that the loop formed by the output end of the operational amplifier U1B and the resistor R4 provides a reverse turn-off current for the diode, and the stability and the safety of the system are improved.
In addition, in order to improve the rapidity of system detection, it is desirable that the charging time of the capacitor C1 can be greatly shortened, therefore, in this embodiment, a transistor is added to operate in the amplification region, the end of the operational amplifier U1A can drive the transistor with a small current to generate a large current for rapidly charging the C1, and the diodes D3 and D4 function to make the VEB much smaller than 6V, thereby protecting the transistor.
Finally, in order to reduce the product cost and improve the product utilization rate to the maximum extent, the operational amplifier U1A is enabled to work near the peak voltage all the time by using a cheap operational amplifier and adding the diodes D2 and D3, so that the defect of low running speed of the cheap operational amplifier is overcome, and the cheap operational amplifier can also be suitable for fast detection of high-frequency signals. Meanwhile, in order to avoid the excessive input current of the operational amplifier, two resistors R6 and R7 with large resistance values are added to the inverting input end of the operational amplifier (a path is formed by the resistor R2 and a feedback loop), and the accuracy of peak detection can be adjusted by adjusting the sliding rheostat R7. Through the above improvement, a fast and high-precision peak detection circuit is finally obtained, as shown in fig. 2, the specific structure of the circuit is as follows:
the pin 2 of the two-port pin header P2 is grounded, and the pin 1 is connected with a signal to be detected; one end of the resistor R11 is grounded, and the other end is connected with a pin 1 of the two-port pin header P2; one end of the resistor R10 is connected with the other end of the resistor R11, and the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U1A and the cathode of the diode D2; the anode of the diode D2 is connected with one end of the resistor R1; the other end of the resistor R1 is connected with one end of a resistor R2, the other end of the resistor R2 is connected with the anode of a diode D2, the fixed end of a slide rheostat R7 and the inverting input end of an operational amplifier U1A, the sliding end of the slide rheostat R7 is connected with one end of a resistor R6, and the other end of the resistor R6 is connected with a-12V power supply. The cathode of the diode D2 is connected with the output end of the operational amplifier U1A and one end of the resistor R8; the other end of the resistor R8 is connected with the cathode of the diode D3 and the base of the triode Q1, the collector of the triode Q1 is connected with a +12V power supply through a resistor R3, and the emitter of the triode Q1 is respectively connected with the anode of the diode D4, the anode of the diode D5, the cathode of the diode D7 and one end of the resistor R14.
The cathode of the diode D4 is connected with the anode of the diode D3, the anode of the diode D7 is connected with one end of the resistor R17, and the other ends of the resistor R17 and the resistor R14 are grounded; the cathode of the diode D5 is connected to one end of the resistor R4 and the anode of the diode D6, the anode of the diode D6 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the capacitor C1, one end of the resistor R16, one end of the resistor R13 and the non-inverting input terminal of the operational amplifier U1B, the inverting input terminal of the operational amplifier U1A is connected to one end of the resistor R5, the other end of the resistor R4 and the other end of the resistor R5 are connected to the output terminal of the operational amplifier U1B, the output terminal of the operational amplifier U1B is connected to pin 1 of the two-port pin bank P1 through the resistor R9, and pin 2 of the two-port pin bank P1 is grounded.
The other end of the capacitor C1 and the other end of the resistor R16 are grounded, the other end of the resistor R13 is connected with the drain electrode of the MOSFET, the grid electrode of the MOSFET is grounded, the source electrode of the MOSFET is connected with one end of the resistor R15, the other end of the resistor R15, one end of the resistor R18 is connected with one end of the capacitor C2, the other end of the capacitor C2 and one end of the resistor R19 are connected with the 1 pin of the dual-port pin bank P3, the 2 pin of the dual-port pin bank P3 is grounded, and the other end of the resistor R19 is grounded.
When the circuit of the embodiment performs peak detection, a signal to be detected is input from a port P2, when a voltage signal rises, the diode D2 is cut off, the D1 is conducted, and the operational amplifier U1A forms a voltage follower for outputting; the diodes D5 and D6 are conducted, the small current output by the operational amplifier U1A drives the triode to amplify the current, so that the capacitor C1 can be charged quickly, the electric quantity of the capacitor C1 is discharged slowly through a loop formed by the capacitor C1 and the large resistor R16, and finally the operational amplifier U1B outputs the amplitude of the signal to be detected. When the next signal to be measured comes, because the output end generates high potential, the actual working point of the operational amplifier U1A is limited near the peak value of the signal to be measured through voltage division of the resistor R1 and voltage drop of conduction of the diode D2, the actual working range of the operational amplifier is greatly reduced, the performance requirement of the operational amplifier is lowered, and the running speed of the circuit is improved. When the peak value of the signal to be detected is reduced, the MOSFET is conducted by giving a high level signal to the P3, and the capacitor C2 is continuously conducted for a period of time, at the moment, the capacitor C1 and the small resistor R13 form a loop, so that the electric quantity of the C1 is quickly discharged, the potential of the output end is reduced, and the peak value of the signal with the reduced amplitude can be detected in time.
Claims (4)
1. A high frequency signal peak detection circuit, characterized by: the device comprises an operational amplifier U1A, an operational amplifier U1B, a triode Q1 and a MOSFET tube;
the pin 2 of the two-port pin header P2 is grounded, and the pin 1 is connected with a signal to be detected; one end of the resistor R11 is grounded, and the other end is connected with a pin 1 of the two-port pin header P2; one end of the resistor R10 is connected with the other end of the resistor R11, and the other end of the resistor R10 is connected with the non-inverting input end of the operational amplifier U1A and the cathode of the diode D2;
the anode of the diode D2 is connected with one end of the resistor R1; the other end of the resistor R1 is connected with one end of a resistor R2, the other end of the resistor R2 is connected with the anode of a diode D2, the fixed end of a slide rheostat R7 and the inverting input end of an operational amplifier U1A, the sliding end of the slide rheostat R7 is connected with one end of a resistor R6, and the other end of the resistor R6 is connected with a-12V power supply;
the cathode of the diode D2 is connected with the output end of the operational amplifier U1A and one end of the resistor R8; the other end of the resistor R8 is connected with the cathode of the diode D3 and the base of the triode Q1, the collector of the triode Q1 is connected with a +12V power supply through a resistor R3, and the emitter of the triode Q1 is respectively connected with the anode of the diode D4, the anode of the diode D5, the cathode of the diode D7 and one end of the resistor R14;
the cathode of the diode D4 is connected with the anode of the diode D3, the anode of the diode D7 is connected with one end of the resistor R17, and the other ends of the resistor R17 and the resistor R14 are grounded;
the cathode of the diode D5 is connected with one end of a resistor R4 and the anode of the diode D6 respectively, the anode of the diode D6 is connected with one end of a resistor R12, the other end of a resistor R12 is connected with one end of a capacitor C1, one end of a resistor R16, one end of a resistor R13 and the non-inverting input end of an operational amplifier U1B respectively, the inverting input end of the operational amplifier U1A is connected with one end of a resistor R5, the other end of the resistor R4 and the other end of the resistor R5 are connected with the output end of an operational amplifier U1B, the output end of the operational amplifier U1B is connected with the 1 pin of the dual-port pin bank P1 through the resistor R9, and the 2 pin of the dual-port pin bank P1 is grounded;
the other end of the capacitor C1 and the other end of the resistor R16 are grounded, the other end of the resistor R13 is connected with the drain electrode of the MOSFET, the grid electrode of the MOSFET is grounded, the source electrode of the MOSFET is connected with one end of the resistor R15, the other end of the resistor R15, one end of the resistor R18 is connected with one end of the capacitor C2, the other end of the capacitor C2 and one end of the resistor R19 are connected with 1 pin of the dual-port pin P3, 2 pins of the dual-port pin P3 are grounded, and the other end of the resistor R19 is grounded;
a signal to be detected is input by a two-port pin header P2, when a voltage signal rises, a diode D2 is cut off, a diode D1 is conducted, and an operational amplifier U1A forms a voltage follower output; the diodes D5 and D6 are conducted, the small current output by the operational amplifier U1A drives the triode Q1 to amplify the current, so that the capacitor C1 is charged quickly, the electric quantity of the capacitor C1 is discharged slowly through a loop formed by the capacitor C1 and the resistor R16, and finally the operational amplifier U1B outputs the amplitude of the signal to be detected; when the next signal to be measured comes, the actual operating point of the operational amplifier U1A is limited to be near the peak value of the signal to be measured due to the high potential generated at the output end of the operational amplifier U1b, the voltage is divided by the resistor R1 and the voltage drop is conducted by the D2.
2. A high frequency signal peak detecting circuit according to claim 1, characterized in that: when the two-port pin header P3 gives a step signal, the MOSFET tube is conducted, so that the peak voltage at the input end is quickly discharged.
3. A high frequency signal peak detecting circuit according to claim 1, characterized in that: the triode Q1 works in the amplification region, so that the output end of the operational amplifier U1A drives the triode with small current to generate large current for rapidly charging the capacitor C1.
4. A high frequency signal peak detecting circuit according to claim 2, characterized in that: when the peak value of the signal to be detected is reduced, the capacitor C2 is continuously conducted for a period of time, at the moment, the capacitor C1 and the resistor R13 form a loop, the electric quantity of the capacitor C1 is quickly discharged, the potential of the output end of the operational amplifier U1B is reduced along with the electric quantity, and therefore the peak value of the signal with the reduced amplitude can be detected in time.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210316705.9A CN114710142B (en) | 2022-03-29 | 2022-03-29 | High-frequency signal peak value detection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210316705.9A CN114710142B (en) | 2022-03-29 | 2022-03-29 | High-frequency signal peak value detection circuit |
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| CN114710142A true CN114710142A (en) | 2022-07-05 |
| CN114710142B CN114710142B (en) | 2024-04-12 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060049774A1 (en) * | 2004-09-03 | 2006-03-09 | Tomoyuki Ichikawa | Peak detecting circuit and discharge lamp lighting device |
| KR20110057857A (en) * | 2009-11-25 | 2011-06-01 | 한국전기연구원 | Apparatus for detecting a peak value of alternative voltage |
| CN105306024A (en) * | 2015-11-18 | 2016-02-03 | 上海大学 | Peak voltage detection circuit |
| CN111506481A (en) * | 2020-04-24 | 2020-08-07 | 郑州工程技术学院 | Power supply loop monitoring system |
| CN113109619A (en) * | 2021-04-30 | 2021-07-13 | 江苏集萃智能集成电路设计技术研究所有限公司 | Receiver demodulator, peak detector and signal demodulation method |
-
2022
- 2022-03-29 CN CN202210316705.9A patent/CN114710142B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060049774A1 (en) * | 2004-09-03 | 2006-03-09 | Tomoyuki Ichikawa | Peak detecting circuit and discharge lamp lighting device |
| KR20110057857A (en) * | 2009-11-25 | 2011-06-01 | 한국전기연구원 | Apparatus for detecting a peak value of alternative voltage |
| CN105306024A (en) * | 2015-11-18 | 2016-02-03 | 上海大学 | Peak voltage detection circuit |
| CN111506481A (en) * | 2020-04-24 | 2020-08-07 | 郑州工程技术学院 | Power supply loop monitoring system |
| CN113109619A (en) * | 2021-04-30 | 2021-07-13 | 江苏集萃智能集成电路设计技术研究所有限公司 | Receiver demodulator, peak detector and signal demodulation method |
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