CN114706802A - Special sequential data distributor and implementation method thereof - Google Patents
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- CN114706802A CN114706802A CN202210294628.1A CN202210294628A CN114706802A CN 114706802 A CN114706802 A CN 114706802A CN 202210294628 A CN202210294628 A CN 202210294628A CN 114706802 A CN114706802 A CN 114706802A
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Abstract
The invention provides a special sequence data distributor and an implementation method thereof, wherein the implementation method comprises the following steps: adopting 2 input ports including an input data valid port i _ valid and an input data port i _ data; n output ports are adopted; and a sequential data distribution logic circuit is adopted, and when the input signal of the input data valid port i _ valid is at a high level, n data input from the input data port i _ data are sequentially output from the n output ports. The present invention reduces the use of combinational logic circuits, enabling the sequential data distributor to have high speed processing capabilities. Meanwhile, the sequence data distributor is internally realized in a pipeline mode, and layout and wiring are greatly facilitated. Compared with the traditional distributor, the performance and the advantages of the distributor are more obvious under the condition of higher speed and larger data volume.
Description
Technical Field
The invention relates to the technical field of data distributors, in particular to a special sequence data distributor and an implementation method thereof.
Background
The data distributor is a circuit for distributing a path of data to a designated output channel according to the requirement of an address signal.
The traditional data distributor is realized by a large number of combinational circuits, is not suitable for the conditions of high-speed circuits and large data quantity, and can cause data errors if the speed is too high; if the amount of data is too large, the internal circuit complexity can be greatly increased, further degrading the splitter performance.
The structure of the conventional data distributor is shown in fig. 1, which has two input ports (i _ sel and i _ data) and n output ports (data (1), data (2) … … data (n)). Inside the data distributor are actually several gate-selectable switches, which control the gating of the corresponding channel by the value of the i _ sel port and then output the i _ data value to the gate port.
The conventional data distributor is implemented in a manner as shown in fig. 2, and controls an enable signal of a corresponding channel by a value of an i _ sel port, thereby gating the corresponding channel and outputting input data to the gated channel. For example, when i _ sel ═ 1, the channel 2 outputs high level, and the remaining channels output low level, at this time, the channel 2 is gated, the input data i _ data is directly output onto data (2), and the remaining channel data remains unchanged.
However, when the data distributor is in high-speed operation, the value of the i _ sel port changes in a very short time, and if the internal channel arbiter cannot keep up with the change speed of the value of the i _ sel port, the channel selection error is caused, and the final output result is wrong.
Moreover, if the data amount is too large, the number of channels is increased, and the complexity of an internal combined circuit is further increased, so that the wiring difficulty inside the distributor is increased, the wiring delay is increased, and the processing speed is further reduced.
Disclosure of Invention
The invention aims to provide a special sequential data distributor and an implementation method thereof, so as to solve the data distribution problem of the traditional data distributor in a high-speed circuit and the data distribution problem under the condition of large data volume.
The invention provides a method for realizing a special sequence data distributor, which comprises the following steps:
adopting 2 input ports including an input data valid port i _ valid and an input data port i _ data;
adopting n output ports, including output port data (1), output port data (2), … …, output port data (n);
when an input signal of the input data valid port i _ valid is at a high level, n data input from the input data port i _ data are sequentially output from the output port data (1), the output ports data (2), … … and the output port data (n) by using a sequential data distribution logic circuit.
Further, the implementation principle of the sequential data allocation logic circuit includes:
carrying out rising edge detection on an input signal of an input data valid port i _ valid, sending a rising edge detection result to an enabling end of a D trigger of a 1 st channel, simultaneously beating the rising edge detection result, and outputting the beating result to enabling ends of D triggers of corresponding 2 nd to n th channels;
when the rising edge detection is carried out on the input signal of the input data valid port i _ valid, the data input by the input data port i _ data is connected to the data ends of the D triggers of all channels;
the output ends of the D flip-flops of the 1 st to nth channels are the output port data (1), the output port data (2), … … and the output port data (n).
Furthermore, the sequential data distribution logic circuit is realized by adopting a register, a NOT gate, an AND gate and a D trigger.
Further, the method for realizing the rising edge detection comprises the following steps:
adopting a register I, a register II, a NOT gate and an AND gate to realize rising edge detection; the input end of the first register is connected with an input data valid port i _ valid, and the output end of the first register is connected with the first input end of the AND gate after passing through the second register and the NOT gate on one hand and is directly connected with the second input end of the AND gate on the other hand; and the output end of the AND gate is used for outputting a rising edge detection result.
Further, the method for realizing the beating of the detection result of the rising edge comprises the following steps:
beating the detection result of the rising edge by adopting n-1 registers connected in sequence, wherein the beating times are n-1;
the input end of the 1 st register is connected with the output end of the AND gate, and the output end of each register is also connected with the enabling ends of the 2 nd to nth D triggers.
Furthermore, while detecting the rising edge of the input signal of the input data valid port i _ valid, a two-beat delay operation needs to be performed on the data input by the input data port i _ data, so that the rising edge of the input signal of the valid port i _ valid is aligned with the 1 st data in the data input by the input data port i _ data.
Further, the two-beat delay operation is realized by adopting 2 connected registers.
The invention also provides a special sequential data distributor, which is realized by adopting the implementation method.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
the invention can be applied to the technical field of digital ICs (integrated circuits) such as FPGA (field programmable gate array), CPLD (complex programmable logic device), semi-custom ASIC (application specific integrated circuit), full-custom ASIC (application specific integrated circuit) and the like, and can greatly improve the performance of the distributor especially under certain special scenes (continuous data input, known channel number, only once gating of each channel and sequential distribution). The present invention provides the sequential data distributor with high speed processing capability due to the reduced use of combinational logic circuits. Meanwhile, the sequence data distributor is internally realized in a pipeline mode, and layout and wiring are greatly facilitated. Compared with the traditional distributor, the performance and the advantages of the distributor are more obvious under the condition of higher speed and larger data volume.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a block diagram of a conventional data distributor.
Fig. 2 is a schematic diagram of a conventional data distributor.
Fig. 3 is a schematic diagram of an implementation of a dedicated sequential data distributor according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
As shown in fig. 1, the present embodiment provides a method for implementing a dedicated sequential data distributor, including:
adopting 2 input ports including an input data valid port i _ valid and an input data port i _ data;
adopting n (n is more than 1 and n is an integer) output ports, including output port data (1), output port data (2), … … and output port data (n);
when an input signal of the input data valid port i _ valid is at a high level, n data input from the input data port i _ data are sequentially output from the output port data (1), the output ports data (2), … … and the output port data (n) by using a sequential data distribution logic circuit.
The implementation principle of the sequential data distribution logic circuit comprises the following steps:
carrying out rising edge detection on an input signal of an input data valid port i _ valid, sending a rising edge detection result to an enabling end of a D trigger of a 1 st channel, simultaneously beating the rising edge detection result, and outputting the beating result to enabling ends of D triggers of corresponding 2 nd to n th channels;
when the rising edge detection is carried out on the input signal of the input data valid port i _ valid, the data input by the input data port i _ data is connected to the data ends of the D triggers of all channels;
the output ends of the D flip-flops of the 1 st to nth channels are the output port data (1), the output port data (2), … … and the output port data (n).
In this embodiment, the sequential data distribution logic circuit is implemented by using a register, a not gate, an and gate, and a D flip-flop. As shown in fig. 2:
the method for realizing the rising edge detection comprises the following steps:
adopting a register I, a register II, a NOT gate and an AND gate to realize rising edge detection; the input end of the first register is connected with an input data valid port i _ valid, and the output end of the first register is connected with the first input end of the AND gate after passing through the second register and the NOT gate on one hand and is directly connected with the second input end of the AND gate on the other hand; and the output end of the AND gate is used for outputting a rising edge detection result.
The method for realizing the beating of the detection result of the rising edge comprises the following steps:
beating the detection result of the rising edge by adopting n-1 registers connected in sequence, wherein the beating times are n-1;
the input end of the 1 st register is connected with the output end of the AND gate, and the output end of each register is also connected with the enabling ends of the 2 nd to nth D triggers. For example, the beat result of the first register is output to the enable terminal of the D flip-flop of the 2 nd channel, … …, and the beat result of the (n-1) th register is output to the enable terminal of the D flip-flop of the n th channel.
Furthermore, while detecting the rising edge of the input signal of the input data valid port i _ valid, a two-beat delay operation needs to be performed on the data input by the input data port i _ data, so that the rising edge of the input signal of the valid port i _ valid is aligned with the 1 st data in the data input by the input data port i _ data. As shown in fig. 3, a two-beat delay operation may be implemented using 2 connected registers.
If n channels are provided, n pieces of data are continuously input, and the n pieces of data need to be sequentially output to the n channels. The working principle of the special sequential data distributor is as follows:
when data is input into the input data port i _ data, detecting a rising edge of an input signal of the input data valid port i _ valid (the valid time of the rising edge is only one clock cycle), enabling the D flip-flop of the 1 st channel (the D flip-flops of the other channels are in a disabled state at the moment), and outputting the 1 st data from the output end of the D flip-flop of the 1 st channel (because the valid time of the rising edge is only one clock cycle, the D flip-flop of the channel also has an enabled state of only one clock cycle, only 1 data is output, and when the next clock arrives, the D flip-flop of the channel returns to the disabled state); when the next clock cycle comes, the D flip-flop of the 2 nd channel is enabled (the other channel flip-flops are in a disabled state at this time), and the output end of the D flip-flop of the 2 nd channel outputs the 2 nd data; when the next clock cycle comes, the D flip-flop of the 3 rd channel is enabled (the other channel flip-flops are in a disabled state at the moment), and the output end of the D flip-flop of the 3 rd channel outputs the 3 rd data; this is followed until the D flip-flop of the nth channel is enabled and outputs the last nth data.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A method for implementing a dedicated sequential data distributor, comprising:
adopting 2 input ports including an input data valid port i _ valid and an input data port i _ data;
adopting n output ports, including output port data (1), output port data (2), … …, output port data (n);
when an input signal of the input data valid port i _ valid is at a high level, n data input from the input data port i _ data are sequentially output from the output port data (1), the output ports data (2), … … and the output port data (n) by using a sequential data distribution logic circuit.
2. The method of claim 1, wherein the sequential data distribution logic is implemented according to a principle comprising:
carrying out rising edge detection on an input signal of an input data valid port i _ valid, sending a rising edge detection result to an enabling end of a D trigger of a 1 st channel, simultaneously beating the rising edge detection result, and outputting the beating result to enabling ends of D triggers of corresponding 2 nd to n th channels;
when the rising edge detection is carried out on the input signal of the input data valid port i _ valid, the data input by the input data port i _ data is connected to the data ends of the D triggers of all channels;
the output ends of the D flip-flops of the 1 st to nth channels are the output port data (1), the output port data (2), … … and the output port data (n).
3. The method of claim 2, wherein the sequential data distribution logic is implemented using registers, NOT gates, AND gates, and D flip-flops.
4. The method of claim 3, wherein the method for detecting the rising edge comprises:
adopting a register I, a register II, a NOT gate and an AND gate to realize rising edge detection; the input end of the first register is connected with an input data valid port i _ valid, and the output end of the first register is connected with the first input end of the AND gate after passing through the second register and the NOT gate on one hand and is directly connected with the second input end of the AND gate on the other hand; and the output end of the AND gate is used for outputting a rising edge detection result.
5. The method for implementing the dedicated sequential data distributor according to claim 4, wherein the method for implementing the beating of the detection result of the rising edge comprises:
beating the detection result of the rising edge by adopting n-1 registers connected in sequence, wherein the beating times are n-1;
the input end of the 1 st register is connected with the output end of the AND gate, and the output end of each register is also connected with the enabling ends of the 2 nd to nth D triggers.
6. The method as claimed in claim 5, wherein the rising edge of the input signal of the valid input data port i _ valid is detected, and at the same time, the data input by the valid input data port i _ data needs to be delayed by two beats, so that the rising edge of the input signal of the valid input data port i _ valid is aligned with the 1 st data in the data input by the valid input data port i _ data.
7. The method of claim 6, wherein the two-beat delay operation is implemented using 2 registers connected.
8. The method of claim 1, wherein n > 1 and n is an integer.
9. A dedicated sequential data distributor, characterized in that it is implemented using the implementation method according to any one of claims 1 to 8.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2015457A2 (en) * | 2007-07-12 | 2009-01-14 | Mitsubishi Heavy Industries, Ltd. | Serial-to-parallel conversion circuit and method of designing the same |
| CN106374898A (en) * | 2016-10-18 | 2017-02-01 | 天津大学 | Time sequence generating structure of multi-channel output gating switch |
| CN110619838A (en) * | 2019-11-04 | 2019-12-27 | 京东方科技集团股份有限公司 | Shift register unit circuit, driving method, gate driver and display device |
| CN114185397A (en) * | 2022-02-15 | 2022-03-15 | 深圳市爱普特微电子有限公司 | Cross-clock domain data transmission circuit and method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2015457A2 (en) * | 2007-07-12 | 2009-01-14 | Mitsubishi Heavy Industries, Ltd. | Serial-to-parallel conversion circuit and method of designing the same |
| CN106374898A (en) * | 2016-10-18 | 2017-02-01 | 天津大学 | Time sequence generating structure of multi-channel output gating switch |
| CN110619838A (en) * | 2019-11-04 | 2019-12-27 | 京东方科技集团股份有限公司 | Shift register unit circuit, driving method, gate driver and display device |
| CN114185397A (en) * | 2022-02-15 | 2022-03-15 | 深圳市爱普特微电子有限公司 | Cross-clock domain data transmission circuit and method |
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