CN114706802B - Special sequential data distributor and implementation method thereof - Google Patents
Special sequential data distributor and implementation method thereof Download PDFInfo
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- CN114706802B CN114706802B CN202210294628.1A CN202210294628A CN114706802B CN 114706802 B CN114706802 B CN 114706802B CN 202210294628 A CN202210294628 A CN 202210294628A CN 114706802 B CN114706802 B CN 114706802B
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- 230000000630 rising effect Effects 0.000 claims description 36
- 238000003708 edge detection Methods 0.000 claims description 23
- 238000010009 beating Methods 0.000 claims description 12
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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Abstract
The invention provides a special sequence data distributor and an implementation method thereof, wherein the implementation method comprises the following steps: 2 input ports are adopted, wherein the input ports comprise an input data effective port i_valid and an input data port i_data; adopting n output ports; and when the input signal of the effective input data port i_valid is at a high level, the n data input from the input data port i_data are sequentially output from the n output ports according to the sequence. The present invention reduces the use of combinational logic circuits, enabling the sequential data allocator to have high speed processing capabilities. Meanwhile, the sequential data distributor is internally realized in a pipeline mode, so that the layout and the wiring are greatly facilitated. The higher the speed, the greater the data volume, the more significant the performance and advantages of the dispenser compared to conventional dispensers.
Description
Technical Field
The invention relates to the technical field of data distributors, in particular to a special sequential data distributor and an implementation method thereof.
Background
The data distributor refers to a circuit for distributing one path of data to a designated output channel according to the address signal requirement.
The traditional data distributor is realized by a large number of combined circuits, is not suitable for the conditions of high-speed circuits and large data volume, and can cause data errors if the speed is too high; if the amount of data is too large, the complexity of the internal circuitry can be greatly increased, further degrading the performance of the divider.
The conventional data splitter has a structure as shown in fig. 1, which has two input ports (i_sel and i_data) and n output ports (data (1), data (2) … … data (n)). Inside the data distributor are actually several selectable switches, the gating of the corresponding channel is controlled by the value of the i_sel port, and then the i_data value is output to the gating port.
The conventional data distributor is implemented as shown in fig. 2, which controls the enable signal of the corresponding channel by the value of the i_sel port, thereby gating the corresponding channel, and outputs input data to the gated channel. For example, when i_sel= 1, channel 2 outputs high level, and the remaining channels output low level, at this time, channel 2 is gated, input data i_data is directly output onto data (2), and the remaining channel data remains unchanged.
However, when the data distributor is operated at a high speed, the value of the i_sel port may change in an extremely short time, and if the internal channel discriminator does not keep pace with the change speed of the value of the i_sel port, a channel selection error may be caused, thereby causing a final output result error.
And if the data volume is too large, the number of channels is increased, so that the complexity of an internal combined circuit is further increased, the wiring difficulty in the distributor is increased, the wiring delay is increased, and the processing speed is further reduced.
Disclosure of Invention
The invention aims to provide a special sequence data distributor and an implementation method thereof, which are used for solving the data distribution problem of the traditional data distributor in a high-speed circuit and the data distribution problem under the condition of large data volume.
The invention provides a realization method of a special sequence data distributor, which comprises the following steps:
2 input ports are adopted, wherein the input ports comprise an input data effective port i_valid and an input data port i_data;
adopting n output ports, including output port data (1), output port data (2), … … and output port data (n);
when the input signal of the input data valid port i_valid is at a high level, the sequential data distribution logic circuit is adopted to sequentially output n data input from the input data port i_data from the output ports data (1), data (2), … … and data (n) according to the sequence.
Further, the implementation principle of the sequential data distribution logic circuit includes:
detecting the rising edge of an input signal of an input data effective port i_valid, giving a rising edge detection result to the enabling end of the D trigger of the 1 st channel, beating the rising edge detection result, and outputting beating results to the enabling ends of the D triggers of the corresponding 2 nd to n th channels;
the method comprises the steps of detecting the rising edge of an input signal of an input data effective port i_valid, and simultaneously connecting data input by an input data port i_data to the data ends of D triggers of all channels;
the output ends of the D flip-flops of the 1 st to n th channels are output ports data (1), output ports data (2), … … and output ports data (n).
Further, the sequential data distribution logic circuit is implemented by a register, an NOT gate, an AND gate and a D trigger.
Further, the method for realizing rising edge detection comprises the following steps:
adopting a first register, a second register, an NOT gate and an AND gate to realize rising edge detection; the input end of the first register is connected with an input data effective port i_valid, the output end of the first register is connected with the first input end of an AND gate after passing through the second register and the NOT gate, and the output end of the first register is directly connected with the second input end of the AND gate; the output end of the AND gate is used for outputting the rising edge detection result.
Further, the method for beating the rising edge detection result comprises the following steps:
the rising edge detection result is beaten by adopting n-1 registers which are connected in sequence, and the beating times are n-1;
the input end of the 1 st register is connected with the output end of the AND gate, and the output end of each register is also connected with the enabling ends of the 2 nd to n th D flip-flops.
Further, while the rising edge detection is performed on the input signal of the valid port i_valid of the input data, a two-beat delay operation is performed on the data input by the valid port i_data, so that the rising edge of the input signal of the valid port i_valid is aligned with the 1 st data in the data input by the valid port i_data.
Furthermore, the two-beat delay operation is realized by adopting 2 connected registers.
The invention also provides a special sequential data distributor, which is realized by adopting the realization method.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
the invention can be applied to the technical field of digital ICs such as FPGA, CPLD, semi-custom, fully custom ASIC and the like, and can greatly improve the performance of the distributor especially under certain special scenes (data continuous input, channel number is known, each channel is only selected once and distributed in sequence). The sequential data distributor has high-speed processing capability due to the reduced use of combinational logic circuits. Meanwhile, the sequential data distributor is internally realized in a pipeline mode, so that the layout and the wiring are greatly facilitated. The higher the speed, the greater the data volume, the more significant the performance and advantages of the dispenser compared to conventional dispensers.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly describe the drawings in the embodiments, it being understood that the following drawings only illustrate some embodiments of the present invention and should not be considered as limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a conventional data distributor.
Fig. 2 is a schematic diagram of an implementation of a conventional data distributor.
Fig. 3 is a schematic diagram of an implementation of a special sequential data allocator according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples
As shown in fig. 1, this embodiment proposes a method for implementing a dedicated sequential data allocator, including:
2 input ports are adopted, wherein the input ports comprise an input data effective port i_valid and an input data port i_data;
n (n is larger than 1 and n is an integer) output ports are adopted, and the output ports comprise output port data (1), output port data (2), … … and output port data (n);
when the input signal of the input data valid port i_valid is at a high level, the sequential data distribution logic circuit is adopted to sequentially output n data input from the input data port i_data from the output ports data (1), data (2), … … and data (n) according to the sequence.
The implementation principle of the sequential data distribution logic circuit comprises the following steps:
detecting the rising edge of an input signal of an input data effective port i_valid, giving a rising edge detection result to the enabling end of the D trigger of the 1 st channel, beating the rising edge detection result, and outputting beating results to the enabling ends of the D triggers of the corresponding 2 nd to n th channels;
the method comprises the steps of detecting the rising edge of an input signal of an input data effective port i_valid, and simultaneously connecting data input by an input data port i_data to the data ends of D triggers of all channels;
the output ends of the D flip-flops of the 1 st to n th channels are output ports data (1), output ports data (2), … … and output ports data (n).
In this embodiment, the sequential data distribution logic circuit is implemented using a register, an not gate, an and gate, and a D flip-flop. As shown in fig. 2:
the method for realizing rising edge detection comprises the following steps:
adopting a first register, a second register, an NOT gate and an AND gate to realize rising edge detection; the input end of the first register is connected with an input data effective port i_valid, the output end of the first register is connected with the first input end of an AND gate after passing through the second register and the NOT gate, and the output end of the first register is directly connected with the second input end of the AND gate; the output end of the AND gate is used for outputting the rising edge detection result.
The method for beating the rising edge detection result comprises the following steps:
the rising edge detection result is beaten by adopting n-1 registers which are connected in sequence, and the beating times are n-1;
the input end of the 1 st register is connected with the output end of the AND gate, and the output end of each register is also connected with the enabling ends of the 2 nd to n th D flip-flops. For example, the beat result of the first register is output to the enable end of the D flip-flop of the 2 nd channel, … …, and the beat result of the n-1 st register is output to the enable end of the D flip-flop of the n-th channel.
Further, while the rising edge detection is performed on the input signal of the valid port i_valid of the input data, a two-beat delay operation is performed on the data input by the valid port i_data, so that the rising edge of the input signal of the valid port i_valid is aligned with the 1 st data in the data input by the valid port i_data. As shown in fig. 3, a two beat delay operation may be implemented using 2 connected registers.
Assuming that n channels are provided, n data are sequentially input, and the n data need to be sequentially output to the n channels. The working principle of the special sequential data distributor is as follows:
when the input data port i_data has data input, detecting the rising edge of an input signal of the input data valid port i_valid (the valid time of the rising edge only has one clock cycle), enabling the D trigger of the 1 st channel (the D triggers of the other channels are in the disabled state at the moment), and outputting the 1 st data by the output end of the D trigger of the 1 st channel (because the valid time of the rising edge only has one clock cycle, the D trigger of the channel also has the enabled state of only one clock cycle, only outputs 1 data, and when the next clock arrives, the D trigger of the channel returns to the disabled state again); when the next clock period comes, enabling the D trigger of the 2 nd channel (the other channel triggers are in the disabled state at the moment), and outputting the 2 nd data by the output end of the D trigger of the 2 nd channel; when the next clock period comes, enabling the D trigger of the 3 rd channel (the rest channel triggers are in the disabled state at the moment), and outputting the 3 rd data by the output end of the D trigger of the 3 rd channel; and recursively, until the D flip-flop of the nth channel is enabled and outputs the last nth data.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for implementing a special sequential data distributor, comprising:
2 input ports are adopted, wherein the input ports comprise an input data effective port i_valid and an input data port i_data;
adopting n output ports, including output port data (1), output port data (2), … … and output port data (n);
when the input signal of the effective input data port i_valid is at a high level, the sequential data distribution logic circuit is adopted to sequentially output n data input from the input data port i_data from the output ports data (1), the output ports data (2), … … and the output port data (n) in sequence;
the implementation principle of the sequential data distribution logic circuit comprises the following steps:
detecting the rising edge of an input signal of an input data effective port i_valid, giving a rising edge detection result to the enabling end of the D trigger of the 1 st channel, beating the rising edge detection result, and outputting the beating result to the enabling end of the D trigger of the corresponding 2~n th channel;
the method comprises the steps of detecting the rising edge of an input signal of an input data effective port i_valid, and simultaneously connecting data input by an input data port i_data to the data ends of D triggers of all channels;
the output ends of the D flip-flops of the 1 st to n th channels are output ports data (1), output ports data (2), … … and output ports data (n).
2. The method of claim 1, wherein the sequential data distribution logic is implemented using registers, not gates, and D flip-flops.
3. The method for implementing a dedicated sequential data allocator according to claim 2, wherein the method for implementing rising edge detection is:
adopting a first register, a second register, an NOT gate and an AND gate to realize rising edge detection; the input end of the first register is connected with an input data effective port i_valid, the output end of the first register is connected with the first input end of an AND gate after passing through the second register and the NOT gate, and the output end of the first register is directly connected with the second input end of the AND gate; the output end of the AND gate is used for outputting the rising edge detection result.
4. A method for implementing a dedicated sequential data distributor according to claim 3, wherein the method for implementing beating of the rising edge detection result is:
the rising edge detection result is beaten by adopting n-1 registers which are connected in sequence, and the beating times are n-1;
the input end of the 1 st register is connected with the output end of the AND gate, and the output end of each register is also connected with the enabling end of the 2~n D trigger.
5. The method according to claim 4, wherein the rising edge of the input signal of the valid port i_valid is detected while the data input from the input data port i_data is delayed by two beats, so that the rising edge of the input signal of the valid port i_valid is aligned with the 1 st data in the data input from the input data port i_data.
6. The method of claim 5, wherein the two-beat delay operation is implemented using 2 connected registers.
7. The method of claim 1, wherein n > 1 and n is an integer.
8. A dedicated sequential data distributor, characterized in that said sequential data distributor is implemented using the implementation method according to any of claims 1-7.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2015457A2 (en) * | 2007-07-12 | 2009-01-14 | Mitsubishi Heavy Industries, Ltd. | Serial-to-parallel conversion circuit and method of designing the same |
| CN106374898A (en) * | 2016-10-18 | 2017-02-01 | 天津大学 | Time sequence generating structure of multi-channel output gating switch |
| CN110619838A (en) * | 2019-11-04 | 2019-12-27 | 京东方科技集团股份有限公司 | Shift register unit circuit, driving method, gate driver and display device |
| CN114185397A (en) * | 2022-02-15 | 2022-03-15 | 深圳市爱普特微电子有限公司 | Cross-clock domain data transmission circuit and method |
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- 2022-03-24 CN CN202210294628.1A patent/CN114706802B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2015457A2 (en) * | 2007-07-12 | 2009-01-14 | Mitsubishi Heavy Industries, Ltd. | Serial-to-parallel conversion circuit and method of designing the same |
| CN106374898A (en) * | 2016-10-18 | 2017-02-01 | 天津大学 | Time sequence generating structure of multi-channel output gating switch |
| CN110619838A (en) * | 2019-11-04 | 2019-12-27 | 京东方科技集团股份有限公司 | Shift register unit circuit, driving method, gate driver and display device |
| CN114185397A (en) * | 2022-02-15 | 2022-03-15 | 深圳市爱普特微电子有限公司 | Cross-clock domain data transmission circuit and method |
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