CN114705973A - Non-invasive complex environment integrated circuit aging monitoring method - Google Patents
Non-invasive complex environment integrated circuit aging monitoring method Download PDFInfo
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- CN114705973A CN114705973A CN202210614890.XA CN202210614890A CN114705973A CN 114705973 A CN114705973 A CN 114705973A CN 202210614890 A CN202210614890 A CN 202210614890A CN 114705973 A CN114705973 A CN 114705973A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2849—Environmental or reliability testing, e.g. burn-in or validation tests
Abstract
The invention discloses a non-invasive complex environment integrated circuit aging monitoring method, and belongs to the field of hardware aging monitoring. The invention collects the aging change characteristic parameters of the storage module and the read-write module, establishes a specific aging monitoring-prediction model, simulates the change value of the characteristic parameters of a target integrated circuit device after operation by collecting the external module, and compares the change value with the established model value to obtain the actual service life and the expected service life of the integrated circuit. The invention can carry out non-invasive real-time monitoring of the whole life cycle of the integrated circuit equipment under the complex environment, and can realize the life monitoring only by consuming very low power on the premise of not influencing the operation of the target integrated circuit. The aging monitoring may be performed in a case where the target integrated circuit is operating normally.
Description
Technical Field
The invention belongs to the field of hardware aging monitoring, and relates to a non-invasive complex environment integrated circuit aging monitoring method.
Background
The aging monitoring techniques at present are roughly classified into 3 types: duplicate/gold Circuits (Replica/arc Circuits), In-Situ Sensors (In-Situ Sensors), Model based monitoring (Model based Prediction).
The copying circuit adopts a process simulation method, and simulates the aging process of the tested circuit by using the copying circuit: a duplicate circuit and a similar circuit of a critical path in an original circuit are used and are placed beside the original circuit, but are isolated from the original circuit, and the aging degree of the original circuit is estimated by measuring the aging condition of the duplicate circuit under a specific load condition (greater than or equal to the working load of the original circuit).
The in-situ sensor technology exists relative to a backup circuit, adopts a direct measurement method, and directly measures the characteristic parameters of a circuit to be measured: the sensor is directly arranged in the monitored critical path/circuit module, and can directly measure relevant circuit parameters of the monitored circuit, such as path delay of the critical path, threshold voltage in SRAM and the like.
The model-based monitoring adopts indirect measurement, and after the circuit aging is modeled, an aging factor is measured to predict the aging state of the circuit: the aging state of the circuit is predicted in real time by measuring indirect factors such as circuit working load, voltage and temperature and the like and establishing a model.
The existing detection method mainly installs an intrusive aging monitor, and the technical defects are obvious, firstly the cost is a problem, and secondly the integrated circuit is influenced during operation. And the problems are solved by physical detection methods, such as physical analysis method and bypass detection method, and the detection methods have a series of problems, the physical detection method causes irreversible damage to hardware, and the bypass detection method consumes long time and needs professional equipment.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a non-invasive complex environment integrated circuit aging monitoring method. The invention adopts a mode of combining a copy circuit with monitoring based on a model, can realize monitoring without reverse engineering on the integrated circuit, is real-time and non-invasive, adopts an external module to be connected with target equipment, and acquires the aging time and the expected service life of the integrated circuit by using a computer or other equipment capable of receiving data to acquire the aging parameters of the external module.
The technical scheme adopted by the invention for solving the technical problems is as follows:
the invention firstly provides a non-invasive complex environment integrated circuit aging monitoring method, which comprises the following steps:
step 1: adopting the static random access memory with the same type as the static random access memory on the target integrated circuit to carry out aging detection simulation in a complex environment, collecting aging characteristic parameters, extracting aging characteristic data of a storage module and the aging characteristic data of a read-write module in the aging characteristic parameters, and establishing an aging monitoring-predicting model;
the aging characteristic data of the storage module is the number ratio of high level and low level of the storage units when the power is on; the aging characteristic data of the read-write module comprises the bit number of error transmission, the clock trigger time of the digital circuit and the power-on time of the digital circuit;
step 2: for a target integrated circuit to be predicted, embedding an external simulation operation module to perform read-write simulation on a static random access memory of the target integrated circuit, and setting the read-write of the external simulation operation module to be consistent with the static random access memory of the target integrated circuit so as to achieve the purpose of copying the operation state of the target integrated circuit; and the external module simulates to store or transmit the aging characteristic data in real time, compares the aging characteristic data with the aging monitoring-predicting model, and outputs the aging time and the expected life of the static random access memory of the target integrated circuit.
In a preferred embodiment of the present invention, the complex environment in step 1 is exactly the same as the actual working environment of the target integrated circuit to be predicted in step 2, and the complex environment is one or more of a high-temperature environment, a high-humidity environment, or a strong electromagnetic interference environment.
As a preferred scheme of the invention, the high temperature is 85-125 ℃; the high humidity refers to relative humidity of 70% to 90%; the electromagnetic interference means that the maximum measurable transient electric field intensity is not less than 50V/m, the electromagnetic measurement sensitivity is not more than 10mV/m, the maximum measurable transient magnetic field intensity is not less than 0.1A/m, and the magnetic field measurement sensitivity is not more than 1 mA/m.
As a preferred solution of the present invention, the memory module includes a plurality of memory cells, when each memory cell is powered on, the potential value of each memory cell will be randomly biased to a high level or a low level, and after a brand new sram is powered on, the distribution of logic high levels or logic low levels is substantially the same; as sram is used, the percentage of high and low levels at power-up can shift, indicating a change in the ratio of the number of high and low levels of the memory cells at power-up.
As a preferred embodiment of the present invention, the aging monitoring-prediction model is as follows:
H = at 3+bt 2 + ct + H 0
t anticipation of= t Terminate -t
Wherein the content of the first and second substances,Hfor the high potential ratio (%) of the sram,tfor the aging time (days),ain order to influence the parameters with respect to temperature,bin order to be able to electromagnetically influence the parameter,cin order to influence the parameters of the humidity,H 0the high potential ratio of a brand-new static random access memory is realized without external factor interference;t anticipation ofThe expected remaining life of the sram,t terminateThe life of the SRAM is the full cycle from use to complete aging.
As a preferred scheme of the present invention, the external analog operation module is a static random access memory of the same type that shares a power supply and a ground with a static random access memory of the integrated circuit to be tested, and the external analog operation module further includes a read-write module, which can be a single chip microcomputer or an FPGA.
As a preferred scheme of the present invention, in step 2, the external simulation operation module needs to be embedded into the target integrated circuit to be predicted before the target integrated circuit to be predicted is put into use;
the embedding method comprises the following steps: the external simulation operation module and the static random access memory of the integrated circuit to be tested share a power supply and a ground, namely the same power supply voltage is used in the same environment, the daily average read-write times under the normal use of the static random access memory of the target integrated circuit are extracted, the read-write frequency is calculated, and the aging characteristic data is stored.
As a preferred scheme of the present invention, step 2 further includes a step of determining whether data stored or transmitted by the external simulation operation module is valid data before comparing with the aging monitoring-prediction model, and deleting invalid data and retaining valid data;
the criterion for judging whether the data is valid data is as follows: and in a period of continuous time, judging that the data acquired at a certain time point has a numerical deviation of more than 10% with the data acquired before and after, and judging that the data is invalid, otherwise, judging that the data is valid.
As a preferred embodiment of the present invention, in step 1, the aging detection simulation is started from a completely new sram until the sram is completely aged, wherein any one of the following conditions is satisfied, that is, the sram is considered to be completely aged:
1) the rising edge or falling edge time is prolonged by 30 percent;
2) the whole time sequence time is prolonged by 15%;
3) the read-write speed is reduced by 20%;
4) the average number of error bits in continuous reading and writing for a period of time is more than 1 bit;
the read-write module aging characteristic data is used for judging whether the static random access memory participating in the simulation is completely aged or not.
Compared with the prior art, the invention has the advantages that the invention can carry out non-invasive real-time monitoring of the whole life cycle of the integrated circuit equipment in a complex environment, and can realize the life monitoring only by consuming very low power on the premise of not influencing the operation of a target integrated circuit. The aging monitoring may be performed in a case where the target integrated circuit is operating normally.
Drawings
FIG. 1 is a schematic diagram of high voltage ratio when a certain type of SRAM is powered on.
FIG. 2 is a diagram illustrating the number of bits erroneously transmitted by a SRAM of a certain type.
Fig. 3 is a flow chart embodying the aging monitoring method.
Detailed Description
The invention will be further illustrated and described with reference to specific embodiments. The described embodiments are merely exemplary of the disclosure and are not intended to limit the scope thereof. The technical features of the embodiments of the present invention can be combined correspondingly without mutual conflict.
In the read and write process of the random access memory, two types of aging are mainly generated, wherein one type is aging of a storage module, and the other type is aging of a read and write module.
The invention collects the variation characteristic parameters of the two aging types, establishes a specific aging monitoring-forecasting model, simulates the variation value of the characteristic parameters of the target integrated circuit device after operation through the collection external module, and compares the variation value with the established model value to obtain the actual life and the expected life of the integrated circuit. The device mainly operates in complex environments, such as high-temperature, high-humidity and strong electromagnetic interference environments, and achieves non-invasive aging monitoring on the integrated circuit in the complex environments.
As shown in fig. 3, the non-intrusive complex environment integrated circuit aging monitoring method according to the embodiment of the present invention includes the following steps:
step 1: adopting the static random access memory with the same type as the static random access memory on the target integrated circuit to carry out aging detection simulation in a complex environment, collecting aging characteristic parameters, extracting aging characteristic data of a storage module and the aging characteristic data of a read-write module in the aging characteristic parameters, and establishing an aging monitoring-predicting model;
the aging characteristic data of the storage module is the number ratio of high level and low level of the storage units when the power is on; the aging characteristic data of the read-write module comprises the bit number of error transmission, the clock trigger time of the digital circuit and the power-on time of the digital circuit;
step 2: for a target integrated circuit to be predicted, embedding an external simulation operation module to simulate the reading and writing of a static random access memory of the target integrated circuit, and setting the reading and writing of the external simulation operation module to be consistent with the static random access memory of the target integrated circuit so as to achieve the purpose of copying the operation state of the target integrated circuit; and the external module simulates to store or transmit the aging characteristic data in real time, compares the aging characteristic data with the aging monitoring-predicting model, and outputs the aging time and the expected life of the static random access memory of the target integrated circuit.
For step 1, the aging characteristic parameter of the memory module is mainly determined by the power-on logic state of the random access memory, i.e. the ratio of the number of high levels and low levels of the memory cells at power-on, and the ratio changes with the aging time.
Taking the six-transistor standard SRAM used most as an example, SRAM cells are basically two ring-connected inverters. Four transistors constitute a bi-stable latch to store 1bit of high and low level data. When the sram array is powered up, initially each individual memory cell randomly acquires a high or low potential. Since the individual memory cells of the sram are designed, each pair of matched transistors is completely symmetrical with layout-dependent parasitic elements. Thus, ideally, each sram cell should be given a high or low level with the possibility of thinking etc. at power-up, with the actual value being determined by the random unbiased noise.
The threshold voltage difference in each pair of P-type and N-type MOS transistors may result in cell biasing in the same direction or in opposite directions. Random unbiased noise determines whether the bias is high or low at power up. The larger net imbalance in the MOS transistor pair results in a more unbalanced sram cell power-up ratio.
If the net threshold voltage difference is small, the potential values will still be randomly biased to a high level or a low level, but for a relatively large net threshold voltage imbalance the potential state will be stable and will always be the same over multiple power-up cycles, and the entire memory module will show more bias to a high level or a low level.
From the above knowledge, we can see that after the power-on of a completely new sram, the distribution of logic high or low in the memory is approximately the same. Considering the transistor characteristic of aging effect, any difference in storage time can cause asymmetric shift of threshold voltage of transistor in memory cell, and thus change of power-on bias of memory cell.
Many static random access memories, such as Block Random Access Memories (BRAMs) in FPGAs, are initialized to 0, which again increases the proportion of time a memory cell is stressed in a low state.
The monitoring of the aging time of an integrated circuit in the present invention is based on the inevitable offset in the percentage of high and low levels when powering up when using static random access memory. The magnitude of the value offset from the initial reference value may have a function value corresponding to the usage time, where the corresponding relationship is not a function mapping relationship but a threshold value corresponding relationship.
The aging parameters of the read-write module mainly comprise the number of bits of error transmission caused by aging effect and clock changes such as clock trigger time of a digital circuit, power-on time of the digital circuit and the like. The read-write module aging characteristic data is used for judging whether the static random access memory participating in the simulation is completely aged or not.
In step 1, the aging detection simulation starts from a brand-new sram until the sram is completely aged, wherein any one of the following conditions is satisfied, that is, the sram is considered to be completely aged:
1) the rising edge or falling edge time is prolonged by 30 percent;
2) the whole time sequence time is prolonged by 15%;
3) the read-write speed is reduced by 20%;
4) the average number of error bits in continuous reading and writing for a period of time is above 1 bit.
The aging monitoring-predicting model provided by the invention comprises the following steps:
H = at 3+bt 2 + ct + H 0
t anticipation of= t Terminate -t
Wherein the content of the first and second substances,Hfor the high potential ratio (%) of the sram,tfor the aging time (days),ain order to influence the parameters with respect to temperature,bin order to be able to electromagnetically influence the parameter,cin order to influence the parameters of the humidity,H 0the high potential ratio of a brand-new static random access memory is realized without external factor interference;t anticipation ofThe expected remaining lifetime for the sram,t terminateThe life of the SRAM is the full cycle from use to complete aging.
FIG. 1 illustrates the variation of the high-voltage ratio with the number of operations when a certain type of SRAM is powered on. Fig. 2 is a graph illustrating the variation of the number of mistransmitted bits of a certain type of sram with the number of runs. It can be seen from the figure that, with the change of the operation times, the high potential ratio and the number of bits of mistransmission both change in a certain rule when the power is on.
The actual working environment of the target integrated circuit is a complex environment, namely a high-temperature, high-humidity or electromagnetic interference environment; wherein the high temperature is 85 ℃ to 125 ℃; the high humidity refers to relative humidity of 70% to 90%; the electromagnetic interference means that the maximum measurable transient electric field intensity is not less than 50V/m, the electromagnetic measurement sensitivity is not more than 10mV/m, the maximum measurable transient magnetic field intensity is not less than 0.1A/m, the magnetic field measurement sensitivity is not more than 1mA/m, and the system field intensity measurement precision is better than +/-3 dB. The invention is suitable for the environment with one or more conditions existing in the complex environment at the same time, in particular for the complex environment with high temperature, high humidity and electromagnetic interference existing at the same time, and can still carry out accurate detection and prediction.
The invention is further described below with reference to a specific example.
Under the environment that the temperature is 90 ℃, the relative humidity is 75%, the electric field intensity is 75V/m, and the maximum measurable transient magnetic field intensity is not less than 0.15A/m, a 23K640T standard 6T type static random access memory module is tested, a target detection integrated circuit is an STM32F103ZET6 type single chip microcomputer, a 23K640T static random access memory of the same type is embedded, and when the read-write is carried out for 6 hours every day, the average read-write intensity is 8192Byte every 10 minutes, an aging monitoring-forecasting model is obtained:
H = 0.0071t 3- 0.1501t 2+ 1.0905t + 48.954
R² = 0.9959
t anticipation of= t Terminate -t。
The high potential logic ratio collected when the aging device runs on the 1 st day is 50.0%, and the aging time corresponding to the aging parameter model with the high potential logic ratio of 50.0% is 1.12 days; the aging time corresponding to the aging parameter model with the high potential logic ratio of 51.7% is 7.86 days. The experimental data show that the prediction accuracy of the aging monitoring-prediction model is 100% in days, and the aging monitoring data of the integrated circuit in a complex environment can be effectively obtained.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.
Claims (9)
1. A non-intrusive complex environment integrated circuit aging monitoring method is characterized by comprising the following steps:
step 1: adopting the static random access memory with the same type as the static random access memory on the target integrated circuit to carry out aging detection simulation in a complex environment, collecting aging characteristic parameters, extracting aging characteristic data of a storage module and the aging characteristic data of a read-write module in the aging characteristic parameters, and establishing an aging monitoring-predicting model;
the storage module aging characteristic data is the number ratio of high level and low level of storage units when the storage module is powered on; the aging characteristic data of the read-write module comprises the bit number of error transmission, the clock trigger time of the digital circuit and the power-on time of the digital circuit;
step 2: for a target integrated circuit to be predicted, embedding an external simulation operation module to simulate the reading and writing of a static random access memory of the target integrated circuit, and setting the reading and writing of the external simulation operation module to be consistent with the static random access memory of the target integrated circuit so as to achieve the purpose of copying the operation state of the target integrated circuit; and the external module simulates to store or transmit the aging characteristic data in real time, compares the aging characteristic data with the aging monitoring-predicting model, and outputs the aging time and the expected life of the static random access memory of the target integrated circuit.
2. The method of claim 1, wherein the complex environment of step 1 is identical to the actual working environment of the target ic to be predicted in step 2, and the complex environment is one or more of high temperature, high humidity or strong electromagnetic interference environment.
3. The method of claim 2, wherein the high temperature is 85 ℃ to 125 ℃; the high humidity refers to relative humidity of 70% to 90%; the electromagnetic interference means that the maximum measurable transient electric field intensity is not less than 50V/m, the electromagnetic measurement sensitivity is not more than 10mV/m, the maximum measurable transient magnetic field intensity is not less than 0.1A/m, and the magnetic field measurement sensitivity is not more than 1 mA/m.
4. The method of claim 1, wherein the memory module comprises a plurality of memory cells, each memory cell randomly biased to a high level or a low level when powered up, and having substantially the same distribution of logic high levels or low levels when a new sram is powered up; as the sram is used, the percentage of high and low levels at power-up can shift, indicating a change in the ratio of the number of high and low levels of the memory cells at power-up.
5. The method of claim 1, wherein the aging monitor-predict model is as follows:
H = at 3+bt 2 + ct + H 0
t anticipation of= t Terminate -t
Wherein the content of the first and second substances,Hfor the high potential ratio (%) of the sram,tfor the aging time (days),ain order to influence the parameters with respect to temperature,bin order to be an electromagnetically influencing parameter,cin order to influence the parameters of the humidity,H 0the high potential ratio of a brand-new static random access memory is realized without external factor interference;t anticipation ofThe expected remaining life of the sram,t terminateThe life of the SRAM is the full cycle from the beginning of use to the complete aging.
6. The method as claimed in claim 1, wherein the external simulation operation module is a static random access memory of the same type that shares power and ground with a static random access memory of the ic to be tested, and further comprises a read/write module.
7. The method according to claim 6, wherein in step 2, the external simulation operation module is embedded into the target IC to be predicted before the target IC to be predicted is put into use;
the embedding method comprises the following steps: the external simulation operation module and the static random access memory of the integrated circuit to be tested share a power supply and a ground, namely the same power supply voltage is used in the same environment, the daily average read-write times under the normal use of the static random access memory of the target integrated circuit are extracted, the read-write frequency is calculated, and the aging characteristic data is stored.
8. The method according to claim 1, wherein in step 2, before comparing with the aging monitoring-prediction model, the method further comprises the step of determining whether the data stored or transmitted by the external simulation operation module is valid data, deleting invalid data and retaining valid data;
the criterion for judging whether the data is valid data is as follows: and in a period of continuous time, judging that the data acquired at a certain time point has a numerical deviation of more than 10% with the data acquired before and after, and judging that the data is invalid, otherwise, judging that the data is valid.
9. The method of claim 1 or 5, wherein in step 1, the burn-in detection simulation starts from a completely new SRAM until the SRAM is completely aged, wherein any one of the following conditions is satisfied, namely the SRAM is considered to be completely aged:
1) the time of the rising edge or the falling edge is prolonged by 30 percent;
2) the whole time sequence time is prolonged by 15%;
3) the read-write speed is reduced by 20%;
4) the average number of error bits in continuous reading and writing for a period of time is more than 1 bit;
the read-write module aging characteristic data is used for judging whether the static random access memory participating in the simulation is completely aged or not.
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