CN114698257A

CN114698257A - Packaging carrier plate with full-embedded precise circuit and processing technology thereof

Info

Publication number: CN114698257A
Application number: CN202210300495.4A
Authority: CN
Inventors: 刘臻祎; 马洪伟; 沈飞; 宗芯如
Original assignee: Jiangsu Punuowei Electronic Co ltd
Current assignee: Jiangsu Punuowei Electronic Co ltd
Priority date: 2022-03-25
Filing date: 2022-03-25
Publication date: 2022-07-01

Abstract

The application relates to a packaging carrier plate with full embedded precise line and a processing technology thereof, the processing technology comprises preparation of a substrate, a first buried line layer, preparation of filling a first insulating medium, a second buried line layer, preparation of repeatedly filling an insulating medium layer and the buried line layer, and preparation of an n buried line layer, wherein the preparation of the n buried line layer comprises insulation layer preparation, pattern reserved area preparation, conducting hole processing, seed layer preparation, preparation photosensitive pattern, pattern electroplating, film stripping, carrier layer removal and flash etching. The processing technology meets the requirement of double-sided precise circuit manufacturing, improves the reliability of the circuit, simultaneously improves the surface flatness of the carrier plate, and is beneficial to the improvement of the packaging technology and the performance of finished products.

Description

Packaging carrier plate with full-embedded precise circuit and processing technology thereof

Technical Field

The application relates to a package carrier, in particular to a package carrier with a full-embedded precise circuit and a processing technology thereof.

Background

With the continuous updating and iteration of the information era, the requirements on the functions of various chips are higher and higher, such as high-speed operation, high storage, high precision, high stability and the like, and correspondingly, the requirements on the packaging substrate are also higher and higher, such as high-density wiring, a thin plate, high flatness and the like; in the prior art, whether a masking process (Tenting) process or an improved semi-additive process (mSAP) process is adopted, a mainstream process or a process in which a copper surface is higher than an insulating medium is adopted, then surface ink coating is carried out, directional insulation is carried out between conductors and on the surfaces of the conductors, partial products with flatness requirements on a support plate can flatten the ink through an ink leveling process, the flatness requirements of the products are met, and the thickness of the obtained support plate and the line width and the distance of lines cannot meet the requirements.

Therefore, another process is a single-side wire embedding process, the existing end is mainly applied to the field of RF (radio frequency), and the product is mainly characterized in that the single-side wiring is dense, the other side is designed conventionally, and the embedding is not needed to carry out special protection on the graph; however, with the continuous development of the technology, the wiring design of the carrier board will become more and more complex and present an integration trend, and the demand for the double-sided precise circuit design configuration product becomes greater and greater, so that a technology for manufacturing the double-sided precise circuit is urgently needed to be developed.

Content of application

In order to overcome the defects, the application provides a processing technology of a packaging carrier plate based on a fully embedded precise circuit, the processing technology meets the requirement of double-sided precise circuit manufacturing, improves the reliability of the double-sided precise circuit, improves the surface flatness of the carrier plate, and is beneficial to the improvement of the packaging technology and the performance of a finished product.

The technical scheme adopted by the application for solving the technical problem is as follows:

a processing technology of a packaging carrier plate with a full-embedded precise circuit comprises the following steps:

step 1: preparing a substrate: preparing a substrate having a carrier layer and a copper foil layer;

step 2: manufacturing a first buried wire layer: manufacturing an embedded first buried wire layer on the copper foil layer in an image electroplating mode;

and step 3: filling an insulating medium: filling an insulating medium on the first buried line layer to form a first insulating medium layer;

and 4, step 4: manufacturing a second buried wire layer:

machining a through hole: processing a through hole in the first insulating medium layer;

manufacturing a seed layer: seed layers are manufactured on the surfaces of the first insulating medium layer and the through hole;

making a pattern circuit: manufacturing a second buried line layer on the seed layer;

and 5: repeating the steps 3 and 4 until an n-1 layer plate is formed, wherein n is more than or equal to 3 and is a natural number;

step 6: and (3) manufacturing an nth buried wire layer:

manufacturing an insulating layer: filling an insulating medium on the (n-1) th buried line layer to form an (n-1) th insulating medium layer;

making a reserved graphic area: half-etching is carried out on the n-1 insulating medium layer through a UV cold light processing technology to etch a pattern shape area which needs to be manufactured with a preset depth finally;

processing a conducting hole: processing the design position of the via hole in the (n-1) th insulating medium layer by a UV cold light processing technology to form the via hole, wherein the via hole is communicated to the (n-1) th buried line layer;

seed layer preparation: manufacturing seed layers on the surfaces of the n-1 th insulating medium layer, the pattern-shaped area and the via hole for conducting the whole board;

making a photosensitive pattern: sensitizing the seed layer in the fourth step to form a photosensitive layer, and exposing the pattern-shaped area and the via hole which need to be electroplated;

pattern electroplating: electroplating copper on the plate, filling copper in the via hole and forming an n-th buried wire layer on the exposed pattern-shaped area;

and removing the film: removing the residual photosensitive layer;

eighthly, polishing: grinding and polishing the plate after film removal to remove slight bumps on the surface;

ninthly, removing the carrier layer;

flash erosion of r: and etching the copper foil layer to expose the first buried wire layer on the copper foil layer, thereby completing the manufacture of the multilayer board with the precise circuits embedded in two sides.

Preferably, in step 1, the carrier layer and the copper foil layer are punched through around the working area of the substrate.

Preferably, drilling is carried out around the working area of the substrate to form a plurality of through holes communicating the carrier layer and the copper foil layer, and when the first insulating medium layer is pressed, the insulating medium flows into the through holes to bond the copper foil layer and the carrier layer together from the side wall.

Preferably, a groove is cut on the periphery of the working area of the substrate by utilizing a laser cutting process, the groove is communicated with the carrier layer and the copper foil layer, and when the first insulating medium layer is pressed, the insulating medium flows into the groove to combine the copper foil layer and the carrier layer together.

Preferably, a certain area is burned out around the working area of the substrate by using a laser process, so that the carrier layer is exposed, and when the first insulating medium layer is pressed, the insulating medium flows to the surface of the burned-out area of the carrier layer, so that the copper foil layer and the carrier layer are combined together.

Preferably, the step 2 specifically comprises the following processes:

pretreatment: cleaning and roughening the surface of the copper foil layer;

manufacturing a photosensitive layer: uniformly coating a photosensitive layer on the surface of the copper foil layer in a pressing or coating mode;

exposure: carrying out polymerization reaction on light and the photosensitive layer by an image transfer mode on a finished product pattern which is not required to be manufactured to form a pattern which cannot be removed by a developing solution but can be removed by a film stripping solution;

fourthly, developing: removing the photosensitive layer in the unreacted area and reserving the area with photopolymerization reaction;

pattern electroplating: electroplating the exposed area after development to form a required pattern circuit;

sixthly, membrane stripping: and removing the photosensitive layer to form a final first buried line layer.

Preferably, the first step in step 3 and step 6 specifically includes the following steps:

pretreatment: cleaning and roughening the surface of the pattern circuit layer to increase the bonding force between the circuit and the insulating medium and improve the product performance;

filling an insulating medium: and forming an insulating medium layer on the pattern circuit layer by a process of pressing or vacuum pressing together with baking.

Preferably, in the step 4, blind holes are manufactured by adopting laser windowing and laser drilling processes, and the alignment reference in the manufacturing process is a target hole with an inner target as the reference; or the blind hole is manufactured by adopting a laser direct blind hole forming process, and the alignment reference in the manufacturing process is an inner layer target; in the step 4 or the step 6, the seed layer is manufactured by a copper deposition process or a sputtering process; in the third step of the step 4 or the sixth step of the step 6, when the pattern is manufactured, the pattern build-up manufacturing is performed by adopting an additive method and pattern electroplating, a semi-additive method or a subtractive method and whole board electroplating and etching processes according to the pattern wiring density.

Preferably, in the sixth step 6, the upper surface of the nth buried line layer is 0-5 um lower than the upper surface of the (n-1) th insulating medium layer.

The application also provides a packaging carrier plate with the fully-embedded precise circuit, which is processed by adopting the processing technology.

The beneficial effect of this application is:

1) on the basis of the existing embedded line technology ETS (embedded Trace substrate) technology of the processing technology, UV laser is innovatively combined with the mSAP processing technology to embed the outermost line on the other side into the insulating layer, so that the purpose that all lines are embedded into the insulating layer is achieved;

2) the processing technology meets the requirement of manufacturing a multilayer board with double-sided precise circuits, improves the reliability of the multilayer board, improves the surface flatness of the carrier board, and is beneficial to the improvement of a packaging technology and the performance of a finished product;

3) the processing technology is suitable for the design that the minimum line width/line distance of the outer layer is 15 mu m/15 mu m, can meet the design requirement of a new packaging mode on double-sided fine lines of a substrate, and reduces the product defects caused by line flying and line breaking;

4) according to the carrier plate, the double-sided precise lines are embedded in the insulating medium, the bonding area between the fine lines and the surrounding medium layer is increased, the bonding force is increased, the performance stability of the fine lines is improved, electromagnetic crosstalk can be effectively reduced due to the fact that the lines are isolated by the PP insulating layer, and good line shielding performance can be widely applied to high-end smart phones and PC ends;

5) because the pattern circuit is embedded in the insulating medium layer, the double-sided flatness of the substrate is better than that of a conventional substrate, and after the substrate is covered with printing ink, the flatness is less than or equal to 3 mu m, and the requirement of sensitive IC packaging can be met.

Drawings

FIG. 1 is a schematic view of the construction of an n-1 laminate of the present application;

FIG. 2 is a schematic structural view of an n-1 laminate of the present application after forming a pattern-shaped region;

FIG. 3 is a schematic view of the structure of the n-1 laminate after via hole processing;

FIG. 4 is a schematic structural diagram of an n-1 laminate after a photosensitive layer is formed thereon;

FIG. 5 is a schematic structural view of an n-layer plate of the present application;

FIG. 6 is a schematic view of the structure of the n-layer plate of the present application with the photosensitive layer removed;

FIG. 7 is a schematic view of the n-layer substrate with the carrier layer removed;

FIG. 8 is a schematic view of the n-layer copper foil layer removed structure of the present application;

FIG. 9 is a schematic structural view of a finished panel of the present application;

in the figure: 10-substrate, 11-carrier layer, 12-copper foil layer, 13-first buried wire layer, 14-first insulating dielectric layer, 21-second buried wire layer, 22-nth-1 insulating dielectric layer, 23-graphic shape area, 24-photosensitive layer and 25-nth buried wire layer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the following drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Spatially relative terms, such as "above … …," "above … …," "above … … surface," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Example (b): a processing technology of a packaging carrier plate with a full-embedded precise circuit comprises the following steps:

step 1: preparing a substrate 10: preparing a substrate having a carrier layer 11 and a copper foil layer 12; the copper foil layer is an ultrathin copper foil layer;

step 2: manufacturing the first buried line layer 13: manufacturing an embedded first buried wire layer 13 on the copper foil layer 12 in an image electroplating mode;

and step 3: filling an insulating medium: filling an insulating medium on the first buried line layer 13 to form a first insulating medium layer 14;

and 4, step 4: manufacturing of the second buried line layer 21:

machining a through hole: processing a via hole in the first insulating medium layer 14;

manufacturing a seed layer: seed layers are manufactured on the surfaces of the first insulating medium layer 14 and the through hole;

making a pattern circuit: manufacturing a second buried line layer 21 on the seed layer;

and 5: repeating the steps 3 and 4 until an n-1 layer plate is formed, wherein n is more than or equal to 3 and is a natural number; the preparation of filling insulating media and wire embedding layers is repeated, a layer of plate is added every time steps 3 and 4 are repeated, a second insulating medium layer and a third wire embedding layer are manufactured when steps 3 and 4 are repeated for the first time, the required layers of multilayer plates are formed by parity of reasoning, and the uppermost layer is the n-1 th wire embedding layer; as shown in FIG. 1, an n-1 layer plate is formed at this time, and the third to n-1 buried layers and the insulating medium layer therebetween are omitted in the figure, the same is true below;

step 6: manufacturing of the nth buried layer 25:

manufacturing an insulating layer: filling an insulating medium on the (n-1) th buried line layer to form an (n-1) th insulating medium layer 22;

making a reserved graphic area: as shown in fig. 2, a UV cold light processing process is performed to half-etch the n-1 th insulating dielectric layer 22 to form a pattern-shaped area 23 with a predetermined depth;

processing a conducting hole: as shown in fig. 3, a UV cold light processing process is performed to process the design position of the via hole in the n-1 th insulating medium layer 22 to form a via hole, and the via hole is communicated to the n-1 th buried line layer;

making a photosensitive pattern: as shown in fig. 4, the seed layer in (iv) is photosensitive to form a photosensitive layer 24, and the pattern-shaped area and the via hole to be plated are exposed;

sixthly, pattern electroplating: as shown in fig. 5, the plate is electroplated with copper, the via hole is filled with copper, and an nth buried layer 25 is formed on the exposed pattern-shaped area;

and removing the film: as shown in fig. 6, the remaining photosensitive layer is removed;

and eighthly, polishing: grinding and polishing the plate after film removal to remove slight bumps on the surface;

ninthly, removing the carrier layer 11; as shown in fig. 7, the carrier layer can be removed by peeling;

flash erosion of r: as shown in fig. 8, the copper foil layer 12 is etched away to expose the first buried wire layer 13 on the copper foil layer, thereby completing the fabrication of a multilayer board with precision wires embedded on both sides. According to the design requirement of a product, the post-manufacturing process comprises the following steps: solder mask → surface treatment → molding → product testing → product inspection → package shipment, as shown in fig. 9, a finished board is formed, and the final product is the package carrier.

In step 1, the carrier layer 11 and the copper foil layer 12 are punched through around the working area of the substrate 10 by the following three methods:

the method comprises the following steps: the periphery of the working area of the substrate 10 is drilled to form a plurality of through holes for communicating the carrier layer 11 and the copper foil layer 12, and when the first insulating medium layer 14 is pressed, the insulating medium flows into the through holes to bond the copper foil layer 12 and the carrier layer 11 together from the side wall.

The second method comprises the following steps: a laser cutting process is used to cut a groove around the working area of the substrate 10, the groove connects the carrier layer 11 and the copper foil layer 12, when the first insulating medium layer 14 is pressed, the insulating medium flows into the groove, and the copper foil layer 12 and the carrier layer 11 are combined together.

The third method comprises the following steps: a certain area is burnt out around the working area of the substrate 10 by using a laser process to expose the carrier layer 11, and when the first insulating medium layer 14 is pressed, the insulating medium flows to the surface of the burnt-out area of the carrier layer to combine the copper foil layer 12 and the carrier layer 11 together.

By utilizing the three processes, the edge of the working area of the substrate is isolated, and the ultrathin copper foil layer is combined with the carrier layer 11 through the first insulating medium, so that the ultrathin copper foil layer can be prevented from being separated due to the attack of external force or liquid medicine in the production process.

The step 2 specifically comprises the following processes:

pretreatment: cleaning and roughening the surface of the copper foil layer 12;

sixthly, membrane stripping: the photosensitive layer is removed to form the final first buried line layer 13.

The first step in the step 3 and the step 6 specifically comprises the following processes:

pretreatment: cleaning and roughening the surface of the pattern circuit layer to increase the bonding force between the circuit and the insulating medium and improve the product performance; the graphic circuit layers are first, second and third … buried wire layers, if the final carrier plate is a three-layer plate, the graphic circuit layers are the first buried wire layer and the second buried wire layer, if the final carrier plate is a four-layer plate, the graphic circuit layers are the first and second buried wire layers, and so on.

Filling an insulating medium: and forming an insulating medium layer on the pattern circuit layer by a process of pressing or vacuum pressing together with baking. The process of filling the insulating medium is not limited to the above two ways as long as the processing characteristics of the insulating medium are matched.

In the step 4, blind holes are manufactured by adopting laser windowing and laser drilling processes, and the alignment reference in the manufacturing process is a target hole with an inner target as the reference; or the blind hole is manufactured by adopting a laser direct blind hole forming process, and the alignment reference in the manufacturing process is an inner layer target; in the step 4 or the step 6, the seed layer is manufactured by a copper deposition process or a sputtering process; in the third step of the step 4 or the sixth step of the step 6, when the pattern is manufactured, the pattern build-up manufacturing is performed by adopting an additive method and pattern electroplating, a semi-additive method or a subtractive method and whole board electroplating and etching processes according to the pattern wiring density. The blind hole processing method is not limited to Laser windowing and Laser Drilling or LDD (Laser Direct Drilling, Laser Direct blind hole formation); the seed layer is not limited to a copper deposition process and a sputtering process, and the same conduction function can be realized; the pattern wiring is not limited to the additive method or the subtractive method, and the patterning may be performed, wherein the additive method, the pattern plating, the semi-additive method, the subtractive method, the whole plate plating, and the etching are conventional processes in the art, and will not be described in detail herein.

In the sixth step 6, the upper surface of the nth buried line layer 25 is 0-5 um lower than the upper surface of the n-1 th insulating medium layer. The distance between the highest interface of the copper surface and the highest interface of the insulating medium needs to be controlled to be 0-5 um during manufacturing, on one hand, the phenomenon that the top of a circuit graph is irregular due to the fact that the height of an electroplating graph is higher than that of the insulating medium is prevented, on the other hand, the copper surface is controlled to be lower than the insulating medium and cannot exceed certain limit, and the adverse effect on a sealing and measuring process is prevented.

As shown in fig. 9, a package carrier with fully embedded precise circuits is manufactured by the above processing process.

It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A processing technology of a packaging carrier plate with a full-embedded precise circuit is characterized in that: the method comprises the following steps:

step 1: preparing a substrate (10): preparing a substrate having a carrier layer (11) and a copper foil layer (12);

step 2: manufacturing a first buried line layer (13): manufacturing an embedded first wire embedding layer (13) on the copper foil layer (12) in an image electroplating mode;

and step 3: filling an insulating medium: filling an insulating medium on the first buried line layer (13) to form a first insulating medium layer (14);

and 4, step 4: and manufacturing a second buried line layer (21):

conducting hole processing: processing a via hole in the first insulating medium layer (14);

manufacturing a seed layer: manufacturing seed layers on the surfaces of the first insulating medium layer (14) and the through hole;

making a pattern circuit: manufacturing a second buried line layer (21) on the seed layer;

step 6: and (2) manufacturing an n-th buried line layer (25):

manufacturing an insulating layer: filling an insulating medium on the (n-1) th buried line layer to form an (n-1) th insulating medium layer (22);

making a reserved graphic area: half-etching is carried out on the n-1 insulating medium layer (22) through a UV cold light processing technology to etch a pattern shape area (23) which needs to be manufactured with a preset depth finally;

processing a conducting hole: processing the design position of a via hole in the (n-1) th insulating medium layer (22) through a UV cold light processing technology to form the via hole, wherein the via hole is communicated to the (n-1) th buried wire layer;

making a photosensitive pattern: performing sensitization on the seed layer in the fourth step to form a photosensitive layer (24), and exposing a pattern-shaped area to be electroplated and a via hole;

sixthly, pattern electroplating: electroplating copper on the plate, filling copper in the via hole and forming an n-th buried wire layer (25) on the exposed pattern-shaped area;

removing the film: removing the residual photosensitive layer;

ninthly, removing the carrier layer (11);

flash erosion of r: and etching the copper foil layer (12) to expose the first wire-burying layer (13) on the copper foil layer, thereby completing the manufacture of the multilayer board with the precise circuits embedded in the two sides.

2. The process for manufacturing a package carrier with a fully embedded precision circuit according to claim 1, wherein: in step 1, the carrier layer (11) and the copper foil layer (12) are punched through around the working area of the substrate (10).

3. The process for manufacturing a package carrier with a fully embedded precision circuit according to claim 2, wherein: and drilling holes around the working area of the substrate (10) to form a plurality of through holes for communicating the carrier layer (11) and the copper foil layer (12), wherein when the first insulating medium layer (14) is pressed, the insulating medium flows into the through holes, and the copper foil layer (12) and the carrier layer (11) are combined together from the side wall.

4. The process for manufacturing a package carrier with a fully embedded precision circuit according to claim 2, wherein: a groove is cut on the periphery of a working area of the substrate (10) by utilizing a laser cutting process, the groove is communicated with the carrier layer (11) and the copper foil layer (12), when the first insulating medium layer (14) is pressed, the insulating medium flows into the groove, and the copper foil layer (12) and the carrier layer (11) are combined together.

5. The process for manufacturing a package carrier with a fully embedded precision circuit according to claim 2, wherein: a certain area is burnt out around the working area of the substrate (10) by utilizing a laser process, so that the carrier layer (11) is exposed, and when the first insulating medium layer (14) is pressed, the insulating medium flows to the surface of the burnt-out area of the carrier layer, so that the copper foil layer (12) and the carrier layer (11) are combined together.

6. The process for manufacturing a package carrier with a fully embedded precision circuit according to claim 1, wherein: the step 2 specifically comprises the following processes:

pretreatment: cleaning and roughening the surface of the copper foil layer (12);

fourthly, developing: removing the photosensitive layer of the unreacted area and reserving the area with photopolymerization reaction;

sixthly, membrane stripping: the photosensitive layer is removed to form a final first buried line layer (13).

7. The process of claim 1, wherein the process comprises the steps of: the first step in the step 3 and the step 6 specifically comprises the following processes:

8. The process for manufacturing a package carrier with a fully embedded precision circuit according to claim 1, wherein: in the step 4, blind holes are manufactured by adopting laser windowing and laser drilling processes, and the alignment reference in the manufacturing process is a target hole with an inner target as the reference; or the blind hole is manufactured by adopting a laser direct blind hole forming process, and the alignment reference in the manufacturing process is an inner layer target; in the step 4 or the step 6, the seed layer is manufactured by a copper deposition process or a sputtering process; in the third step of the step 4 or the sixth step of the step 6, when the pattern is manufactured, the pattern build-up manufacturing is performed by adopting an additive method and pattern electroplating, a semi-additive method or a subtractive method and whole board electroplating and etching processes according to the pattern wiring density.

9. The process for manufacturing a package carrier with a fully embedded precision circuit according to claim 1, wherein: in the sixth step 6, the upper surface of the nth buried line layer (25) is 0-5 um lower than the upper surface of the (n-1) th insulating medium layer.

10. A package carrier with full embedded precise circuit is characterized in that: processed by the process of any one of claims 1-9.