CN114678381A - Substrate for testing flat panel detector and testing method thereof - Google Patents
Substrate for testing flat panel detector and testing method thereof Download PDFInfo
- Publication number
- CN114678381A CN114678381A CN202210317042.2A CN202210317042A CN114678381A CN 114678381 A CN114678381 A CN 114678381A CN 202210317042 A CN202210317042 A CN 202210317042A CN 114678381 A CN114678381 A CN 114678381A
- Authority
- CN
- China
- Prior art keywords
- testing
- substrate
- flat panel
- thin film
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 189
- 239000000758 substrate Substances 0.000 title claims abstract description 93
- 238000001514 detection method Methods 0.000 claims abstract description 25
- 230000002093 peripheral effect Effects 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims description 55
- 239000002184 metal Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000004044 response Effects 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 description 18
- 230000008569 process Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 3
- 102100032282 26S proteasome non-ATPase regulatory subunit 14 Human genes 0.000 description 2
- 101100406366 Caenorhabditis elegans pad-2 gene Proteins 0.000 description 2
- 101000590281 Homo sapiens 26S proteasome non-ATPase regulatory subunit 14 Proteins 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Automation & Control Theory (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention discloses a substrate for testing a flat panel detector and a testing method thereof, the embodiment of the invention carries out characteristic testing on TFTs in the whole testing area, and compared with the prior art that TFT characteristic testing is carried out in the peripheral area of the periphery of the detecting area by adopting a TFT testing key (Teg), the invention can obtain real and effective I-V data of the TFTs in the AA area, thereby truly and accurately reflecting the IV characteristic of the TFTs in the AA area and effectively avoiding the problem of inaccurate testing data of the Teg area in the prior art; in addition, the detection area in the embodiment of the invention only manufactures the TFT and the voltage line for testing, and the test response speed is higher.
Description
Technical Field
The invention relates to the technical field of photoelectric detection, in particular to a substrate for testing a flat panel detector and a testing method thereof.
Background
The X-ray detection technology is widely applied to the fields of industrial nondestructive detection, container scanning, circuit board inspection, medical treatment, security protection, industry and the like, and has wide application prospect. The traditional X-Ray imaging technology belongs to analog signal imaging, and has low resolution and poor image quality. The X-ray digital imaging technology adopts an X-ray flat panel detector to directly convert an X-ray image into a digital image, and has been widely developed and applied because the converted digital image is clear, high in resolution, and easy to store and transmit.
The X-ray flat panel detector generally includes a Thin Film Transistor (TFT) and a photodiode. Under the irradiation of X-rays, a scintillator layer or a phosphor layer of an indirect conversion type X-ray flat panel detector converts X-ray photons into visible light, then the visible light is converted into an electric signal under the action of a photodiode, finally the electric signal is read through a TFT and output, the electric signal forms a digital signal after A/D conversion, and a computer performs image processing on the digital signal to form an X-ray digital image.
During the design and manufacture of the flat Panel detector, a TFT Teg test key (Testkey) is usually counted outside the Panel peripheral AA area to monitor the relevant characteristics of the AA area pixel TFT. However, in the actual production process, due to the differences of the positions of the Teg area and the AA area, the pattern density and the like, and the influence of the processes such as etching and the like, the characteristics of the TFTs in the Teg area and the AA area are different.
Disclosure of Invention
The embodiment of the invention provides a substrate for testing a flat panel detector and a testing method thereof, which are used for solving the problem that the characteristics of TFTs (thin film transistors) in a Teg area and an AA area are different when the characteristics of the TFTs of the flat panel detector are tested.
The embodiment of the invention provides a substrate for testing a flat panel detector, which comprises a substrate base plate, wherein the substrate base plate is provided with a testing area and a peripheral area arranged around the testing area, and the testing area comprises a plurality of grid lines and a plurality of data lines which are positioned on the substrate base plate; the plurality of grid lines and the plurality of data lines are crossed to define a plurality of detection regions, and each detection region comprises a thin film transistor;
the testing metal layer comprises a plurality of testing voltage wires, and the testing voltage wires are electrically connected with the source electrode of the thin film transistor.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the metal layer for testing further includes a light shielding portion electrically connected to the voltage line for testing, and an orthogonal projection of the light shielding portion on the substrate covers an orthogonal projection of an active layer of the thin film transistor on the substrate.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, an orthographic projection of the light shielding portion on the substrate further covers an orthographic projection of a source of the thin film transistor on the substrate, and the testing voltage line is electrically connected to the source through the light shielding portion.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the substrate further includes an insulating layer located between the thin film transistor and the metal layer for testing, and the light shielding portion is electrically connected to the source through a via hole penetrating through the insulating layer.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the testing voltage line and the light shielding portion are integrated into a single structure.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the extension direction of the test voltage line is the same as the extension direction of the data line.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the sources of the thin film transistors in the same column are electrically connected to the same testing voltage line, and the sources of the thin film transistors in different columns are electrically connected to different testing voltage lines.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the light shielding portions correspond to the thin film transistors one to one.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the substrate further includes a test signal input terminal located in the peripheral region, and all the test voltage lines are electrically connected to the same test signal input terminal.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the substrate further includes a gate signal input terminal located in the peripheral region, and all the gate lines are electrically connected to the same gate signal input terminal.
Optionally, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, the substrate further includes a data signal input terminal located in the peripheral region, and all the data lines are electrically connected to the same data signal input terminal.
Correspondingly, an embodiment of the present invention further provides a method for testing a substrate for a flat panel detector, where the substrate for a flat panel detector is the substrate for a flat panel detector described in any one of the above embodiments, and the method includes:
and simultaneously loading grid signals to all grid lines, simultaneously loading test voltage signals to all test voltage lines, and reading the electric signals output by the thin film transistor through the data line so as to judge the electrical characteristics of the thin film transistor.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a substrate for testing a flat panel detector and a testing method thereof, wherein a Thin Film Transistor (TFT) is manufactured in each detection area in a testing area (AA) of a substrate, and a testing voltage wire electrically connected with a source electrode of the TFT is manufactured, so that when the characteristics of the TFT are tested, a grid signal can be loaded to all grid lines, a testing signal is loaded to all testing voltage wires, then an electric signal (current) output by the TFT is read through a data wire, whether the characteristics of the TFT are normal (whether the characteristics accord with an I-V curve of the TFT) is judged through the electric signal, if the characteristics of the TFT are normal, then when the flat panel detector is manufactured, a thin film transistor process for manufacturing the testing substrate can be adopted to manufacture the flat panel detector, if the characteristics of the TFT are abnormal, a problem is judged in which step when the TFT is manufactured, and therefore when the flat panel detector is manufactured subsequently, the problematic steps are optimized so that the characteristics of the fabricated TFT are good. Because the embodiment of the invention tests the characteristics of the TFTs in the whole test area, compared with the prior art that the TFT Teg is adopted to test the characteristics of the TFTs in the peripheral area of the detection area, the invention can obtain real and effective I-V data of the TFTs in the AA area, thereby truly and accurately reflecting the IV characteristics of the TFTs in the AA area and effectively avoiding the problem of inaccurate test data of the Teg area in the prior art; in addition, the detection area in the embodiment of the invention only manufactures the TFT and the voltage line for testing, and the test response speed is higher.
Drawings
Fig. 1 is a schematic plan view illustrating a substrate for testing a flat panel detector according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the structure of four detection zones in FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along direction CC' of FIG. 2;
FIG. 4 is a schematic structural diagram of a thin film transistor in a substrate for testing a flat panel detector according to an embodiment of the present invention;
fig. 5 is a schematic view of a detection zone of fig. 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It should be apparent that the described embodiments are only some of the embodiments of the present invention, and not all of them. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the word "comprise" or "comprises", and the like, in the context of this application, is intended to mean that the elements or items listed before that word, in addition to those listed after that word, do not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "inner", "outer", "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
The embodiment of the invention provides a substrate for a flat panel detector, as shown in fig. 1-3, fig. 1 is a schematic plane view of the substrate for the flat panel detector, fig. 2 is a schematic specific structure view of four detection regions P in fig. 1, fig. 3 is a schematic cross-sectional view along the CC' direction in fig. 2, the substrate for the flat panel detector comprises a substrate 1, the substrate 1 has a test region AA and a peripheral region BB arranged around the test region AA, the test region AA comprises a plurality of gate lines G and a plurality of data lines D on the substrate 1; a plurality of detection regions P are defined by the intersection of the plurality of grid lines G and the plurality of data lines D, and each detection region P comprises a thin film transistor 2;
the testing device further comprises a testing metal layer 3 which is positioned on one side of the thin film transistor 2 far away from the substrate base plate 1, wherein the testing metal layer 3 comprises a plurality of testing voltage wires T, and the testing voltage wires T are electrically connected with the source electrode 21 of the thin film transistor 2.
In the substrate for testing the flat panel detector provided by the embodiment of the invention, the Thin Film Transistor (TFT) is manufactured in each detection area in the test area (AA) of the substrate, and the test voltage line electrically connected with the source electrode of the thin film transistor is manufactured, so that when the characteristics of the TFT are tested, a gate signal can be loaded to all gate lines, a test signal is loaded to all test voltage lines, then an electrical signal (current) output by the TFT is read through the data line, whether the characteristics of the TFT are normal (whether the characteristics accord with the I-V curve of the TFT) is judged through the electrical signal, if the characteristics of the TFT are normal, the flat panel detector can be manufactured by adopting the thin film transistor process in the substrate for manufacturing the flat panel detector subsequently, if the characteristics of the TFT are abnormal, a problem is judged in which step when the TFT is manufactured, and thus when the flat panel detector is manufactured subsequently, the problematic steps are optimized so that the characteristics of the fabricated TFT are good. Because the embodiment of the invention tests the characteristics of the TFTs in the whole test area, compared with the prior art that the TFT test key (Teg) is adopted to test the characteristics of the TFTs in the peripheral area of the detection area, the invention can obtain real and effective I-V data of the TFTs in the AA area, thereby truly and accurately reflecting the IV characteristics of the TFTs in the AA area and effectively avoiding the problem of inaccurate test data in the Teg area in the prior art; in addition, the detection area in the embodiment of the invention is only provided with the TFT and the test voltage line, so that the test response speed is higher.
Specifically, in the substrate for testing the flat panel detector provided by the embodiment of the invention, the manufacturing process of the thin film transistor is consistent with the mass production process flow in the prior art, and only 1 Mask design of the metal layer for testing is added, so that the cost is low.
Specifically, in the substrate for testing the flat panel detector provided by the embodiment of the invention, a large-size sample can be tested, so that the back-end test operation is facilitated.
Specifically, to illustrate the structures of the thin film transistor 2 and the test voltage line T of each of the detection regions P clearly, as shown in fig. 4 and 5, fig. 4 is a structure of the thin film transistor 2 of one detection region P, and fig. 5 is a structure of the thin film transistor 2 and the test voltage line T of one detection region P.
In a specific implementation, in the substrate for testing a flat panel detector according to an embodiment of the present invention, as shown in fig. 3 to 5, the testing metal layer 3 further includes a light shielding portion 31 electrically connected to the testing voltage line T, and an orthographic projection of the light shielding portion 31 on the substrate 1 covers an orthographic projection of the active layer 22 of the thin film transistor 2 on the substrate 1. The light shielding portion 31 can shield the active layer 22, thereby reducing the influence of light on the active layer 22 and improving the stability of the thin film transistor 2.
In a specific implementation, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, as shown in fig. 3 and 5, an orthogonal projection of the light shielding portion 31 on the substrate 1 further covers an orthogonal projection of the source 21 of the thin film transistor 2 on the substrate 1, and the testing voltage line T is electrically connected to the source 21 through the light shielding portion 31; the thin film transistor device further comprises an insulating layer 4 positioned between the thin film transistor 2 and the metal layer 3 for testing, and the light shielding part 31 is electrically connected with the source 21 through a via hole penetrating through the insulating layer 4. Thus, the test voltage line T can supply the test signal to the source electrode 21 through the light shielding portion 31.
In a specific implementation, in the substrate for testing a flat panel detector according to the embodiment of the present invention, as shown in fig. 3 and 5, the testing voltage line T and the light shielding portion 31 are integrated. Thus, the patterns of the light shielding portion 31 and the testing voltage line T can be formed by one-time composition process only by changing the original composition pattern when the testing voltage line T is formed, and the process for separately preparing the light shielding portion 31 is not required to be added, so that the preparation process flow can be simplified, the production cost can be saved, and the production efficiency can be improved.
Specifically, as shown in fig. 5, in order to simplify the manufacturing process, the light shielding portion 31 may be directly designed in a square shape to completely shield the thin film transistor 2.
In a specific implementation, in the substrate for testing a flat panel detector according to the embodiment of the invention, as shown in fig. 2 and 5, the testing voltage line T may extend in the same direction as the data line D.
In a specific implementation, in the substrate for testing a flat panel detector according to the embodiment of the present invention, as shown in fig. 1 and fig. 2, the sources 21 of the thin film transistors 2 in the same column are electrically connected to the same testing voltage line T, and the sources of the thin film transistors 2 in different columns are electrically connected to different testing voltage lines T. Therefore, the number of the voltage lines T for testing can be reduced, and the manufacturing process is simplified.
In specific implementation, in the substrate for testing a flat panel detector provided in the embodiment of the present invention, as shown in fig. 2 and 5, the light shielding portions 31 correspond to the thin film transistors 2 one to one, so that all the thin film transistors 2 are prevented from being illuminated, and stability of all the thin film transistors 2 is ensured.
Specifically, as shown in fig. 2 to 5, the thin film transistor 2 further includes a gate electrode 23, a drain electrode 24, and a gate insulating layer 5 between the gate electrode 23 and the active layer 22, the gate line G is electrically connected to the gate electrode 23, and the data line D is electrically connected to the drain electrode 24.
In a specific implementation, as shown in fig. 1, the substrate for testing a flat panel detector further includes a test signal INPUT terminal INPUT1 located in the peripheral area BB, and all the test voltage lines T are electrically connected to the same test signal INPUT terminal INPUT 1. Thus, the test signal can be INPUT to all the test voltage lines T through the test signal INPUT terminal INPUT1 to be transmitted to the source electrode 21 of the thin film transistor 2.
Specifically, as shown in fig. 1, all the test voltage lines T may be drawn from below the substrate base plate 1 to be electrically connected to the same metal line 6, and then the metal line 6 is electrically connected to the test signal INPUT terminal INPUT1, that is, all the test voltage lines T are electrically connected to each other, and when the gate of the thin film transistor 2 is turned on, the test voltage signal is simultaneously INPUT to all the test voltage lines T through the test signal INPUT terminal INPUT1, so that a voltage difference is generated between the source 21 and the drain 24 of the thin film transistor 2.
In a specific implementation, as shown in fig. 1, the substrate for testing a flat panel detector further includes a gate signal INPUT terminal INPUT2 located in the peripheral area BB, and all gate lines G are electrically connected to the same gate signal INPUT terminal INPUT 2. Specifically, all the gate lines G can be led out to the bonding area on the left side of the substrate 1, since the invention is mainly used for testing large-sized products, for example, the size of the substrate 1 is 43cm × 43cm, so that the number of the gate lines G is large (only a part of the gate lines G are illustrated in the invention), all the gate lines G can be divided into a plurality of areas, for example, 6 areas, each area includes a certain number of gate lines G, the gate lines G in each area are led out to the bonding area and electrically connected with the same bonding pad (pad), the gate lines G in different areas are led out to the bonding areas and electrically connected with different bonding pads (pads), for example, fig. 1 in the embodiment of the invention only shows two areas, wherein the gate line G in one area is electrically connected with the first pad1, the gate line G in the other area is electrically connected with the second pad2, the first pad1 is electrically connected with the second pad2 through the first conductive connection portion 7, thus, all gate lines G can be electrically connected to the same gate signal INPUT terminal INPUT2, i.e., all gate lines G are electrically connected to each other, so that a gate signal is simultaneously INPUT to all gate lines G through the gate signal INPUT terminal INPUT2 to simultaneously turn on or off all TFTs in the test area AA.
In a specific implementation, as shown in fig. 1, the substrate for testing a flat panel detector further includes a data signal INPUT terminal INPUT3 located in the peripheral area BB, and all data lines D are electrically connected to the same data signal INPUT terminal INPUT 3. Specifically, all the data lines D can be led out to the bonding area on the lower side of the substrate board 1, since the present invention is mainly used for testing large-sized products, for example, the size of the substrate board 1 is 43cm × 43cm, so the number of the data lines D is large (only part of the data lines D are illustrated in the present invention), all the data lines D can be divided into several areas, for example, 6 areas, each area includes a certain number of data lines D, the data lines D of each area are led out to the bonding area and electrically connected to the same bonding pad (pad), the data lines D of different areas are led out to the bonding area and electrically connected to different bonding pads (pads), for example, fig. 1 illustrates only two areas, wherein the data lines D of one area are electrically connected to the third pad3, the data lines D of the other area are electrically connected to the fourth pad4, the third pad3 and the fourth pad4 are electrically connected through the second conductive connection portion 8, thus, all the data lines D can be electrically connected to the same data signal INPUT terminal INPUT3, i.e., all the data lines D are electrically connected to each other for reading the electrical signals output from all the TFTs in the test area AA to determine the I-V characteristics of the TFTs.
It should be noted that the first conductive connection portion 7 and the second conductive connection portion 8 in the embodiment of the present invention may be made of metal, and the first conductive connection portion 7, the second conductive connection portion 8 and the test voltage line T may be made of the same layer of metal. Like this, only need change original composition figure when forming test voltage line T, can form the figure of first electrically conductive connecting portion 7, second electrically conductive connecting portion 8 and test voltage line T through composition technology once, need not increase the technology of preparing first electrically conductive connecting portion 7 and second electrically conductive connecting portion 8 alone, can simplify the preparation process flow, save manufacturing cost, improve production efficiency.
Specifically, as shown in fig. 1, in order to improve the routing uniformity of the bonding area, a floating electrode 9 is generally disposed in the blank area (dummy area).
The following describes a method for testing characteristics of a thin film transistor by using a substrate for testing a flat panel detector according to an embodiment of the present invention.
As shown in fig. 1 and 2, a gate signal is simultaneously INPUT to all gate lines G through a gate signal INPUT terminal INPUT2 to simultaneously turn on all TFTs in the test area AA; the test signal INPUT terminal INPUT1 INPUTs a test voltage signal to all the test voltage lines T at the same time, so that a voltage difference is generated between the source 21 and the drain 24 of the TFT 2, and the electrical signals output by all the TFTs in the test area AA are read through the data line D to determine the electrical characteristics (I-V) of the TFTs.
Based on the same disclosure concept, the embodiment of the invention also provides a test method of the substrate for testing the flat panel detector, the substrate for testing the flat panel detector is the substrate for testing the flat panel detector provided by the embodiment of the invention, and the test method comprises the following steps:
and simultaneously loading grid signals to all grid lines, simultaneously loading test voltage signals to all test voltage lines, and reading the electric signals output by the thin film transistor through the data line so as to judge the electrical characteristics of the thin film transistor.
Specifically, the testing method of the substrate for testing a flat panel detector can be referred to the testing method of the substrate for testing a flat panel detector, and repeated details are not repeated herein.
The embodiment of the invention provides a substrate for testing a flat panel detector and a testing method thereof, wherein a Thin Film Transistor (TFT) is manufactured in each detection area in a testing area (AA) of a substrate, and a testing voltage line electrically connected with a source electrode of the TFT is manufactured, so that when the characteristics of the TFT are tested, grid signals can be loaded to all grid lines, testing signals are loaded to all testing voltage lines, then electric signals (current) output by the TFT are read through a data line, whether the characteristics of the TFT are normal (whether the characteristics accord with an I-V curve of the TFT or not) is judged through the electric signals, if the characteristics of the TFT are normal, a thin film transistor process in the manufacturing testing substrate can be adopted to manufacture the flat panel detector in the follow-up process of manufacturing the flat panel detector, if the characteristics of the TFT are abnormal, a problem is judged in which step of manufacturing the TFT, and if the characteristics of the TFT are abnormal, then when the flat panel detector is manufactured in the follow-up process of manufacturing, the problematic steps are optimized so that the characteristics of the fabricated TFT are good. Because the embodiment of the invention tests the characteristics of the TFTs in the whole test area, compared with the prior art that the TFT test key (Teg) is adopted to test the characteristics of the TFTs in the peripheral area of the detection area, the invention can obtain real and effective I-V data of the TFTs in the AA area, thereby truly and accurately reflecting the IV characteristics of the TFTs in the AA area and effectively avoiding the problem of inaccurate test data in the Teg area in the prior art; in addition, the detection area in the embodiment of the invention only manufactures the TFT and the voltage line for testing, and the test response speed is higher.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass these modifications and variations.
Claims (12)
1. The substrate for the flat panel detector test is characterized by comprising a substrate base plate, wherein the substrate base plate is provided with a test area and a peripheral area arranged around the test area, and the test area comprises a plurality of grid lines and a plurality of data lines which are positioned on the substrate base plate; the plurality of grid lines and the plurality of data lines are crossed to define a plurality of detection regions, and each detection region comprises a thin film transistor;
the testing metal layer comprises a plurality of testing voltage wires, and the testing voltage wires are electrically connected with the source electrode of the thin film transistor.
2. The substrate for testing flat panel detectors according to claim 1, wherein the metal layer for testing further comprises a light shielding portion electrically connected to the voltage line for testing, and an orthographic projection of the light shielding portion on the substrate covers an orthographic projection of the active layer of the thin film transistor on the substrate.
3. The substrate for testing flat panel detectors according to claim 2, wherein an orthographic projection of the light shielding portion on the substrate further covers an orthographic projection of a source electrode of the thin film transistor on the substrate, and the testing voltage line is electrically connected to the source electrode through the light shielding portion.
4. The substrate according to claim 3, further comprising an insulating layer between the thin film transistor and the test metal layer, wherein the light shielding portion is electrically connected to the source electrode through a via hole penetrating the insulating layer.
5. The substrate for testing flat panel detectors according to claim 2, wherein the testing voltage line is integrally formed with the light shielding portion.
6. The substrate for flat panel detector testing according to any of claims 1 to 5, wherein the testing voltage line and the data line extend in the same direction.
7. The substrate for testing flat panel detectors according to any of claims 1 to 5, wherein the sources of the thin film transistors in the same column are electrically connected to the same testing voltage line, and the sources of the thin film transistors in different columns are electrically connected to different testing voltage lines.
8. The substrate for testing flat panel detectors according to claim 7, wherein the light shielding portions correspond to the thin film transistors one to one.
9. The substrate according to any of claims 1-5, further comprising a test signal input terminal located in the peripheral region, wherein all of the test voltage lines are electrically connected to the same test signal input terminal.
10. The substrate according to any one of claims 1 to 5, further comprising a gate signal input terminal located in the peripheral region, wherein all the gate lines are electrically connected to the same gate signal input terminal.
11. The substrate according to any of claims 1 to 5, further comprising data signal input terminals located in the peripheral region, wherein all the data lines are electrically connected to the same data signal input terminal.
12. A method for testing a substrate for flat panel detector testing according to any one of claims 1 to 11, the method comprising:
and simultaneously loading grid signals to all grid lines, simultaneously loading test voltage signals to all test voltage lines, and reading the electric signals output by the thin film transistor through the data line so as to judge the electrical characteristics of the thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210317042.2A CN114678381A (en) | 2022-03-28 | 2022-03-28 | Substrate for testing flat panel detector and testing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210317042.2A CN114678381A (en) | 2022-03-28 | 2022-03-28 | Substrate for testing flat panel detector and testing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114678381A true CN114678381A (en) | 2022-06-28 |
Family
ID=82075538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210317042.2A Pending CN114678381A (en) | 2022-03-28 | 2022-03-28 | Substrate for testing flat panel detector and testing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114678381A (en) |
-
2022
- 2022-03-28 CN CN202210317042.2A patent/CN114678381A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103715212B (en) | Detection apparatus, detection system, and method for producing detection apparatus | |
| CN106096595A (en) | A kind of fingerprint recognition module, its manufacture method and fingerprint recognition display device | |
| CN206058227U (en) | A kind of fingerprint recognition module and fingerprint recognition display device | |
| JP2003066086A (en) | Testing device sensor and testing device | |
| JP5002007B2 (en) | Sensor element for inspecting conductor path structure, conductor path structure inspection apparatus, conductor path structure inspection method, and sensor element manufacturing method | |
| JP2009294204A (en) | Method and apparatus for testing a substrate for display, and substrate for the display and the display | |
| CN107680523B (en) | Method for detecting cross line defect of array substrate | |
| US11596062B2 (en) | Substrate motherboard and manufacturing method thereof, driving substrate and display device | |
| CN107167951A (en) | Display panel | |
| CN111682040B (en) | Detection substrate and radiation detector | |
| US20220077229A1 (en) | Display panel and detection method therefor, and display device | |
| US7488944B2 (en) | Radiation image detector | |
| JP2003255049A (en) | Light-detecting apparatus and radiation-detecting apparatus | |
| US20160223692A1 (en) | Digital X-Ray Detector and Method for Manufacturing the X-Ray Detector | |
| CN114678381A (en) | Substrate for testing flat panel detector and testing method thereof | |
| WO2019052268A1 (en) | Substrate and sensing method therefor, touch panel and display device | |
| CN109633731B (en) | Detector and manufacturing method thereof | |
| JP2009170768A (en) | Photosensor array substrate, and photosensor | |
| JPS62265688A (en) | Active matrix array | |
| CN109785745B (en) | Display device and repairing detection method thereof | |
| CN109920799B (en) | TFT panel and testing method | |
| CN104091804B (en) | A kind of array base palte and preparation method thereof, display device | |
| CN114566510B (en) | Detection panel, preparation method thereof and flat panel detector | |
| US20190164264A1 (en) | Method and system for diagnosing a semiconductor wafer | |
| JPH0950014A (en) | Inspection method for liquid crystal driving board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |