CN114677964A

CN114677964A - Shift register, grid drive circuit and display panel

Info

Publication number: CN114677964A
Application number: CN202210383706.5A
Authority: CN
Inventors: 阮敏
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2022-04-12
Filing date: 2022-04-12
Publication date: 2022-06-28
Anticipated expiration: 2042-04-12
Also published as: CN114677964B

Abstract

The application relates to a shift register, a grid driving circuit and a display panel. The shift register comprises a plurality of shift register units, wherein the plurality of shift register units share a first pull-down circuit, and each shift register unit further comprises a first output circuit and a second output circuit. The first shift register unit further comprises a third pull-down circuit and a pull-down holding circuit, the third pull-down circuit is connected with the first pull-up node, the first pull-down node and the second pull-down node, and the third pull-down circuit is used for initializing the first pull-up node under the control of the first pull-down node or the second pull-down node. The pull-down holding circuit is respectively connected with the third pull-down circuit and the first pull-down circuit, and the pull-down holding circuit is used for keeping the first pull-down node at a low potential when the first pull-down node is in a pull-down potential state. The requirement of a high-resolution narrow frame is met, and meanwhile potential fluctuation of the first pull-down node is prevented, so that the pull-down reliability of the shared first pull-down circuit is greatly improved.

Description

Shift register, grid drive circuit and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit and a display panel.

Background

The OLED gate driving circuit generally includes three sub-circuits, i.e., a detection unit, a display unit, and a connection unit (or gate circuit or Hiz circuit) for outputting a composite pulse of the detection unit and the display unit, but has a problem in that the circuit structure is very complicated and cannot meet the requirement of a high resolution and a narrow frame. A commonly used gate driving circuit includes a plurality of shift registers. Wherein the shift register unit includes: an input module to provide a first voltage signal to an output terminal in response to an input signal; the reset module is used for responding to the reset signal and providing a second voltage signal to a first node which is used as an output end in the input module; an output module supplying a first clock signal to an output terminal in response to a voltage of the first node; a pull-down control module for providing a second clock signal to the second node in response to the second clock signal, and providing a power supply negative voltage to the second node in response to a voltage of the first node or the output terminal; a pull-down module that provides a supply negative voltage to the first node and the output terminal in response to the voltage of the second node. The structure of the circuit can be simplified by sharing the first pull-down circuit, and the occupied space is saved, so that the requirement of a high-resolution narrow frame is met. However, in the implementation process, the inventor finds that the shift register unit sharing the first pull-down circuit at least has the technical problem of low pull-down reliability.

Disclosure of Invention

In view of the above, it is necessary to provide a shift register with high pull-down reliability, a gate driving circuit and a display panel, aiming at the technical problem of low pull-down reliability.

In order to achieve the above object, in one aspect, an embodiment of the present application provides a shift register, including a plurality of shift register units, the plurality of shift register units share a first pull-down circuit, and each shift register unit further includes a first output circuit and a second output circuit;

the first output circuit of each shift register unit is connected with the first output end of the corresponding shift register unit, the second output circuit of each shift register unit is connected with the second output end of the corresponding shift register unit, the first output end of each shift register unit is also connected with the first pull-down circuit through the first one-way isolating circuit, and the second output end of each shift register unit is also connected with the first pull-down circuit through the second one-way isolating circuit;

the plurality of shift register units comprise a first shift register unit and a second shift register unit, wherein a first output circuit of the first shift register unit is further connected with a first pull-up node and a first clock end, the first output circuit of the first shift register unit is used for controlling a first output end of the first shift register unit to output a first output signal according to the potential of the first pull-up node and a first clock signal of the first clock end, the second output circuit of the first shift register unit is further connected with the first pull-up node and a second clock end, and the second output circuit of the first shift register unit is used for controlling a second output end of the first shift register unit to output a second output signal according to the potential of the first pull-up node and a second clock signal of the second clock end;

the first output circuit of the second shift register unit is connected with the second pull-up node and the third clock end, the first output circuit of the second shift register unit is used for controlling the first output end of the second shift register unit to output a third output signal according to the potential of the second pull-up node and a third clock signal of the third clock end, the second output circuit of the second shift register unit is connected with the second pull-up node and the fourth clock end, and the second output circuit of the second shift register unit is used for controlling the second output end of the second shift register unit to output a fourth output signal according to the potential of the second pull-up node and the fourth clock signal of the fourth clock end;

the first shift register unit also comprises a third pull-down circuit and a pull-down holding circuit, wherein the third pull-down circuit is connected with the first pull-up node, the first pull-down node and the second pull-down node, and is used for initializing the first pull-up node under the control of the first pull-down node or the second pull-down node;

the pull-down holding circuit is respectively connected with the third pull-down circuit and the first pull-down circuit, and the pull-down holding circuit is used for keeping the first pull-down node at a low potential when the first pull-down node is in a pull-down potential state.

On the other hand, an embodiment of the present application further provides a gate driving circuit, which includes a plurality of shift registers as described above.

In another aspect, an embodiment of the present application further provides a display panel, including the gate driving circuit.

One of the above technical solutions has the following advantages and beneficial effects:

the shift register, the grid drive circuit and the display panel share the first pull-down circuit through the plurality of shift register units, the first output end of each shift register unit is also connected with the first pull-down circuit through the first unidirectional isolation circuit, the second output end of each shift register unit is also connected with the first pull-down circuit through the second unidirectional isolation circuit, so that the first output end and the second output end of each shift register unit are isolated from each other, the structure of the circuit can be simplified, the occupied space can be saved, the requirements of narrow frames can be met, meanwhile, pull-down holding circuits are additionally arranged at two ends of the first pull-down node, so that the first pull-down node is kept at a low potential when the first pull-down node is in a pull-down potential state, the first pull-down node is prevented from generating potential fluctuation, and the pull-down reliability of the shared first pull-down circuit is greatly improved, the influence on the normal operation of the circuit caused by the pull-down failure is avoided.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

FIG. 1 is a block diagram of a shift register sharing a first pull-down circuit;

FIG. 2 is a schematic circuit diagram of a shift register according to an embodiment;

fig. 3 is a schematic diagram of a specific circuit structure of the shift register in one embodiment.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "one end," "the other end," and the like are used herein for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In practical studies, the inventor finds that, in a conventional shift register unit sharing a first circuit, while sharing a first pull-down circuit, a requirement for the stability of the potential of the low potential at QB1 is imposed, that is, a fluctuation of the potential at QB1 will actually affect the pull-down function of the pull-down unit, which may cause a pull-down failure to affect the normal operation of the circuit, and the pull-down reliability is not high. In view of the above technical problems, the present application is directed to optimizing a gate driving circuit sharing a first pull-down circuit for meeting the requirement of a high resolution narrow bezel, and since the function of the shared first pull-down circuit may fail due to the fluctuation of the electric potential at the QB1 point, the present application adopts the technical idea of adding a new pull-down unit at the QB1 point, so as to maintain the low electric potential at the QB1 point when the pull-down function is used, thereby fundamentally solving the defect of stability of the pull-down function, optimizing the pull-down unit, and achieving the purpose of improving the pull-down reliability.

Fig. 1 is a block diagram of a shift register sharing a first pull-down circuit. As shown in fig. 2, the shift register 100 provided in the present application includes a plurality of shift register units 101, the plurality of shift register units 101 share a first pull-down circuit 11, wherein each shift register unit 101 further comprises a first output circuit 12 and a second output circuit 13, the first output circuit 12 of each shift register unit 101 is connected to the first output terminal OUT1 of the corresponding shift register unit 101, the second output circuit 13 of each shift register unit 101 is connected to the second output terminal OUT2 of the corresponding shift register unit 101, the first output terminal OUT1 of each shift register unit 101 is further connected to the first pull-down circuit 11 through the first unidirectional isolation circuit 14, and the second output terminal OUT2 of each shift register cell 101 is also connected to the first pull-down circuit 11 through the second unidirectional isolation circuit 15, so that the first output terminal OUT1 and the second output terminal OUT2 of each shift register cell 101 are isolated from each other.

It should be noted that the first unidirectional isolation circuit 14 and the second unidirectional isolation circuit 15 can be turned on in one direction, specifically, a node M is provided between the plurality of shift register units 101 and the first pull-down circuit 11, the first unidirectional isolation circuit 14 is turned on when the potential of the first output terminal OUT1 is higher than the potential of the node M, and the first unidirectional isolation circuit 14 is turned off when the potential of the first output terminal OUT1 is lower than the potential of the node M, and similarly, the second unidirectional isolation circuit 15 is turned on when the potential of the second output terminal OUT2 is higher than the potential of the node M, and the second unidirectional isolation circuit 15 is turned off when the potential of the second output terminal OUT2 is lower than the potential of the node M.

It should be further noted that a plurality of shift registers 100 are used to construct the gate driver circuit GOA, and a plurality of shift register units 101 in the shift registers 100 may be respectively located at different stages, i.e. respectively corresponding to a plurality of rows of pixels in the driving pixel circuit.

It is understood that, in the embodiment of the present invention, the first output terminal OUT1 and the second output terminal OUT2 of the shift register units 101 may be controlled to output respectively, for example, the shift register units 101 are controlled to output sequentially, and the first output terminal OUT1 and the second output terminal OUT 3832 of each shift register unit 101 are made to output high potential. In addition, after the outputs of the shift register units 101 are all completed, the first pull-down circuit 11 may be controlled to pull down the first output terminal OUT1 and the second output terminal OUT2 of the shift register units 101 at the same time, that is, the first output terminal OUT1 and the second output terminal OUT2 of the shift register units 101 are pulled down to the low potential at the same time through the first pull-down circuit 11.

The shift register 100 includes two shift register units 101, which is not the only limitation to the scope of the present invention (especially the number of actual shift register units). After reading the description of the present application, it is obvious to a person skilled in the art that the present application can be applied to a case where the shift register 100 includes three or more shift register units 101, for example, all shift register units can be divided into two types, one type of shift register unit including a pull-down holding circuit is referred to as a first shift register unit, and the rest is referred to as a second shift register unit.

Here, as an example, the two shift register units 101 in the shift register 100 may be respectively located at odd and even stages, that is, respectively correspond to the odd-row pixels and the even-row pixels in the driving pixel circuit.

As shown in fig. 2, the plurality of shift register units 101 includes a first shift register unit 101A and a second shift register unit 101B, the first output circuit 12A of the first shift register unit 101A is further connected to the first pull-up node Q1 and the first clock terminal CLKEA, the first output circuit 12A of the first shift register unit 101A is configured to control the first output terminal OUT1 of the first shift register unit 101A to output the first output signal according to the potential of the first pull-up node Q1 and the first clock signal of the first clock terminal CLKEA, the second output circuit 13A of the first shift register unit 101A is further connected to the first pull-up node Q1 and the second clock terminal CLKFA, the second output circuit 13A of the first shift register unit 101A is configured to control the second output terminal OUT2 of the first shift register unit 101A to output the second output signal according to the potential of the first pull-up node Q1 and the second clock signal of the second clock terminal CLKFA; the first output circuit 12B of the second shift register unit 101B is connected to the second pull-up node Q2 and the third clock terminal CLKEB, the first output circuit 12B of the second shift register unit 101B is configured to control the first output terminal OUT1 of the second shift register unit 101B to output the third output signal according to the potential of the second pull-up node Q2 and the third clock signal of the third clock terminal CLKEB, the second output circuit 13B of the second shift register unit 101B is connected to the second pull-up node Q2 and the fourth clock terminal fb, and the second output circuit 13B of the second shift register unit 101B is configured to control the second output terminal 2 of the second shift register unit 101B to output the fourth output signal according to the potential of the second pull-up node Q2 and the fourth clock signal of the fourth clock terminal CLKFB.

The first shift register unit 101A further includes a third pull-down circuit 17A and a pull-down hold circuit 30. The third pull-down circuit 17A is connected to the first pull-up node Q1, the first pull-down node QB1 and the second pull-down node QB2, and the third pull-down circuit 17A is configured to initialize the first pull-up node Q1 under the control of the first pull-down node QB1 or the second pull-down node QB 2. The pull-down holding circuit 30 is connected to the third pull-down circuit 17A and the first pull-down circuit 11, respectively, and the pull-down holding circuit 30 is configured to hold the first pull-down node QB1 at a low potential when the first pull-down node QB1 is in a pull-down potential state.

It is understood that when the first pull-up node Q1 is high and the first clock signal provided by the first clock terminal CLKEA is high, the first output circuit 12A of the first shift register unit 101A is turned on, and the high voltage provided by the first clock terminal CLKEA makes the first output terminal OUT1 of the first shift register unit 101A output high voltage. When the first pull-up node Q1 is high and the second clock signal provided by the second clock terminal CLKFA is high, the second output circuit 13A of the first shift register unit 101A is turned on, and the high voltage provided by the second clock terminal CLKFA makes the second output terminal OUT2 of the first shift register unit 101A output high voltage.

Similarly, when the second pull-up node Q2 is at a high level and the third clock signal provided by the third clock terminal CLKEB is at a high level, the first output circuit 12B of the second shift register unit 101B is turned on, and the high level provided by the third clock terminal CLKEB enables the first output terminal OUT1 of the second shift register unit 101B to output a high level. When the second pull-up node Q2 is high and the fourth clock signal provided by the fourth clock terminal CLKFB is high, the second output circuit 13B of the second shift register unit 101B is turned on, and the high level provided by the fourth clock terminal CLKFB makes the second output terminal OUT2 of the second shift register unit 101B output high level.

When the first pull-up node Q1 is at a high level, the level of the first pull-down node QB1 is pulled down to a low level, and the pull-down holding circuit 30 will always maintain the level of the first pull-down node QB1 at a low level during this period, so that the fluctuation of the level of the first pull-down node QB1 will not cause the low level state at this point to change, thereby ensuring that the pull-down function of the first pull-down node QB1 is not affected.

In some embodiments, the second shift register unit 101B further includes a fourth pull-down circuit 17B. The fourth pull-down circuit 17B is connected to the second pull-up node Q2, the first pull-down node QB1, and the second pull-down node QB 2. The fourth pull-down circuit 17B is configured to initialize the second pull-up node Q2 under the control of the first pull-down node QB1 or the second pull-down node QB 2.

When the first pull-down node QB1 or the second pull-down node QB2 is at a high level, the third pull-down circuit 17A of the first shift register unit 101A is turned on to initialize the first pull-up node Q1, i.e., pull down the potential of the first pull-up node Q1 to the potential (low level) of the third power supply VGL 1. Similarly, when the first pull-down node QB1 or the second pull-down node QB2 is at a high level, the fourth pull-down circuit 17B of the second shift register unit 101B is turned on to initialize the second pull-up node Q2, i.e., pull down the potential of the second pull-up node Q2 to the potential (low level) of the third power supply VGL 1.

It should be noted that "high" and "low" herein refer to two logic states represented by a range of potential heights at a certain circuit node position, respectively. For example, the high potential at the first pull-up node Q1 may specifically refer to a potential higher than the common terminal voltage, and the low potential at the first pull-up node Q1 may specifically refer to a potential lower than the common terminal voltage. It is understood that the specific potential height range can be set as required in a specific application scenario, and the present invention is not limited thereto.

Correspondingly, "pull-up" herein refers to raising the potential at the corresponding circuit node to a high potential, and "pull-down" herein refers to lowering the potential at the corresponding circuit node to a low potential. It is to be understood that the above-mentioned "pull-up" and "pull-down" can be realized by directional movement of charges, and therefore can be realized by electronic components or their combination with corresponding functions, which is not limited by the present invention.

In the shift register 100, the plurality of shift register units 101 share the first pull-down circuit 11, the first output end OUT1 of each shift register unit 101 is further connected to the first pull-down circuit 11 through the first unidirectional isolation circuit 14, and the second output end OUT2 of each shift register unit 101 is further connected to the first pull-down circuit 11 through the second unidirectional isolation circuit 15, so that the first output end OUT1 and the second output end OUT2 of each shift register unit 101 are isolated from each other, thereby simplifying the circuit structure, saving the occupied space, satisfying the requirement of a high-resolution narrow bezel, and simultaneously adding the pull-down holding circuits 30 at two ends of the first pull-down node QB1, so as to keep the first pull-down node QB1 at a low potential when the first pull-down node QB1 is in a pull-down potential state, preventing the first pull-down node QB1 from potential fluctuation, thereby greatly improving the pull-down reliability of the shared first pull-down circuit 11, the influence on the normal operation of the circuit caused by the pull-down failure is avoided.

Further, as shown in fig. 2, the first shift register unit 101A further includes a first control circuit 16A, the first control circuit 16A is respectively connected to the first pull-up node Q1, the first pull-down node QB1, the first power supply VDDA and the third power supply VGL1, the first control circuit 16A is configured to write the potential of the first power supply VDDA into the first pull-down node QB1, or pull down the potential of the first pull-down node QB1 to the potential of the third power supply VGL1 under the control of the first pull-up node Q1; the second shift register unit 101B further includes a second control circuit 16B, the second control circuit 16B is respectively connected to the second pull-up node Q2, the second pull-down node QB2, the second power supply VDDB, and the third power supply VGL1, the second control circuit 16B is configured to write the potential of the second power supply VDDB into the second pull-down node QB2, or pull down the potential of the second pull-down node QB2 to the potential of the third power supply VGL1 under the control of the second pull-up node Q2; a first control terminal of the first pull-down circuit 11 is connected to the first pull-down node QB1, and a second control terminal of the first pull-down circuit 11 is connected to the second pull-down node QB 2.

It should be noted that the first power supply VDDA and the second power supply VDDB may be alternatively operated. That is, only one of the first power supply VDDA and the second power supply VDDB is operated at the same time, for example, when the first power supply VDDA supplies a high potential, the second power supply VDDB supplies a low potential, and when the first power supply VDDA supplies a low potential, the second power supply VDDB supplies a high potential. In addition, the third power supply VGL1 may provide a low potential.

It is understood that, taking the example that the first power supply VDDA provides a high potential, the potential of the first power supply VDDA is written into the first pull-down node QB1, when the first pull-up node Q1 is a high potential, the first control circuit 16A may pull down the potential of the first pull-down node QB1, that is, the potential of the first pull-down node QB1 to the potential (low potential) of the third power supply VGL1, through the third power supply VGL1, at this time, the pull-down holding circuit 30 operates to eliminate the potential fluctuation that may occur on the first pull-down node QB1 by way of cancellation or absorption, so as to maintain the low potential of the first pull-down node QB 1. When the first pull-up node Q1 is at the low potential, the first control circuit 16A stops pulling down the potential of the first pull-down node QB1, and at this time, the pull-down holding circuit 30 does not operate, i.e., the potential of the first pull-down node QB1 is maintained at the potential of the first power supply VDDA (high potential). At this time, since the second power supply VDDB provides a low potential, the potential of the second pull-down node QB2 is always at a low potential.

Similarly, taking the example that the second power supply VDDB provides a high potential, the potential of the second power supply VDDB is written into the second pull-down node QB2, when the second pull-up node Q2 is a high potential, the second control circuit 16B may pull down the potential of the second pull-down node QB2, i.e., the potential of the second pull-down node QB2 is pulled down to the potential (low potential) of the third power supply VGL1, by the third power supply VGL1, and when the second pull-up node Q2 is a low potential, the second control circuit 16B stops pulling down the potential of the second pull-down node QB2, i.e., the potential of the second pull-down node QB2 is maintained at the potential (high potential) of the second power supply VDDB. At this time, since the first power supply VDDA provides a low potential, the potential of the first pull-down node QB1 is always at a low potential.

Further, as shown in fig. 2, the first shift register unit 101A further includes a cascade output circuit 18 and a second pull-down circuit 19, the cascade output circuit 18 is connected to the fifth clock terminal CLKD, the first pull-up node Q1 and the cascade output terminal CR, the cascade output circuit 18 is configured to control the cascade output terminal CR to output a cascade output signal according to the potential of the first pull-up node Q1 and the fifth clock signal of the fifth clock terminal CLKD, the second pull-down circuit 19 is connected to the cascade output terminal CR, the first control terminal of the second pull-down circuit 19 is connected to the first pull-down node QB1, the second control terminal of the second pull-down circuit 19 is connected to the second pull-down node QB2, and the second pull-down circuit 19 is configured to pull down the potential of the cascade output terminal CR under the control of the first pull-down node QB1 or the second pull-down node QB 2.

It is understood that when the first pull-up node Q1 is high and the fifth clock signal provided by the fifth clock terminal CLKD is high, the cascade output circuit 18 of the first shift register unit 101A is turned on, and the high voltage provided by the fifth clock terminal CLKD makes the cascade output terminal CR of the first shift register unit 101A output high voltage. In addition, when the first pull-down node QB1 or the second pull-down node QB2 is at a high level, the second pull-down circuit 19 of the first shift register unit 101A is turned on to pull down the cascade output terminal CR, i.e., to pull down the potential of the cascade output terminal CR to the potential (low level) of the third power supply VGL 1.

Further, as shown in fig. 2, the first shift register unit 101A further includes a first input unit 20A and a first reset unit 21A, the first input unit 20A is respectively connected to the first pull-up node Q1, the fourth power supply VDD and the first control terminal STU, the first input unit 20A is configured to write a potential provided by the fourth power supply VDD into the first pull-up node Q1 under the control of the first control terminal STU, the first reset unit 21A is connected to the first pull-up node Q1, the third power supply VGL1 and the second control terminal STD, the first reset unit 21A is configured to reset the first pull-up node Q1 by the third power supply VGL1 under the control of the second control terminal STD; the second shift register unit 101B further includes a second input unit 20B and a second reset unit 21B, the second input unit 20B is respectively connected to the second pull-up node Q2, the fourth power supply VDD, and the first control terminal STU, the second input unit 20B is configured to write a potential provided by the fourth power supply VDD into the second pull-up node Q2 under the control of the first control terminal STU, the second reset unit 21B is connected to the second pull-up node Q2, the third power supply VGL1, and the second control terminal STD, and the second reset unit 21B is configured to reset the second pull-up node Q2 by the third power supply VGL1 under the control of the second control terminal STD.

It is understood that when the first control terminal STU is at a high potential, the first input unit 20A of the first shift register unit 101A is turned on to write a high potential supplied from the fourth power source VDD into the first pull-up node Q1, and the second input unit 20B of the second shift register unit 101B is turned on to write a high potential supplied from the fourth power source VDD into the second pull-up node Q2. When the second control terminal STD is at the high potential, the first reset unit 21A of the first shift register unit 101A is turned on, the third power supply VGL1 resets the first pull-up node Q1, i.e., the potential of the first pull-up node Q1 is pulled down to the potential (low potential) of the third power supply VGL1, and the second reset unit 21B of the second shift register unit 101B is turned on, the third power supply VGL1 resets the second pull-up node Q2, i.e., the potential of the second pull-up node Q2 is pulled down to the potential (low potential) of the third power supply VGL 1.

Further, as shown in fig. 2, the first shift register unit 101A further includes a first sensing control circuit 22A, the first sensing control circuit 22A is respectively connected to the first pull-up node Q1, the pre-stored node H, the third control terminal CLKA, the fifth control terminal OE, and the fourth power supply VDD, the first sensing control circuit 22A is configured to write the potential provided by the fourth power supply VDD into the pre-stored node H under the control of the fifth control terminal OE in the display mode, and control the potential of the first pull-up node Q1 according to the potential of the pre-stored node H and the third control signal of the third control terminal CLKA in the sensing mode, so that the first output circuit 12A and the second output circuit 13A of the first shift register unit 101A output the first sensing control signal and the second sensing control signal respectively; the second shift register unit 101B further includes a second sensing control circuit 22B, the second sensing control circuit 22B is respectively connected to the second pull-up node Q2 and the third control terminal CLKA, the second sensing control circuit 22B is configured to control the potential of the second pull-up node Q2 according to a third control signal of the third control terminal CLKA in the sensing mode, so that the first output circuit 12B and the second output circuit 13B of the second shift register unit 101B respectively output the third sensing control signal and the fourth sensing control signal.

It is understood that, in the display mode, when the fifth control terminal OE outputs a high potential, the first sensing control circuit 22A writes the high potential provided by the fourth power supply VDD into the pre-storage node H, and the pre-storage node H keeps the high potential until entering the sensing mode, wherein the sensing is performed during the Blank period (Blank period) of the display device. In the sensing mode, the potential of the pre-stored node H is high, and when the third control signal of the third control terminal CLKA is high, the first sensing control circuit 22A is turned on and writes a high potential into the first pull-up node Q1 and the second pull-up node Q2.

Furthermore, when the first clock signal provided by the first clock terminal CLKEA is at a high level, the first output circuit 12A of the first shift register unit 101A is turned on, and the high level provided by the first clock terminal CLKEA makes the first output terminal OUT1 of the first shift register unit 101A output a high level, and when the second clock signal provided by the second clock terminal CLKFA is at a high level, the second output circuit 13A of the first shift register unit 101A is turned on, and the high level provided by the second clock terminal CLKFA makes the second output terminal OUT2 of the first shift register unit 101A output a high level. Similarly, when the third clock signal provided by the third clock terminal CLKEB is at a high level, the first output circuit 12B of the second shift register unit 101B is turned on, and the high level provided by the third clock terminal CLKEB enables the first output terminal OUT1 of the second shift register unit 101B to output a high level. When the fourth clock signal provided by the fourth clock terminal CLKFB is at a high level, the second output circuit 13B of the second shift register unit 101B is turned on, and the high level provided by the fourth clock terminal CLKFB makes the second output terminal OUT2 of the second shift register unit 101B output a high level.

Further, as shown in fig. 2, the first shift register unit 101A further includes a first reset circuit 23A, the first reset circuit 23A is connected to the first pull-up node Q1, the third power supply VGL1 and the fourth control terminal TRST, the first reset circuit 23A is configured to reset the first pull-up node Q1 through the third power supply VGL1 under the control of the fourth control terminal TRST; the second shift register unit 101B further includes a second reset circuit 23B, the second reset circuit 23B is connected to the second pull-up node Q2, the third power source VGL1 and the fourth control terminal TRST, and the second reset circuit 23B is configured to reset the second pull-up node Q2 by the third power source VGL1 under the control of the fourth control terminal TRST.

It is understood that when the fourth control terminal TRST is at a high potential, the first reset circuit 23A of the first shift register unit 101A is turned on, the first pull-up node Q1 is reset by the third power supply VGL1, that is, the potential of the first pull-up node Q1 is pulled down to the potential (low potential) of the third power supply VGL1, and the second reset circuit 23B of the second shift register unit 101B is turned on, the second pull-up node Q2 is reset by the third power supply VGL1, that is, the potential of the second pull-up node Q2 is pulled down to the potential (low potential) of the third power supply VGL 1.

The specific circuits and operation principles of the first shift register unit 101A and the second shift register unit 101B are described below with reference to fig. 3. In the following embodiments, the control electrode of the transistor may be a gate electrode, the first electrode of the transistor may be a collector electrode, and the second electrode of the transistor may be an emitter electrode. The transistors may be N-type transistors or P-type transistors, and the present application takes N-type transistors as an example for illustration. After reading the description of the present application, it is obvious to a person of ordinary skill in the art that the present application can be applied to the case of a P-type transistor, knowing the technical idea of the present application. As one example, the transistor may be a thin film transistor TFT.

As shown in fig. 3, in one embodiment, the first pull-down circuit 11 includes a first transistor M1 and a second transistor M2, a first pole of the first transistor M1 is connected to a first pole of the second transistor M2, and is connected to the first unidirectional isolation circuit 14 and the second unidirectional isolation circuit 15 of each shift register unit 101, a second pole of the first transistor M1 is connected to a second pole of the second transistor M2 and is connected to the fifth power source VGL2, a control pole of the first transistor M1 is connected to the first pull-down node QB1, and a control pole of the second transistor M2 is connected to the second pull-down node QB 2.

It should be noted that the fifth power supply VGL2 and the third power supply VGL1 may be dc low voltage signals, and the values thereof may be the same or different, and optionally, the voltage level of the fifth power supply VGL2 is higher than the voltage level of the third power supply VGL 1. Here, both the potential of the fifth power supply VGL2 and the potential of the third power supply VGL1 may be negative potentials. And the third power supply VDD is a dc high signal.

It is understood that when the first pull-down node QB1 is at a high potential, the first transistor M1 is turned on, and since the unidirectional isolation circuit in this application can conduct unidirectionally from the end connected to the output terminal to the end connected to the first pull-down circuit 11, the first transistor M1 is turned on, so that the first output terminal OUT1 and the second output terminal OUT2 of each shift register unit 101 are pulled down by the corresponding unidirectional isolation circuit, and the potential of the first output terminal OUT1 and the second output terminal OUT2 of each shift register unit 101 is pulled down to a low potential provided by the third power supply VGL 1.

In one embodiment, as shown in fig. 3, the first unidirectional isolation circuit 14A, 14B includes a third transistor M3 (i.e., the transistor Q3 in fig. 3), a first pole of the third transistor M3 is connected to the control pole and to the first output terminal OUT1 of the corresponding shift register unit 101, and a second pole of the third transistor M3 is connected to the first pull-down circuit 11; the second unidirectional isolation circuit 15A, 15B includes a fourth transistor M4 (i.e., the transistor Q4 in fig. 3), a first pole of the fourth transistor M4 is connected to the control pole and to the second output terminal OUT2 of the corresponding shift register unit 101, and a second pole of the fourth transistor M4 is connected to the first pull-down circuit 11.

It is to be understood that the first pole of the third transistor M3 is connected to the control pole to connect the third transistor M3 in a diode form, the first pole of the fourth transistor M4 is connected to the control pole to connect the fourth transistor M4 in a diode form, the second pole of the third transistor M3 and the second pole of the fourth transistor M4 are connected to the common node M, that is, the second pole of the third transistor M3 and the second pole of the fourth transistor M4 in the plurality of shift register units 101 are both connected to the common node M, and the common node M is connected to the first pull-down circuit 11. Taking the first output terminal OUT1 and the second output terminal OUT2 of the first shift register unit 101A as an example, when the first output terminal OUT1 is at a high voltage level, the output signal of the second output terminal OUT2 is not affected by the first output terminal OUT1 due to the reverse cut-off of the second unidirectional isolation circuit 15A, and when the second output terminal OUT2 is at a high voltage level, the output signal of the first output terminal OUT1 is not affected by the second output terminal OUT2 due to the reverse cut-off of the first unidirectional isolation circuit 14A.

Therefore, the sharing of the pull-down tubes is realized in a diode grouping mode, and the output ends can be independently output without mutual influence.

In the two shift register unit embodiment, as shown in fig. 3, the third transistor M3 in the first shift register unit 101A is denoted as Q3A, the fourth transistor M4 in the first shift register unit 101A is denoted as Q4A, the third transistor M3 in the second shift register unit 101B is denoted as Q3B, and the fourth transistor M4 in the second shift register unit 101B is denoted as Q4B.

In one embodiment, as shown in fig. 3, the third pull-down circuit 17A includes a seventh transistor Q7 (i.e., transistor M7 in fig. 3) and an eighth transistor Q8 (i.e., transistor M8 in fig. 3), a first pole of the seventh transistor Q7 is connected to a first pole of the eighth transistor Q8 and to the first pull-up node Q1, a second pole of the seventh transistor Q7 is connected to a second pole of the eighth transistor Q8 and to the third power source VGL1, a control pole of the seventh transistor Q7 is connected to the first pull-down node QB1, and a control pole of the eighth transistor Q8 is connected to the second pull-down node QB 2;

the pull-down holding circuit 30 includes an not gate NG and a thirtieth transistor M30. An input terminal a of the not-gate NG is connected to a control electrode of the seventh transistor Q7, an output terminal F of the not-gate NG is connected to a control terminal of the thirtieth transistor M30, a first electrode of the thirtieth transistor M30 is connected to the first control terminal of the first pull-down circuit 11, and a second electrode of the thirtieth transistor M30 is connected to the third power source VGL 1.

The fourth pull-down circuit 17B includes a ninth transistor Q9 (i.e., the transistor M9 in fig. 3) and a tenth transistor Q10 (i.e., the transistor M10 in fig. 3), a first pole of the ninth transistor Q9 is connected to a first pole of the tenth transistor Q10 and to the second pull-up node Q2, a second pole of the ninth transistor Q9 is connected to a second pole of the tenth transistor Q10 and to the third power source VGL1, a control pole of the ninth transistor Q9 is connected to the first pull-down node QB1, and a control pole of the tenth transistor Q10 is connected to the second pull-down node QB 2.

It is to be understood that when the first pull-down node QB1 is high, the seventh transistor Q7 is turned on, the potential of the first pull-up node Q1 may be pulled down to a low potential supplied from the third power supply VGL1 by the seventh transistor Q7, and the ninth transistor Q9 is turned on, the potential of the second pull-up node Q2 may be pulled down to a low potential supplied from the third power supply VGL1 by the ninth transistor Q9. And when the second pull-down node QB2 is high, the eighth transistor Q8 is turned on, the potential of the first pull-up node Q1 may be pulled down to a low potential supplied from the third power supply VGL1 by the eighth transistor Q8, and the tenth transistor Q10 is turned on, the potential of the second pull-up node Q2 may be pulled down to a low potential supplied from the third power supply VGL1 by the tenth transistor Q10.

When the first pull-down node QB1 is at a low level, for example, when the level fluctuates, the level can be maintained by the loop provided by the not gate NG and the thirtieth transistor M30, so that the level of the first pull-down node QB1 is maintained at a low level, that is, the low level provided by the third power source VGL 1.

In one embodiment, as shown in fig. 3, the second pull-down circuit 19 includes an eleventh transistor M11 and a twelfth transistor M12, a first pole of the eleventh transistor M11 is connected to a first pole of the twelfth transistor M12 and to the cascade output terminal CR, a second pole of the eleventh transistor M11 is connected to a second pole of the twelfth transistor M12 and to the third power source VGL1, a control pole of the eleventh transistor M11 is connected to the first pull-down node QB1, and a control pole of the twelfth transistor M12 is connected to the second pull-down node QB 2.

It is to be understood that when the first pull-down node QB1 is high, the eleventh transistor M11 is turned on, and the potential of the cascade output terminal CR may be pulled down to a low potential supplied from the third power supply VGL1 through the eleventh transistor M11. When the second pull-down node QB2 is at a high level, the twelfth transistor M12 is turned on, and the level of the cascade output terminal CR may be pulled down to a low level supplied by the third power source VGL1 through the twelfth transistor M12.

In one embodiment, as shown in fig. 3, the first output circuit 12A of the first shift register unit 101A includes a fifth transistor Q5 (i.e., the transistor M5 in fig. 3) and a second capacitor C2, a first pole of the fifth transistor Q5 is connected to the first clock terminal CLKEA, a second pole of the fifth transistor Q5 is connected to the first output terminal OUT1 of the first shift register unit 101A, and a control pole of the fifth transistor Q5 is connected to the first pull-up node Q1; one terminal of the second capacitor C2 is connected to the control electrode of the fifth transistor Q5, and the other terminal of the second capacitor C2 is connected to the second electrode of the fifth transistor Q5. The second output circuit 13A of the first shift register unit 101A includes a sixth transistor Q6 (i.e., the transistor M6 in fig. 3) and a third capacitor C3, a first pole of the sixth transistor Q6 is connected to the second clock terminal CLKFA, a second pole of the sixth transistor Q6 is connected to the second output terminal OUT2 of the first shift register unit 101A, and a control pole of the sixth transistor Q6 is connected to the first pull-up node Q1; one terminal of the third capacitor C3 is connected to the control electrode of the sixth transistor Q6, and the other terminal of the third capacitor C3 is connected to the second electrode of the sixth transistor Q6.

The first output circuit 12B of the second shift register unit 101B includes a thirteenth transistor Q13 (i.e., a transistor M13 in fig. 3) and a fourth capacitor C4, a first pole of the thirteenth transistor Q13 is connected to the third clock terminal CLKEB, a second pole of the thirteenth transistor Q13 is connected to the first output terminal OUT1 of the second shift register unit 101B, and a control pole of the thirteenth transistor Q13 is connected to the second pull-up node Q2; one terminal of the fourth capacitor C4 is connected to the control electrode of the thirteenth transistor Q13, and the other terminal of the fourth capacitor C4 is connected to the second electrode of the thirteenth transistor Q13. The second output circuit 13B of the second shift register unit 101B includes a fourteenth transistor Q14 (i.e., the transistor M14 in fig. 3) and a fifth capacitor C5, a first pole of the fourteenth transistor Q14 is connected to the fourth clock terminal CLKFB, a second pole of the fourteenth transistor Q14 is connected to the second output terminal OUT2 of the second shift register unit 101B, and a control pole of the fourteenth transistor Q14 is connected to the second pull-up node Q2; one terminal of the fifth capacitor C5 is connected to the control electrode of the fourteenth transistor Q14, and the other terminal of the fifth capacitor C5 is connected to the second electrode of the fourteenth transistor Q14.

It is understood that when the first pull-up node Q1 is at a high level, the gates of the fifth transistor Q5 and the sixth transistor Q6 are set to a high level, and if the first clock terminal CLKEA provides a high level, the first output terminal OUT1 of the first shift register unit 101A outputs a high level, and if the second clock terminal CLKFA provides a high level, the second output terminal OUT2 of the first shift register unit 101A outputs a high level. Similarly, when the second pull-up node Q2 is at a high level, the gates of the thirteenth transistor Q13 and the fourteenth transistor Q14 are set to a high level, if the third clock terminal CLKEB provides a high level, the first output terminal OUT1 of the second shift register unit 101B outputs a high level, and if the fourth clock terminal CLKFB provides a high level, the second output terminal OUT2 of the second shift register unit 101B outputs a high level.

In one embodiment, as shown in fig. 3, the first control circuit 16A of the first shift register unit 101A includes a fifteenth transistor M15 and a sixteenth transistor M16. A first pole of the fifteenth transistor M15 is connected to the control pole and to the first power supply VDDA, a second pole of the fifteenth transistor M15 is connected to the first pull-up node Q1, a first pole of the sixteenth transistor M16 is connected to the first pull-up node Q1, a second pole of the sixteenth transistor M16 is connected to the third power supply VGL1, and a control pole of the sixteenth transistor M16 is connected to the first pull-down node QB 1. The second control circuit 16B of the second shift register unit 101B includes a seventeenth transistor M17 and an eighteenth transistor M18. Wherein a first pole of the seventeenth transistor M17 is connected to the control pole and to the second power supply VDDB, a second pole of the seventeenth transistor M17 is connected to the second pull-up node Q2, a first pole of the eighteenth transistor M18 is connected to the second pull-up node Q2, a second pole of the eighteenth transistor M18 is connected to the third power supply VGL1, and a control pole of the eighteenth transistor M18 is connected to the second pull-down node QB 2.

It is to be understood that when the second power supply VDDB is operated, the second power supply VDDB provides a high potential, the first power supply VDDA provides a low potential, at this time, the fifteenth transistor M15 is turned off, the seventeenth transistor M17 is turned on, at this time, if the second pull-up node Q2 is high potential, the eighteenth transistor M18 is turned on, the potential of the second pull-down node QB2 is pulled down to the low potential of the third power supply VGL1, and if the second pull-up node Q2 is low potential, the second control circuit 16B stops pulling down the potential of the second pull-down node QB2, that is, the potential of the second pull-down node QB2 is maintained at the high potential of the second power supply VDDB.

Specifically, as shown in fig. 3, the cascade output circuit 18 includes a twenty-ninth transistor M29, wherein a first pole of the twenty-ninth transistor M29 is connected to the fifth clock terminal CLKD, a second pole of the twenty-ninth transistor M29 is connected to the cascade output terminal CR, and a control pole of the twenty-ninth transistor M29 is connected to the first pull-up node Q1.

It is understood that when the first pull-up node Q1 is at a high level, the gate of the twenty-ninth transistor M29 is set to a high level, and the high level is provided by the fifth clock terminal CLKD, so that the cascade output terminal CR of the first shift register unit 101A can output a high level.

Specifically, as shown in fig. 3, the first input unit 20A of the first shift register unit 101A includes a twenty-seventh transistor M27, a first electrode of the twenty-seventh transistor M27 is connected to the fourth power VDD, a second electrode of the twenty-seventh transistor M27 is connected to the first pull-up node Q1, and a control electrode of the twenty-seventh transistor M27 is connected to the first control terminal STU. The first reset unit 21A of the first shift register unit 101A includes a nineteenth transistor M19, a first pole of the nineteenth transistor M19 is connected to the first pull-up node Q1, a second pole of the nineteenth transistor M19 is connected to the third power source VGL1, and a control pole of the nineteenth transistor M19 is connected to the second control terminal STD.

It can be understood that, regarding the explanation of the rest of the devices in the shift register shown in fig. 3, the same part of circuits or devices in the shift register circuit existing in the field can be operated and understood in the same way, and the description is not repeated in this application.

Therefore, the shift register of the embodiment of the present invention, by sharing the first pull-down circuit 11, can simplify the structure of the circuit, save the occupied space, and meet the requirement of a high resolution narrow frame, and at the same time, add the pull-down holding circuits 30 at the two ends of the first pull-down node, so as to keep the first pull-down node at a low potential when the first pull-down node is at a pull-down potential state, and prevent the first pull-down node from potential fluctuation, thereby greatly improving the pull-down reliability of the shared first pull-down circuit, and avoiding the influence of pull-down failure on the normal operation of the circuit.

In one embodiment, a gate driving circuit is further provided, which includes a plurality of the above-mentioned shift registers 100.

It can be understood that, regarding the specific explanation of the shift register 100 in this embodiment, the same principle can be understood by referring to the corresponding explanation in the above embodiments of the shift register 100, and the description is omitted here.

The gate driving circuit using the shift register 100 can meet the requirement of a high resolution and narrow frame, and can effectively improve the reliability of the driving circuit.

In an embodiment, a display panel is further provided, which includes the gate driving circuit. It is to be understood that the display panel may include various necessary structural components besides the aforementioned circuit component of the gate driving circuit to which the shift register 100 is applied, and the specific structural components are determined according to the type of the display panel in practical application, and are not described in detail in this specification.

By applying the gate driving circuit, the product reliability of the display panel can be effectively improved.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A shift register is characterized by comprising a plurality of shift register units, wherein the plurality of shift register units share a first pull-down circuit, and each shift register unit further comprises a first output circuit and a second output circuit;

the first output circuit of each shift register unit is connected with the first output end of the corresponding shift register unit, the second output circuit of each shift register unit is connected with the second output end of the corresponding shift register unit, the first output end of each shift register unit is also connected with the first pull-down circuit through a first one-way isolation circuit, and the second output end of each shift register unit is also connected with the first pull-down circuit through a second one-way isolation circuit;

the shift register units comprise a first shift register unit and a second shift register unit, wherein a first output circuit of the first shift register unit is further connected with a first pull-up node and a first clock end, the first output circuit of the first shift register unit is used for controlling a first output end of the first shift register unit to output a first output signal according to the potential of the first pull-up node and a first clock signal of the first clock end, the second output circuit of the first shift register unit is further connected with the first pull-up node and a second clock end, and the second output circuit of the first shift register unit is used for controlling a second output end of the first shift register unit to output a second output signal according to the potential of the first pull-up node and a second clock signal of the second clock end;

the first output circuit of the second shift register unit is connected to the second pull-up node and the third clock terminal, the first output circuit of the second shift register unit is configured to control the first output terminal of the second shift register unit to output a third output signal according to the potential of the second pull-up node and a third clock signal of the third clock terminal, the second output circuit of the second shift register unit is connected to the second pull-up node and the fourth clock terminal, and the second output circuit of the second shift register unit is configured to control the second output terminal of the second shift register unit to output a fourth output signal according to the potential of the second pull-up node and the fourth clock signal of the fourth clock terminal;

the first shift register unit further comprises a third pull-down circuit and a pull-down holding circuit, the third pull-down circuit is connected with the first pull-up node, the first pull-down node and the second pull-down node, and the third pull-down circuit is used for initializing the first pull-up node under the control of the first pull-down node or the second pull-down node;

the pull-down holding circuit is respectively connected with the third pull-down circuit and the first pull-down circuit, and the pull-down holding circuit is used for holding the first pull-down node at a low potential when the first pull-down node is in a pull-down potential state.

2. The shift register of claim 1, wherein the first shift register unit further comprises a first control circuit, the first control circuit is connected to the first pull-up node, the first pull-down node, a first power supply, and a third power supply, respectively, and the first control circuit is configured to write a potential of the first power supply to the first pull-down node or pull down a potential of the first pull-down node to a potential of the third power supply under control of the first pull-up node;

the second shift register unit further comprises a second control circuit, the second control circuit is respectively connected with a second pull-up node, a second pull-down node, a second power supply and the third power supply, and the second control circuit is used for writing the potential of the second power supply into the second pull-down node or pulling down the potential of the second pull-down node to the potential of the third power supply under the control of the second pull-up node;

wherein a first control terminal of the first pull-down circuit is connected to the first pull-down node, and a second control terminal of the first pull-down circuit is connected to the second pull-down node.

3. The shift register of claim 1, wherein the first shift register unit further comprises a cascade output circuit and a second pull-down circuit, the cascade output circuit being connected to the fifth clock terminal, the first pull-up node, and the cascade output terminal; the cascade output circuit is used for controlling the cascade output end to output a cascade output signal according to the potential of the first pull-up node and a fifth clock signal of the fifth clock end;

the second pull-down circuit is connected with the cascade output end, a first control end of the second pull-down circuit is connected with a first pull-down node, a second control end of the second pull-down circuit is connected with a second pull-down node, and the second pull-down circuit is used for pulling down the potential of the cascade output end under the control of the first pull-down node or the second pull-down node.

4. The shift register of claim 1, wherein the first shift register unit further comprises a first input unit and a first reset unit, the first input unit is respectively connected to a first pull-up node, a fourth power supply and a first control terminal, and the first input unit is configured to write a potential provided by the fourth power supply into the first pull-up node under the control of the first control terminal;

the first reset unit is connected with the first pull-up node, a third power supply and a second control end, and is used for resetting the first pull-up node through the third power supply under the control of the second control end;

the second shift register unit further includes a second input unit and a second reset unit, the second input unit is respectively connected to the second pull-up node, the fourth power supply and the first control end, and the second input unit is configured to write a potential provided by the fourth power supply into the second pull-up node under the control of the first control end;

the second reset unit is connected with the second pull-up node, the third power supply and the second control end, and the second reset unit is used for resetting the second pull-up node through the third power supply under the control of the second control end.

5. The shift register of claim 2, wherein the first shift register unit further comprises a first sensing control circuit, the first sensing control circuit is respectively connected to the first pull-up node, a pre-stored node, a third control terminal, a fifth control terminal and a fourth power supply, the first sensing control circuit is configured to write a potential provided by the fourth power supply into the pre-stored node under the control of the fifth control terminal in the display mode, and control the potential of the first pull-up node according to the potential of the pre-stored node and a third control signal of the third control terminal in the sensing mode, so that the first output circuit and the second output circuit of the first shift register unit respectively output a first sensing control signal and a second sensing control signal;

the second shift register unit further comprises a fourth pull-down circuit and a second sensing control circuit, the fourth pull-down circuit is connected with the second pull-up node, the first pull-down node and the second pull-down node, and the fourth pull-down circuit is used for initializing the second pull-up node under the control of the first pull-down node or the second pull-down node;

the second sensing control circuit is connected to the second pull-up node and the third control terminal, and the second sensing control circuit is configured to control a potential of the second pull-up node according to a third control signal of the third control terminal in a sensing mode, so that the first output circuit and the second output circuit of the second shift register unit output a third sensing control signal and a fourth sensing control signal, respectively.

6. The shift register according to claim 2, wherein the first power supply and the second power supply operate alternately.

7. The shift register of claim 2, wherein the first pull-down circuit comprises a first transistor and a second transistor, a first pole of the first transistor is connected to a first pole of the second transistor and to the first unidirectional isolation circuit and the second unidirectional isolation circuit of each of the shift register cells, a second pole of the first transistor is connected to a second pole of the second transistor and to a fifth power supply, a control pole of the first transistor is connected to the first pull-down node, and a control pole of the second transistor is connected to the second pull-down node.

8. The shift register of claim 1, wherein the first unidirectional isolation circuit comprises a third transistor, a first pole of the third transistor is connected to the control pole and to the first output terminal of the corresponding shift register cell, and a second pole of the third transistor is connected to the first pull-down circuit;

the second unidirectional isolation circuit comprises a fourth transistor, a first pole of the fourth transistor is connected with the control pole and is connected with the second output end of the corresponding shift register unit, and a second pole of the fourth transistor is connected with the first pull-down circuit.

9. The shift register of claim 5, wherein the third pull-down circuit comprises a seventh transistor and an eighth transistor, a first pole of the seventh transistor is connected to a first pole of the eighth transistor and to the first pull-up node, a second pole of the seventh transistor is connected to a second pole of the eighth transistor and to a third power supply, a control pole of the seventh transistor is connected to the first pull-down node, and a control pole of the eighth transistor is connected to the second pull-down node;

the pull-down holding circuit comprises an NOT gate and a thirtieth transistor, wherein the input end of the NOT gate is connected with the control electrode of the seventh transistor, the output end of the NOT gate is connected with the control end of the thirtieth transistor, the first electrode of the thirtieth transistor is connected with the first control end of the first pull-down circuit, and the second electrode of the thirtieth transistor is connected with the third power supply;

the fourth pull-down circuit comprises a ninth transistor and a tenth transistor, wherein the first pole of the ninth transistor is connected with the first pole of the tenth transistor and is connected with the second pull-up node, the second pole of the ninth transistor is connected with the second pole of the tenth transistor and is connected with the third power supply, the control pole of the ninth transistor is connected with the first pull-down node, and the control pole of the tenth transistor is connected with the second pull-down node.

10. The shift register of claim 3, wherein the second pull-down circuit comprises an eleventh transistor and a twelfth transistor, a first pole of the eleventh transistor is connected to a first pole of the twelfth transistor and to the cascade output terminal, a second pole of the eleventh transistor is connected to a second pole of the twelfth transistor and to a third power supply, a control pole of the eleventh transistor is connected to the first pull-down node, and a control pole of the twelfth transistor is connected to the second pull-down node.

11. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 10.

12. A display panel comprising the gate driver circuit according to claim 11.