CN106782664A - Shift register and its driving method, gate driving circuit - Google Patents
Shift register and its driving method, gate driving circuit Download PDFInfo
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- CN106782664A CN106782664A CN201710093202.9A CN201710093202A CN106782664A CN 106782664 A CN106782664 A CN 106782664A CN 201710093202 A CN201710093202 A CN 201710093202A CN 106782664 A CN106782664 A CN 106782664A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
The present invention provides a kind of shift register and its driving method, gate driving circuit, belongs to gate driving circuit technical field, and it can at least partly be solved, and existing shift register structure is complicated, takes the big problem of wiring space.Shift register of the invention includes：Unit is drawn, the signal of output end is introduced input by its connection pull-down node, input, output end for the level according to pull-down node；Input block, its level for being used to be controlled according to the signal of input pull-up node；Reset unit, its signal for being used to that according to the signal of reset terminal level terminal will to be determined introduces pull-up node；Output unit, it is used to that the signal at clock end to be introduced into output end according to the level of pull-up node；Drop-down control unit, its signal for being used to that according to the signal of control end and the level of pull-up node level terminal will to be determined introduces pull-down node；Drop-down unit, its signal for being used to that according to the level of pull-down node level terminal will to be determined introduces pull-up node and output end.
Description
Technical field
The invention belongs to gate driving circuit technical field, and in particular to a kind of shift register and its driving method, grid
Pole drive circuit.
Background technology
Gate driving circuit (GOA) is the circuit for driven grid line being directly produced on array base palte, and it is by multiple
The shift register of cascade is constituted.Wherein, for make to realize 100% noise reduction, can protected by control end and related transistor
Hold the stage introduces pull-down node by high level, and then will determine the low level signal of level terminal and introduce output end.
As shown in figure 1, existing shift register has the first control end VDD1 and the second control end VDD2, and accordingly
First pull-down node PD1 and the second pull-down node PD2.Wherein, the first control end VDD1 and the second control end VDD2 are input into turn
High level (maintains multiple clock cycle) every time, so that the first pull-down node PD1 and the second pull-down node PD2 are in turn electricity high
It is flat, output end OUTPUT is introduced with the lasting low level signal that will determine level terminal VSS.So, it is corresponding with each control end
Transistor all only in part-time work, without being in bias state for a long time, can avoid the failure of transistor, improve circuit
Reliability.
Obviously, above shift register avoids transistor from working long hours by setting two control ends, therefore wherein also
There must be " two sets " transistors for noise reduction, this causes its number of devices many, at least wants 15 transistors (15T1C), and
The wiring space of occupancy is big, is unfavorable for realizing that narrow frame (especially ultra-narrow frame) is designed.
The content of the invention
The present invention at least partly solves existing shift register structure complexity, takes the big problem of wiring space, there is provided
A kind of simple structure, takes wiring space small, it is easy to accomplish the shift register and its driving method of ultra-narrow frame design, grid
Drive circuit.
The technical scheme that solution present invention problem is used is a kind of shift register, and it includes：
Storage capacitance, its first pole connection pull-up node, the second pole connection output end；
Unit is drawn, its connection pull-down node, input, output end, for the level according to pull-down node by output end
Signal introduce input；
Input block, its connection input and pull-up node, the electricity for controlling pull-up node according to the signal of input
It is flat；
Reset unit, its connection reset terminal, determine level terminal, pull-up node, for according to the signal of reset terminal will determine level
The signal at end introduces pull-up node；
Output unit, its connection clock end, output end, pull-up node, for the level according to pull-up node by clock end
Signal introduce output end；
Drop-down control unit, it connects control end, pull-up node, level terminal, pull-down node is determined, for according to control end
The signal that the level of signal and pull-up node will determine level terminal introduces pull-down node；
Drop-down unit, its connection pull-down node, pull-up node, output end, determines level terminal, for the electricity according to pull-down node
The flat signal that will determine level terminal introduces pull-up node and output end.
Preferably, the extraction unit includes the tenth transistor, wherein, the grid connection of the tenth transistor is drop-down
Node, the first pole connection input, the second pole connection output end.
It may further be preferable that the input block includes the first transistor, wherein, the grid of the first transistor connects
Connect input, the first pole connection input, the second pole connection pull-up node.
It may further be preferable that the reset unit includes transistor seconds, wherein, the grid of the transistor seconds connects
Reset terminal is connect, level terminal is determined in the first pole connection pull-up node, the second pole connection.
It may further be preferable that the output unit includes third transistor, wherein, the grid of the third transistor connects
Connect pull-up node, the first pole connection clock end, the second pole connection output end.
It may further be preferable that the drop-down control unit include the 4th transistor, the 5th transistor, the 6th transistor,
7th transistor, wherein, the grid of the 4th transistor connection control end, the first pole connection control end, the second pole connection the
First pole of six transistors；The grid of the 5th transistor connects the first pole of the 6th transistor, and the first pole connects control end,
Second pole connects pull-down node；Level terminal is determined in the grid connection pull-up node of the 6th transistor, the second pole connection；Described
Level terminal is determined in the grid connection pull-up node of seven transistors, the first pole connection pull-down node, the second pole connection.
It may further be preferable that the drop-down unit includes the 8th transistor, the 9th transistor, wherein, the described 8th is brilliant
Level terminal is determined in the grid connection pull-down node of body pipe, the first pole connection pull-up node, the second pole connection；9th transistor
Grid connects pull-down node, and level terminal is determined in the first pole connection output end, the second pole connection.
It may further be preferable that all transistors are N-type transistor；Or, all transistors are P-type transistor.
It is a kind of gate driving circuit to solve the technical scheme that is used of present invention problem, including multiple cascades is upper
Shift register is stated, wherein,
The output end of the shift register connects the input of its lower first order shift register；
The reset terminal of the shift register connects the pull-up node of its lower second level shift register；
The clock end of odd level shift register cell connects the first clock signal, the clock end connection second of even level shift register cell
Clock signal；
The clock end of odd level shift register cell connects the first control signal, the clock end connection second of even level shift register cell
Control signal, at any time, one is high level in first control signal and the second control signal, and another is low electricity
It is flat.
The technical scheme that solution present invention problem is used is a kind of driving method of above-mentioned shift register, its bag
Include：
The signal of input is introduced pull-up node by input phase, input block；
The signal at clock end is introduced output end by output stage, output unit；
Reseting stage, the signal that reset unit will determine level terminal introduces pull-up node；
Holding stage, the signal that drop-down unit will determine level terminal introduces output end.
Preferably, when all transistors are N-type transistor in above-mentioned shift register, it is described determine level terminal continue
Low level signal is provided；The driving method of the shift register includes：
Input phase：Input provides high level signal, and clock end provides low level signal, and reset terminal provides low level letter
Number；
The output stage：Input provides low level signal, and clock end provides high level signal, and reset terminal provides low level letter
Number；
Reseting stage：Input provides low level signal, and clock end provides low level signal, and reset terminal provides high level letter
Number；
The holding stage：Input provides low level signal, and reset terminal provides low level signal；
Or,
It is described to determine level terminal electricity high is persistently provided when all transistors are P-type transistor in above-mentioned shift register
Ordinary mail number；The driving method of the shift register includes：
Input phase：Input provides low level signal, and clock end provides high level signal, and reset terminal provides high level letter
Number；
The output stage：Input provides high level signal, and clock end provides low level signal, and reset terminal provides high level letter
Number；
Reseting stage：Input provides high level signal, and clock end provides high level signal, and reset terminal provides low level letter
Number；
The holding stage：Input provides high level signal, and reset terminal provides high level signal..
In shift register of the invention, can be by drawing unit by output end and input (namely upper level displacement
The output end of register) it is connected, so as to not in the same time, a shift register or be itself and upper level shift register
Noise reduction, or by next stage shift register noise reduction.So, can be in the situation of each shift register only one of which control end
Under, taken turns to operate by transistor and realize 100% noise reduction；Thus, the number of devices of the shift register is few (10T1C), structure
Simply, wiring space is taken small, it is easy to accomplish ultra-narrow frame is set.
Brief description of the drawings
Fig. 1 is a kind of circuit diagram of existing shift register；
Fig. 2 is a kind of circuit diagram of shift register of embodiments of the invention；
Fig. 3 is three timing diagrams of the shift register of the embodiments of the invention of cascade；
Fig. 4 is a kind of composition block diagram of gate driving circuit of embodiments of the invention；
Wherein, reference is：1st, unit is drawn；2nd, input block；3rd, reset unit；4th, output unit；5th, drop-down control
Unit processed；6th, drop-down unit；M1, the first transistor；M2, transistor seconds；M3, third transistor；M4, the 4th transistor；M5、
5th transistor；M6, the 6th transistor；M7, the 7th transistor；M8, the 8th transistor；M9, the 9th transistor；M10, the tenth crystalline substance
Body pipe；C, storage capacitance；OUTPUT, output end；INPUT, input；VSS, determine level terminal；VDD, control end；CLK, clock
End；RESET, reset terminal；PD, pull-down node；PU, pull-up node.
Specific embodiment
To make those skilled in the art more fully understand technical scheme, below in conjunction with the accompanying drawings and specific embodiment party
Formula is described in further detail to the present invention.
Embodiment 1：
As shown in Figures 2 to 4, the present embodiment provides a kind of shift register, and it includes：
Storage capacitance C, its first pole connection pull-up node PU, the second pole connects output end OUTPUT；
Unit 1 is drawn, its connection pull-down node PD, input INPUT, output end OUTPUT, for according to pull-down node
The signal of output end OUTPUT is introduced input INPUT by the level of PD；
Input block 2, its connection input INPUT and pull-up node PU, for being controlled according to the signal of input INPUT
The level of pull-up node PU；
Reset unit 3, it connects reset terminal RESET, level terminal VSS, pull-up node PU is determined, for according to reset terminal
The signal that the signal of RESET will determine level terminal VSS introduces pull-up node PU；
Output unit 4, its connection clock end CLK, output end OUTPUT, pull-up node PU, for according to pull-up node PU
Level the signal of clock end CLK is introduced into output end OUTPUT；
Drop-down control unit 5, it connects control end VDD, pull-up node PU, determines level terminal VSS, pull-down node PD, is used for
The signal that the level of signal and pull-up node PU according to control end VDD will determine level terminal VSS introduces pull-down node PD；
Drop-down unit 6, its connection pull-down node PD, pull-up node PU, output end OUTPUT, determines level terminal VSS, for root
The signal that will determine level terminal VSS according to the level of pull-down node PD introduces pull-up node PU and output end OUTPUT.
In the shift register of the present embodiment, can be by drawing unit by output end OUTPUT and input INPUT (also
It is the output end OUTPUT of upper level shift register) it is connected, so as to not in the same time, a shift register or be itself
With upper level shift register noise reduction, or by next stage shift register noise reduction.So, can only have in each shift register
In the case of one control end VDD, taken turns to operate by transistor and realize 100% noise reduction；Thus, the device of the shift register
Quantity is few (10T1C), simple structure, takes wiring space small, it is easy to accomplish ultra-narrow frame is set.
As shown in Figure 2, it is preferred that draw unit 1 include the tenth transistor M10, wherein, the grid of the tenth transistor M10
Connection pull-down node PD, the first pole connection input INPUT, the second pole connects output end OUTPUT.
It is further preferred that input block 2 includes the first transistor M1, wherein, the grid connection of the first transistor M1 is defeated
Enter and hold INPUT, the first pole connection input INPUT, the second pole connects pull-up node PU.
It is further preferred that reset unit 3 includes transistor seconds M2, wherein, the grid connection of transistor seconds M2 is multiple
Level terminal VSS is determined in position end RESET, the first pole connection pull-up node PU, the second pole connection.
It is further preferred that output unit 4 includes third transistor M3, wherein, in the grid connection of third transistor M3
Node PU, the first pole connection clock end CLK are drawn, the second pole connects output end OUTPUT.
It is further preferred that drop-down control unit 5 include the 4th transistor M4, the 5th transistor M5, the 6th transistor M6,
7th transistor M7, wherein, the grid connection control end VDD of the 4th transistor M4, the first pole connection control end VDD, the second pole
Connect first pole of the 6th transistor M6；The grid of the 5th transistor M5 connects first pole of the 6th transistor M6, and the first pole connects
Control end VDD is met, the second pole connects pull-down node PD；The grid connection pull-up node PU of the 6th transistor M6, the connection of the second pole
Determine level terminal VSS；The grid connection pull-up node PU of the 7th transistor M7, the first pole connection pull-down node PD, the connection of the second pole
Determine level terminal VSS.
It is further preferred that drop-down unit 6 includes the 8th transistor M8, the 9th transistor M9, wherein, the 8th transistor M8
Grid connection pull-down node PD, the first pole connection pull-up node PU, the second pole connection determines level terminal VSS；9th transistor M9
Grid connection pull-down node PD, the first pole connection output end OUTPUT, the second pole connection determines level terminal VSS.
It is further preferred that all transistors are N-type transistor；Or, all transistors are P-type transistor.
That is, in the shift register of the present embodiment, all of transistor is preferably same type, in Fig. 2 with
Whole transistors are illustrated as a example by being N-type transistor.Certainly, if wherein all of transistor is P-type transistor,
It is feasible.
As shown in figure 4, the present embodiment also provides a kind of gate driving circuit, including multiple above-mentioned shift LDs for cascading
Device, wherein,
The output end OUTPUT of shift register connects the input INPUT of its lower first order shift register；
The reset terminal RESET of shift register connects the pull-up node PU of its lower second level shift register；
The clock end CLK of odd level shift register cell connects the first clock signal, and the clock end CLK of even level shift register cell connects
Connect second clock signal；
The clock end CLK of odd level shift register cell connects the first control signal, and the clock end CLK of even level shift register cell connects
The second control signal is connect, at any time, one is high level in first control signal and the second control signal, another
It is low level.
That is, shift register more than multiple is concatenated together, gate driving circuit is constituted, the grid being somebody's turn to do drives
The output end OUTPUT of each shift register of dynamic circuit connects a grid line (not shown) to be driven.
Wherein, in addition to afterbody shift register, it is next that the output end OUTPUT of every grade of shift register is all connected with its
The input INPUT of level shift register, for the input INPUT of next stage shift register provides signal.Certainly, last
The output end OUTPUT of level shift register is simultaneously not connected to the input INPUT of other shift registers, and the first level is deposited
The input INPUT of device is then controlled by additional independent signal, is also not connected to the output end OUTPUT of other shift registers.
Meanwhile, in addition to last two-stage shift register, the reset terminal RESET of every grade of shift register is also connected with two under it
The pull-up node PU of level shift register (referring to the second level shift register under it, rather than two shift registers), that is, use
The level of the pull-up node PU of lower two-stage shift register as reset terminal RESET input signal.Certainly, last two-stage displacement
The reset terminal RESET of register is simultaneously not connected to the pull-up node PU of other shift registers, but by additional independent signal
Control, meanwhile, the pull-up node PU of most preceding two-stage shift register is also not connected to the reset terminal RESET of other shift registers.
In addition, the clock end CLK of each shift register is intended to connect clock signal, and odd level and even level displacement are posted
The level of the clock signal of storage connection is opposite.
In the gate driving circuit, the control end VDD of each shift register also wants connection control signal, and wherein strange
The level of several levels and the control signal of even level shift register connection is opposite.That is, at any time, if odd number
The control end VDD of level shift register is high level, then the control end VDD of even level shift register is low level；And if strange
The control end VDD of several levels shift register is low level, then the control end VDD of even level shift register is high level.So,
For the shift register of any two successive stages, the level of the signal of its control end VDD is necessarily opposite.
Thus, when the Shift Reg Odd being connected with the first control signal can carry out noise reduction, (such as the first control signal is
High level) when, they be both itself noise reduction, while being also the even level shift register noise reduction of upper level；And controlled when with second
When the connected Shift Reg Even of signal processed can carry out noise reduction (such as the second control signal is high level), then they are alternatively
The odd level shift register noise reduction of one-level；Thus, no matter the situation of the first control signal and the second control signal, all
Shift register can realize noise reduction.
Wherein, in a frame picture, the first control signal can repeatedly be switched with the level relationship of the second control signal
(maintaining multiple clock cycle every time), so as to be used for the transistor (mainly the 5th transistor M5) of noise reduction in each shift register
Alternation without being in bias state for a long time, it is to avoid the damage of transistor.
The present embodiment also provides a kind of driving method of above-mentioned shift register, and it includes：
The signal of input INPUT is introduced pull-up node PU by input phase, input block；
The signal of clock end CLK is introduced output end OUTPUT by output stage, output unit；
Reseting stage, the signal that reset unit will determine level terminal VSS introduces pull-up node PU；
Holding stage, the signal that drop-down unit will determine level terminal VSS introduces output end OUTPUT.
As shown in figure 3, below by taking the shift register that above-mentioned all transistors are N-type transistor as an example, to displacement
The specific work process of register is described in detail.Wherein, for the shift register, level terminal is determined during its driving
VSS persistently provides low level signal, and the driving method of the shift register specifically includes following steps：
S101, input phase：Input INPUT provides high level signal, and clock end CLK provides low level signal, resets
End RESET provide low level signal.
In this stage, input INPUT provides high level signal (i.e. the Continuity signal of upper level shift register output),
Therefore the first transistor M1 is turned on, pull-up node PU is set to be high level.And then third transistor M3 is turned on, by the low of clock end CLK
Level signal introduces output end OUTPUT, and storage capacitance C charges, shift register output low level.
Simultaneously as pull-up node PU is high level, the 6th transistor M6, the 7th transistor M7 conducting, no matter therefore the shifting
How is the signal of the control end VDD of bit register, and the 4th transistor M4 and the 5th transistor M5 are turned off, and pull-down node PD is low
Level, the tenth transistor M10 shut-offs, (now upper level shift register is in output not to interfere with upper level shift register
Stage).And because now this grade of shift register directly exports low level, no matter therefore whether next stage shift register can be this
Level shift register noise reduction, does not affect its output.
S102, output stage：Input INPUT provides low level signal, and clock end CLK provides high level signal, resets
End RESET provide low level signal.
In this stage, input INPUT is changed into low level, therefore the first transistor M1 is turned off, and pull-up node PU cannot be provided
Electricity and keep high level, third transistor M3 is persistently opened, and the clock end CLK signal that will be changed into high level introduces output end
OUTPUT, shift register output high level (Continuity signal), and drive next stage shift register to enter input phase.
Simultaneously as the boot strap of storage capacitance C, the level of pull-up node PU is further raised and (but still falls within electricity high
It is flat), the 6th transistor M6, the 7th transistor M7 are held on, no matter therefore the now signal of control end VDD, pull-down node
PD is low level, and the output of shift register high level does not interfere with upper level shift register, and (now upper level displacement is posted
Storage is in reseting stage).And now next stage shift register is now in input phase, therefore this grade of displacement will not also be posted
Storage is impacted.
S103, reseting stage：Input INPUT provides low level signal, and clock end CLK provides low level signal, resets
End RESET provide high level signal.
In this stage, reset terminal RESET provides high level signal and (descends the pull-up node PU electricity of two-stage shift register
It is flat) transistor seconds M2 is turned on, the low level signal that will determine level terminal VSS introduces pull-up node PU, and pull-up node PU is changed into
Low level, third transistor M3, the 6th transistor M6, the 7th transistor M7 are turned off.
Wherein, if now this grade of control end VDD of shift register is high level, the 4th transistor M4 and the 5th is brilliant
Body pipe M5 is turned on, and high point ordinary mail number enters pull-down node PD, opens the 8th transistor M8 and the 9th transistor M9, will determine level
The low level signal of VSS is held to introduce pull-up node PU and output end OUTPUT respectively, storage capacitance C resets, and shift register is defeated
Go out low level and be itself noise reduction.Meanwhile, the high level of pull-down node PD also turns on the tenth transistor M10, therefore output end
The low level of OUTPUT can enter the output end of upper level shift register by the tenth transistor M10 and input INPUT
OUTPUT, is that (now upper level shift register has just enter into the holding stage to upper level shift register noise reduction and control end VDD is
Low level).And if now this grade of control end VDD of shift register is low level, then pull-down node PD is low level, output
End OUTPUT is reduced to low level as pull-up node PU, and storage capacitance C resets, shift register output low level.Wherein,
Next stage shift register is now in the output stage, therefore does not interfere with this grade of shift register.
S104, holding stage：Input INPUT provides low level signal, and reset terminal RESET provides low level signal.
Input INPUT and reset terminal RESET are low level in this stage, therefore pull-up node PU keeps low level, the
Three transistor M3 are turned off, and though clock end CLK why signal, all without influence output end OUTPUT.
Wherein, when this grade of control end VDD of shift register is high level, pull-down node PD is high level, can be determined
The low level of level terminal VSS introduces the output end OUTPUT of output end OUTPUT and upper level shift register, so as to be this
Level shift register and upper level shift register noise reduction (upper level shift register is now also at the holding stage).
Conversely, when the control end VDD of the shift register is low level, then the control end of its next stage shift register
VDD in reseting stage or is kept for the stage to be necessarily high level, so that can be by next stage shift register for this level is shifted
Register noise reduction.
Certainly, due to the pull-up node PU of two-stage shift register under being of reset terminal RESET connections, therefore in the stage of holding
Start to make, the level of reset terminal RESET actually can further raise (but still falling within high level), but it does not influence shift LD
The output of device.
In a frame picture, the first control signal and the second control signal are alternately high level, therefore a shift register control
The signal of end VDD processed is also to replace as high level and is low level (maintaining multiple clock cycle every time), can so make each shifting
Transistor (mainly the 5th transistor M5) alternation for being used for noise reduction in bit register is in bias shape without long-time
State, it is to avoid the damage of transistor.
Certainly, the shift register of P-type transistor is to all of above transistor, level terminal is determined during its driving
VSS persistently provides low level signal, and the driving method of the shift register specifically includes following steps：
Input phase：Input INPUT provides low level signal, and clock end CLK provides high level signal, reset terminal
RESET provides high level signal.
The output stage：Input INPUT provides high level signal, and clock end CLK provides low level signal, reset terminal
RESET provides high level signal.
Reseting stage：Input INPUT provides high level signal, and clock end CLK provides high level signal, reset terminal
RESET provides low level signal.
The holding stage：Input INPUT provides high level signal, and reset terminal RESET provides high level signal.
The structure of the shift register is identical with example above, and simply transistor types and level height be and example above
Conversely, therefore, its course of work and example above are really identical, do not describing in detail herein.
It is understood that the embodiment of above principle being intended to be merely illustrative of the present and the exemplary implementation for using
Mode, but the invention is not limited in this.For those skilled in the art, essence of the invention is not being departed from
In the case of god and essence, various changes and modifications can be made therein, and these variations and modifications are also considered as protection scope of the present invention.
Claims (10)
1. a kind of shift register, it is characterised in that including：
Storage capacitance, its first pole connection pull-up node, the second pole connection output end；
Unit is drawn, its connection pull-down node, input, output end, for the level according to pull-down node by the letter of output end
Number introduce input；
Input block, its connection input and pull-up node, the level for controlling pull-up node according to the signal of input；
Reset unit, it connects reset terminal, determines level terminal, pull-up node, and level terminal will be determined for the signal according to reset terminal
Signal introduces pull-up node；
Output unit, its connection clock end, output end, pull-up node, for the level according to pull-up node by the letter at clock end
Number introduce output end；
Drop-down control unit, it connects control end, pull-up node, level terminal, pull-down node is determined, for the signal according to control end
The signal that will determine level terminal with the level of pull-up node introduces pull-down node；
Drop-down unit, its connection pull-down node, pull-up node, output end, determine level terminal, for according to the level of pull-down node general
The signal for determining level terminal introduces pull-up node and output end.
2. shift register according to claim 1, it is characterised in that the extraction unit includes the tenth transistor, its
In,
The grid connection pull-down node of the tenth transistor, the first pole connection input, the second pole connection output end.
3. shift register according to claim 2, it is characterised in that the input block includes the first transistor, its
In,
The grid connection input of the first transistor, the first pole connection input, the second pole connection pull-up node.
4. shift register according to claim 3, it is characterised in that the reset unit includes transistor seconds, its
In,
Level terminal is determined in the grid connection reset terminal of the transistor seconds, the first pole connection pull-up node, the second pole connection.
5. shift register according to claim 4, it is characterised in that the output unit includes third transistor, its
In,
The grid connection pull-up node of the third transistor, the first pole connection clock end, the second pole connection output end.
6. shift register according to claim 5, it is characterised in that the drop-down control unit includes the 4th crystal
Pipe, the 5th transistor, the 6th transistor, the 7th transistor, wherein,
The grid connection control end of the 4th transistor, the first pole connection control end, the second pole connects the of the 6th transistor
One pole；
The grid of the 5th transistor connects the first pole of the 6th transistor, the first pole connection control end, under the connection of the second pole
Draw node；
Level terminal is determined in the grid connection pull-up node of the 6th transistor, the second pole connection；
Level terminal is determined in the grid connection pull-up node of the 7th transistor, the first pole connection pull-down node, the second pole connection.
7. shift register according to claim 6, it is characterised in that the drop-down unit includes the 8th transistor, the
Nine transistors, wherein,
Level terminal is determined in the grid connection pull-down node of the 8th transistor, the first pole connection pull-up node, the second pole connection；
Level terminal is determined in the grid connection pull-down node of the 9th transistor, the first pole connection output end, the second pole connection.
8. shift register according to claim 7, it is characterised in that
All transistors are N-type transistor；
Or,
All transistors are P-type transistor.
9. the shift register of a kind of gate driving circuit, including multiple cascades, it is characterised in that the shift register is power
Profit requires the shift register described in any one in 1 to 8, wherein,
The output end of the shift register connects the input of its lower first order shift register；
The reset terminal of the shift register connects the pull-up node of its lower second level shift register；
The clock end of odd level shift register cell connects the first clock signal, the clock end connection second clock of even level shift register cell
Signal；
The clock end of odd level shift register cell connects the first control signal, and the clock end connection second of even level shift register cell is controlled
Signal, at any time, one is high level in first control signal and the second control signal, and another is low level.
10. a kind of driving method of shift register, it is characterised in that the shift register is any in claim 1 to 8
Shift register described in one, the driving method of the shift register includes：
The signal of input is introduced pull-up node by input phase, input block；
The signal at clock end is introduced output end by output stage, output unit；
Reseting stage, the signal that reset unit will determine level terminal introduces pull-up node；
Holding stage, the signal that drop-down unit will determine level terminal introduces output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN108399906A (en) * | 2018-05-25 | 2018-08-14 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and display device |
| CN109754767A (en) * | 2019-01-24 | 2019-05-14 | 合肥京东方显示技术有限公司 | A kind of shift register and its driving method, gate driving circuit, display device |
| CN110459185A (en) * | 2019-07-19 | 2019-11-15 | 信利半导体有限公司 | A kind of GOA driving circuit, driving method and the display device of low noise |
| CN110880301A (en) * | 2019-12-12 | 2020-03-13 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof and grid driving circuit |
| WO2023005628A1 (en) * | 2021-07-29 | 2023-02-02 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, and gate driver circuit and driving method thereof |
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