CN114677948A - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN114677948A
CN114677948A CN202210294935.XA CN202210294935A CN114677948A CN 114677948 A CN114677948 A CN 114677948A CN 202210294935 A CN202210294935 A CN 202210294935A CN 114677948 A CN114677948 A CN 114677948A
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transistor
signal
gate
reference signal
initialization
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Chinese (zh)
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林飞鹏
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Xiamen Tianma Display Technology Co Ltd
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Xiamen Tianma Display Technology Co Ltd
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Priority to CN202210294935.XA priority Critical patent/CN114677948A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The application discloses a display panel and a display device. The display panel includes a pixel circuit and a light emitting element; the pixel circuit comprises a driving transistor, a compensation transistor and a first initialization transistor; the driving transistor is used for providing driving current for the light-emitting element; the compensation transistor is used for providing a data signal for the driving transistor; the first initialization transistor is used for providing an initialization signal for the driving transistor; the compensation transistor and the first initialization transistor are oxide transistors comprising a first grid and a second grid, one of the first grid and the second grid of the compensation transistor and the first initialization transistor is connected with a reference signal, and the other one of the first grid and the second grid of the compensation transistor and the first initialization transistor is respectively connected with a compensation signal and a first initialization signal; the signal voltage of the reference signal is lower than the effective signal voltage of the compensation signal and the first initialization signal. According to the embodiment of the application, the compatibility of different types of transistors can be realized by adjusting the threshold voltage of the oxide transistor, and the uniformity and the stability of the transistor are improved.

Description

Display panel and display device
Technical Field
The application belongs to the technical field of display, and particularly relates to a display panel and a display device.
Background
At present, a display panel is composed of a plurality of pixel circuits and a plurality of light emitting elements arranged in an array, and the pixel circuits are generally composed of TFTs (thin film transistors) and capacitors.
In the existing pixel circuit, a hybrid thin film transistor (hybird TFT) process is generally employed to simultaneously dispose an oxide transistor and other types of transistors in the pixel circuit. For example, the pixel circuit can be compatible with an IGZO (Indium-Gallium-Zinc-Oxide) TFT and an LTPS (Low Temperature polysilicon) TFT.
In the hybrid TFT process, the threshold voltage of the oxide transistor is easy to drift due to insufficient stability of the oxide transistor, and the threshold voltage of the oxide transistor cannot be effectively corrected and adjusted, so that the oxide transistor cannot be compatible with other types of transistors.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which can solve the technical problem that the threshold voltage of an oxide transistor is difficult to correct and adjust, so that the oxide transistor cannot be compatible with other types of transistors.
In a first aspect, an embodiment of the present application provides a display panel including a pixel circuit and a light emitting element;
the pixel circuit comprises a driving transistor, a compensation transistor and a first initialization transistor;
the driving transistor is used for providing a driving current for the light-emitting element;
the compensation transistor is used for providing a data signal for the driving transistor;
the first initialization transistor is used for providing an initialization signal for the driving transistor;
the compensation transistor and the first initialization transistor are oxide transistors comprising a first grid and a second grid, one of the first grid and the second grid of the compensation transistor is connected with a reference signal, and the other one of the first grid and the second grid of the compensation transistor is connected with a compensation signal; one of a first grid and a second grid of the first initialization transistor is connected with a reference signal, and the other one is connected with a first initialization signal; the signal voltage of the reference signal is lower than the effective signal voltage of the compensation signal and the effective signal voltage of the first initialization signal.
In a second aspect, an embodiment of the present application provides a display device, including the above display panel.
Compared with the prior art, according to the display panel provided by the embodiment of the application, the compensation transistor and the first initialization transistor in the pixel circuit are arranged to be the oxide transistor with two gates, and one of the two gates of the two oxide transistors is connected with the reference signal, so that the threshold voltages of the two transistors can be adjusted through the reference signal, the threshold voltages of the two transistors are respectively located in the adjustment ranges of the compensation signal and the first initialization signal, the correction and adjustment of the threshold voltage of the oxide transistor are realized, and the oxide transistor and the low-temperature polysilicon transistor in the pixel circuit can be compatible. The uniformity of the characteristics of the oxide transistor device is improved, and the display uniformity of the display panel is guaranteed. And the signal voltage of the reference signal is set to be lower than the compensation signal and the first initialization signal valid signal voltage, so that the reference signal can be prevented from influencing the conducting state of the oxide transistor.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an oxide transistor according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of an oxide transistor provided in accordance with an embodiment of the present application;
fig. 4 is a schematic structural diagram of a display panel according to another embodiment of the present application;
fig. 5 is a schematic structural diagram of a display panel according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of a display panel according to still another embodiment of the present application;
fig. 7 is a schematic structural diagram of an oxide transistor according to another embodiment of the present application;
FIG. 8 is a schematic cross-sectional view of an oxide transistor according to another embodiment of the present application;
FIG. 9 is a schematic diagram of a display panel according to yet another embodiment of the present application;
FIG. 10 is a diagram illustrating a bottom-gate signal voltage and a threshold voltage of an oxide transistor according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present application.
In the drawings:
1. a pixel circuit; PVDD, a first power supply signal; PVEE, a second power supply new signal; m1, a first light emitting control transistor; m2, data write transistor; m3, a drive transistor; m4, compensation transistor; m5, a first initialization transistor; m6, a second emission control transistor; m7, a second initialization transistor; cst, storage capacitor; l, a light-emitting element; REF, reference signal; REF1, first reference signal; REF2, second reference signal; S1N, a first initialization signal; S2N, compensating signals; vref; initializing a signal; s2, data write signal; vdata, a data signal; emit, light emission control signal.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The embodiments will be described in detail below with reference to the accompanying drawings.
At present, a display panel is composed of a plurality of pixel circuits and a plurality of light emitting elements arranged in an array, and the pixel circuits are generally composed of TFTs and capacitors. In the existing pixel circuit, hybrid TFT technology is usually adopted, i.e. both oxide TFT and other types of TFT are compatible in the pixel circuit. In the hybrid TFT process, due to insufficient stability of the oxide transistor, the threshold voltage of the oxide transistor cannot be corrected and adjusted, so that the threshold voltage of the oxide transistor is easily shifted, and thus the oxide transistor cannot be compatible with other types of transistors.
In order to solve the above technical problem, an embodiment of the present application provides a display panel and a display device. The following first describes a display panel provided in an embodiment of the present application.
Fig. 1 shows a schematic structural diagram of a display panel according to an embodiment of the present application. The display panel includes a pixel circuit 1 and a light emitting element L, and the pixel circuit 1 includes a driving transistor M3, a compensation transistor M4, and a first initialization transistor M5.
The first initialization transistor M5 may provide the initialization signal Vref for the driving transistor M3, the compensation transistor M4 may provide the data signal Vdata for the driving transistor M3, and the driving transistor M3 may provide the driving current for the light emitting element L, so that the light emitting element L emits light under the driving of the driving current.
The compensation transistor M4 and the first initialization transistor M5 are each an oxide transistor including a first gate and a second gate, and one of the first gate and the second gate of the compensation transistor M4 is connected to the reference signal REF, and the other gate is connected to the compensation signal S2N. Of the first and second gates of the first initialization transistor M5, one gate is connected to the reference signal REF, and the other gate is connected to the first initialization signal S1N. The signal voltage of the reference signal REF may be set lower than the effective signal voltage of the compensation signal S2N and lower than the effective signal voltage of the first initialization signal S1N.
In the hybrid TFT process, two different types of thin film transistors, i.e., a low temperature polysilicon transistor and an oxide transistor, may be provided in the pixel circuit 1. The two transistors have different characteristics respectively, for example, the projection area of the low-temperature polysilicon transistor is smaller than that of the oxide transistor, and the oxide transistor can improve the charging and discharging speed of the driving transistor M3, and can reduce the leakage current flowing through the transistor in an off state, so as to avoid the influence of the leakage current on the light-emitting effect. Among a plurality of thin film transistors constituting the pixel circuit 1, selection is made from low-temperature multi-transistor transistors and oxide transistors according to requirements of different transistors, so that device characteristics of different types of transistors can be considered, and the driving speed and stability of the pixel circuit 1 are improved. It is understood that the lower polysilicon transistors may be replaced by other types of transistors other than oxide transistors, and are not limited herein.
Two gates are provided on the compensation transistor M4 and the first initialization transistor M5, and one of the gates is connected to the reference signal REF, and the threshold voltages of the two transistors can be adjusted by the signal voltage of the reference signal REF.
Taking the compensation transistor M4 as an example, when the signal voltage of the reference signal REF is lowered, the threshold voltage of the compensation transistor M4 can be raised. By setting the signal voltage of the reference signal REF, the threshold voltage of the compensation transistor M4 can be adjusted to be within the driving range of the compensation signal S2N, so that the compensation signal S2N can realize switching control of the on or off state of the compensation transistor M4 by variation of the high and low levels. Likewise, by setting the signal voltage of the reference signal REF, the threshold voltage of the first initialization transistor M5 can also be adjusted to be within the driving range of the first initialization signal S1N, so that the first initialization transistor M5 can be normally driven to turn on or turn off by the first initialization signal S1N.
When the compensation transistor M4 receives the effective signal voltage of the compensation signal S2N, the compensation transistor M4 is turned on, and by setting the signal voltage of the reference signal REF to be lower than the effective signal voltage of the compensation signal S2N, the compensation transistor M4 can be prevented from being turned on when receiving the reference signal REF, so that the reference signal REF only plays a role of adjusting the threshold voltage of the transistor, and the on state of the transistor is not affected. Likewise, by setting the signal voltage of the reference signal REF to be lower than the effective signal voltage of the first initialization signal S1N, the first initialization transistor M5 can be prevented from being turned on upon receiving the reference signal REF.
In the present embodiment, by providing the compensation transistor M4 and the first initialization transistor M5 in the pixel circuit 1 as oxide transistors having two gates and connecting one of the gates of the two oxide transistors to the reference signal REF, the threshold voltages of the two transistors can be adjusted by the reference signal REF so that the threshold voltages of the two transistors are within the adjustment ranges of the compensation signal S2N and the first initialization signal S1N, respectively, correction adjustment of the threshold voltages of the oxide transistors is achieved, uniformity of the transistor device characteristics of the oxide transistors is improved, and the oxide transistors and the low-temperature silicon transistors in the pixel circuit 1 can be compatible. And setting the signal voltage of the reference signal REF lower than the effective signal voltage also makes it possible to prevent the reference signal REF from affecting the on state of the oxide transistor.
It is understood that the compensation signal S2N and the first initialization signal S1N may be scan signals provided by scan signal lines. In the pixel circuit 1 of the display panel, in order to avoid the increase of the frame area caused by the arrangement of more shift register cells in the frame area, the scanning signal lines are usually multiplexed, for example, the data write signal S2 and the compensation signal S2N in the same row can share the same scanning signal line. When the low temperature polysilicon transistor is usually a P-type transistor and the oxide transistor is usually an N-type transistor, it is necessary to invert the scanning signal before the gate of one of the two different types of transistors when the same scanning signal line is shared. That is, two different types of transistors can be controlled by the same scan signal. When there is a difference between the threshold voltage of the oxide transistor and the threshold voltage of the low temperature polysilicon transistor, the same scan signal cannot effectively control the on-states of the two types of transistors. By providing the reference signal REF for one of the two gates of the oxide transistor and adjusting the signal voltage of the reference signal REF, the threshold voltage of the oxide transistor can be corrected and adjusted, so that the difference between the adjusted threshold voltages of the oxide transistor and the low-temperature polysilicon transistor is reduced, and the control of the two transistors can be realized through the same scanning signal, namely the compatibility of the oxide transistor and the low-temperature polysilicon transistor is realized.
Referring to fig. 2, in some embodiments, the oxide transistor may include a first active layer, and the first gate and the second gate of the oxide transistor are respectively located on two sides of the first active layer in a first direction, where the first direction is a direction perpendicular to a plane of the display panel. One of the two gates of the oxide transistor is closer to the display panel than the first active layer, and the other gate of the oxide transistor is farther from the display panel than the first active layer. Namely, two grid electrodes of the oxide transistor are respectively positioned above and below the active layer, and the first grid electrode and the second grid electrode are of a top-bottom double-grid structure.
Referring to fig. 3, in the above embodiment, the oxide transistor is exemplified by an IGZO TFT, and the other types of transistors are exemplified by LTPS TFTs. Wherein the driving transistor M3 may be an LTPS TFT, and the compensating transistor M4 and the first initializing transistor M5 may be IGZO TFTs.
LTPS TFTs, typically P-type transistors, include a first gate electrode and a first active layer, with the first gate electrode being located above the first active layer. That is, LTPS TFTs are typically of a top gate structure.
The IGZO TFT is generally an N-type transistor, and includes a first gate electrode, a second gate electrode, and a first active layer, the first gate electrode being located above the first active layer, and the second gate electrode being located below the first active layer. That is, the IGZO TFT is generally a top-bottom double gate structure in which the first gate electrode is a top gate and the second gate electrode is a bottom gate.
As can be seen from fig. 2 and 3, in the IGZO TFT, the first gate electrode is connected to a shift register unit disposed in the non-display region, the shift register unit may provide the scan signal ScanN to the first gate electrode, and the second gate electrode is connected to the reference signal REF. It is to be understood that the first gate electrode of the LTPS TFT may be located at the same layer as the first gate electrode of the IGZO TFT, or may be located at the same layer as the second gate electrode of the IGZO TFT. Fig. 3 shows a schematic cross-sectional view of the first gate of the LTPS TFT in the same layer as the second gate of the IGZO TFT.
In some embodiments, the display panel may further include a substrate on which the pixel circuit 1 and the light emitting element L are disposed.
The first grid of the oxide transistor is positioned on one side of the first active layer far away from the substrate along the first direction, and the second grid is positioned on one side of the first active layer close to the substrate along the first direction. As shown in fig. 2, the first gate is a top gate of the oxide transistor, and the second gate is a bottom gate of the oxide transistor.
In some embodiments, the thickness of the gate insulating layer of the second gate of the oxide transistor is greater than the thickness of the gate insulating layer of the first gate. The second gate of the compensation transistor M4 is connected to the reference signal REF, and the second gate of the first initialization transistor M5 is connected to the reference signal REF.
The gate insulating layer is an insulating layer arranged between the gate and the first active layer, and the thickness of the insulating layer can be adjusted by adjusting the etching time and the concentration of etching liquid in the etching process of the thin film transistor. When the thickness of the gate insulating layer is increased, the driving capability of the gate to the thin film transistor can be improved; when the thickness of the gate insulating layer is reduced, the switching control capability of the gate to the thin film transistor can be improved.
In the oxide transistor having the dual gate structure, if the thicknesses of the gate insulating layers of the two gates are not the same, one gate having a thicker gate insulating layer may be connected to a stable low voltage signal, and the other gate having a thinner gate insulating layer may be connected to a scan signal for controlling the on/off of the transistor.
With reference to fig. 2, taking the compensation transistor M4 and the first initialization transistor M5 as an example, when the thickness of the gate insulating layer of the first gate is smaller than that of the gate insulating layer of the second gate, the second gate of the compensation transistor M4 may be connected to the reference signal REF, the second gate of the first initialization transistor M5 may also be connected to the reference signal REF, and the first gate of the compensation transistor M4 and the first gate of the first initialization transistor M5 may be connected to the corresponding compensation signal S2N and the corresponding first initialization signal S1N, respectively. The compensation signal S2N and the first initialization signal S1N may be scan signals ScanN provided by shift register cells in a non-display region other than the display region of the display panel.
The threshold voltages of the two oxide transistors can be kept stable and within the control range of the scan signal by forward-adjusting the threshold voltages of the two oxide transistors by the signal voltage of the reference signal REF. At this time, the first gate of the compensation transistor M4 is connected to the compensation signal S2N, and the first gate of the first initialization transistor M5 is connected to the first initialization signal S1N.
After the threshold voltages of the compensation transistor M4 and the first initialization transistor M5 are positively adjusted by the reference signal REF, the compensation transistor M4 is controlled to be turned on and off by the compensation signal S2N, and the first initialization transistor M5 is controlled to be turned on and off by the first initialization signal S1N.
In some embodiments, as shown in fig. 4, the compensation transistor M4 is connected to the reference signal REF through the second gate, and the first initialization transistor M5 is connected to the reference signal REF through the first gate. Alternatively, as shown in fig. 5, the compensation transistor M4 may be connected to the reference signal REF through a first gate, and the first initialization transistor M5 is connected to the reference signal REF through a second gate. That is, while one of the compensation transistor M4 and the first initialization transistor M5 is connected to the reference signal REF through a top gate, the other may be connected to the reference signal REF through a bottom gate.
Referring to FIG. 6, in some embodiments, the reference signals REF may include a first reference signal REF1 and a second reference signal REF 2. One of the two gates of the first initialization transistor M5 is connected to the first reference signal REF1, and one of the two gates of the compensation transistor M4 is connected to the second reference signal REF 2.
The signal voltage of the first reference signal REF1 and the signal voltage of the second reference signal REF2 may be set to different voltage values. The threshold voltage of the first initialization transistor M5 may be adjusted by adjusting the signal voltage of the first reference signal REF1, and the threshold voltage of the compensation transistor M4 may be adjusted by adjusting the signal voltage of the second reference signal REF 2. After the first reference signal REF1 and the second reference signal REF2 are respectively adjusted, the threshold voltages of the first initialization transistor M5 and the compensation transistor M4 can be adjusted to be within the control range of the scan signal, so that the problem that the threshold voltages of the two transistors cannot meet the control range of the scan signal when the same reference signal REF is used for adjustment is avoided.
Referring to fig. 6 and 7, taking the first initialization transistor M5 as an example, the first initialization transistor M5 may be an IGZO TFT, and the first gate of the first initialization transistor M5 is connected to a shift register unit disposed in the non-display region, which may provide the scan signal ScanN to the first gate. A second gate of the first initialization transistor M5 is electrically connected to the first reference signal REF 1. As shown in fig. 7, the driving transistor M3 may be an LTPS TFT, the gate of the driving transistor M3 is the first gate of the LTPS TFT, and the first gate of the LTPS TFT and the first gate of the first initialization transistor M5 may be located at the same layer.
In some embodiments, the signal voltages of the first and second reference signals REF1 and REF2 described above may be set based on the aspect ratio of the conduction channels of the two oxide transistors.
When the signal voltage of the first reference signal REF1 and the signal voltage of the second reference signal REF2 are consistent, if the width-to-length ratio of the conduction channel of the first initialization transistor M5 is greater than the width-to-length ratio of the conduction channel of the compensation transistor M4, the positive bias amplitude of the threshold voltage of the first initialization transistor M5 is greater than the positive bias amplitude of the compensation transistor M4, that is, the adjusted threshold voltage of the first initialization transistor M5 is greater than the threshold voltage of the compensation transistor M4. Since the compensation signal S2N and the first initialization signal S1N are both scan signals output by the scan signal line, and their high and low levels are equal or relatively similar, when there is a large difference between the threshold voltages of the first initialization transistor M5 and the compensation transistor M4, the scan signals cannot effectively control the compensation transistor M4 and the first initialization transistor M5 at the same time.
For an oxide transistor having a double gate structure, when the signal voltage of the reference signal REF of one of the gates is reduced, the threshold voltage of the transistor can be also positively biased. Conversely, when the signal voltage of the reference signal REF increases, the threshold voltage of the transistor can be negatively biased.
Based on the effect of the width-to-length ratio of the conduction channel of the transistor and the signal voltage of the reference signal REF on the threshold voltage of the transistor. When the width-to-length ratio of the conduction channel of the first initialization transistor M5 is greater than the width-to-length ratio of the conduction channel of the compensation transistor M4, since the threshold voltage of the first initialization transistor M5 is affected by the width-to-length ratio of the conduction channel and is greater than the threshold voltage of the compensation transistor M4, the threshold voltage of the first initialization transistor M5 can be decreased by increasing the signal voltage of the first reference signal REF1 at this time. By adjusting the width-to-length ratio of the conduction channel of the transistor and the signal voltage of the reference signal REF connected with the gate of the transistor, the threshold voltage of the transistor can be flexibly adjusted. After the display panel is manufactured, since the width-to-length ratio of the conductive channel cannot be adjusted any more, the threshold voltage of the transistor can be adjusted by adjusting the signal voltage of the reference signal REF.
In order to keep the threshold voltages of the first initialization transistor M5 and the compensation transistor M4 consistent or closer, the signal voltage magnitudes of the first reference signal REF1 and the second reference signal REF2 may be determined according to the width-to-length ratio of the conductive channel of the first initialization transistor M5 and the width-to-length ratio of the conductive channel of the compensation transistor M4. For example, the width-to-length ratio of the conduction channel of the oxide transistor and the signal voltage of the reference signal REF may be set to satisfy the following equation:
(M1W/L-M2W/L)*(Vref1-Vref2)>0；
wherein, M1W/LFor the aspect ratio of the conduction channel of the first initialization transistor M5, M2W/LTo compensate for the width-to-length ratio of the conduction channel of transistor M4, Vref1 is the signal voltage of the first reference signal REF1 and Vref2 is the signal voltage of the second reference signal REF 2. That is, when the width-to-length ratio of the conduction channel of the first initialization transistor M5 is greater than the width-to-length ratio of the conduction channel of the second compensation transistor M4, the signal voltage of the first reference signal REF1 may be set greater than the signal voltage of the second reference signal REF 2. The threshold voltages of the first initialization transistor M5 and the compensation transistor M4 are kept consistent or closer by a combination of the threshold voltage being forward biased by the increase of the conducting channel width-to-length ratio and the threshold voltage being reversely biased by the increase of the signal voltage of the reference signal REF.
It can be understood that, according to the above formula, when the width-to-length ratio of the conduction channel of the first initialization transistor M5 is smaller than the width-to-length ratio of the conduction channel of the second compensation transistor M4, the signal voltage of the first reference signal REF1 may be set to be smaller than the signal voltage of the second reference signal REF2, so that the threshold voltages of the two transistors are closer to each other, and it is avoided that the difference between the threshold voltages of the two transistors is too large, so that the scan signal cannot achieve effective control of the conduction states of the two transistors.
In some embodiments, the pixel circuit 1 may include a first pixel circuit and a second pixel circuit.
In the first pixel circuit, one of the first gate and the second gate of the first initialization transistor M5 is connected to the first reference signal REF1, and one of the first gate and the second gate of the compensation transistor M4 is connected to the second reference signal REF 2.
In the second pixel circuit, one of the first gate and the second gate of the first initialization transistor M5 is connected to the second reference signal REF2, and one of the first gate and the second gate of the compensation transistor M4 is connected to the first reference signal REF 1.
When the signal voltages of the first reference signal REF1 and the second reference signal REF2 are set to different signal voltages, in the first pixel circuit, one of the gates of the first initialization transistor M5 is connected to the first reference signal REF1, and one of the gates of the compensation transistor M4 is connected to the second reference signal REF 2. In the second pixel circuit, one gate of the first initialization transistor M5 is connected to the second reference signal REF2, and one gate of the compensation transistor M4 is connected to the first reference signal REF 1.
Taking the case that the signal voltage of the first reference signal REF1 is-3V and the signal voltage of the second reference signal REF2 is 0V as an example, in the first pixel circuit, one gate of the first initialization transistor M5 is connected to-3V, and one gate of the compensation transistor M4 is connected to 0V; in the second pixel circuit, one of the gates of the first initialization transistor M5 is connected to 0V, and one of the gates of the compensation transistor M4 is connected to-3V.
Referring to fig. 9, in some embodiments, the first pole of the compensation transistor M4 is connected to the second pole of the driving transistor M3, and the second pole of the compensation transistor M4 is connected to the gate of the driving transistor M3. The pixel circuit 1 may further include a light emission control transistor, a data writing transistor M2, and a second initialization transistor M7.
The light emission control transistor may be connected to the light emission control signal Emit, and selectively turned on under the control of the light emission control signal Emit to enable the light emitting element L to enter a light emission phase to Emit light under the drive of the drive current.
The data write transistor M2 may be connected to the first pole of the driving transistor M3 and selectively turned on under the control of the data write signal S2 to supply the data signal Vdata to the driving transistor M3.
The second initialization transistor M7 is connected to the first pole of the light emitting element L, and the second initialization transistor M7 may be selectively turned on under the control of the second initialization signal Vref to supply the initialization signal Vref to the driving transistor M3.
The pixel circuit 1 includes an initialization stage, a data writing stage, and a light emitting stage in this order in one light emitting period.
In the initialization phase, the first initialization transistor M5 and the second initialization transistor M7 are turned on under the control of the corresponding control signals, and the first initialization transistor M5 may switch the initialization signal Vref to the gate of the driving transistor M3 to initialize the gate voltage of the driving transistor M3; the second initialization transistor M7 may switch the initialization signal Vref into the first pole of the light emitting element L to initialize the first pole of the light emitting element L. The first electrode of the light emitting element L is an anode, and the second electrode is a cathode.
In the data writing phase, the first initialization transistor M5 and the second initialization transistor M7 are turned off, the data writing transistor M2, the driving transistor M3 and the compensation transistor M4 are turned on, and the data signal Vdata can be sequentially connected to the gate of the driving transistor M3 through the data writing transistor M2, the driving transistor M3 and the compensation transistor M4 to provide the data signal Vdata to the gate of the driving transistor M3. An energy storage capacitor Cst is further disposed between the gate of the driving transistor M3 and the first power signal PVDD, the data signal Vdata can charge the energy storage capacitor Cst, and the energy storage capacitor Cst can discharge during the light emitting period to control the driving transistor M3 to maintain the on state.
In the light emitting period, the data writing transistor M2 and the compensation transistor M4 are turned off, the light emitting control transistor M3 are turned on, the first pole of the light emitting device L is connected to the first power signal PVDD through the pixel circuit 1, and the second pole of the light emitting device L is connected to the second power signal PVEE. When the light emission control transistor and the driving transistor M3 are turned on, the light emitting element L can emit light under the drive of the driving current.
In some embodiments, the display panel may include a scan signal line, the scan signal line is connected to the gate of the data writing transistor M2, and the scan signal line may provide the data writing signal S2 to the data writing transistor M2, so that the data writing transistor M2 connects the data signal Vdata to the driving transistor M3 and the storage capacitor Cst under the driving of the data writing signal S2.
It is understood that a plurality of pixel circuits 1 are disposed on the display panel, the pixel circuits 1 may be arranged in an array, and the number of scanning signal lines may be set to be consistent with the number of rows of the pixel circuits 1. Each scanning signal line is electrically connected to the data writing transistor M2 in the pixel circuit 1 of the same row.
In the same pixel circuit 1, the scanning signal line connected to the gate of the data writing transistor M2 may also be connected to the gate of the second initialization transistor M7. That is, the data write transistor M2 and the second initialization transistor M7 may be kept turned on in synchronization or turned off in synchronization.
The light emission controlling transistors may be provided in two, a first light emission controlling transistor M1 and a second light emission controlling transistor M6, respectively. The first and second light emission control transistors M1 and M6 are connected in series with the first and second poles of the driving transistor M3, respectively. In the data writing stage, since the second emission control transistor M6 between the driving transistor M3 and the light emitting element L is turned off, when the data writing transistor M2 and the second initialization transistor M7 are turned on at the same time, the second emission control transistor M6 is turned off and kept isolated from each other, and does not affect each other.
It is to be understood that, when the gate of the second initialization transistor M7 shares the same scanning signal line with the gate of the data writing transistor M2, the second initialization transistor M7 is turned on in the data writing phase, and initializes the first pole of the light emitting element L. That is, the second initialization transistor M7 may be turned on in the initialization stage to initialize the first electrode of the light emitting element L, or may be turned on in the data writing stage to initialize the first electrode of the light emitting element L. The first initialization transistor M5 still needs to be turned on during the initialization phase when the gate of the driving transistor M3 is initialized.
By adjusting the on time of the second initialization transistor M7 from the initialization stage to the data writing stage, multiplexing of scanning signal lines can be achieved, reducing the circuit complexity and wiring cost of the display panel.
In some embodiments, the reference signal REF may be set to a negative potential signal.
Referring to fig. 10, when bottom gates of two gates of the oxide transistor are respectively connected to reference signals REF of different potentials, the detected threshold voltages of the oxide transistor are as shown in fig. 10. As the signal voltage of the reference signal REF decreases, the threshold voltage of the oxide transistor gradually increases. When the signal voltage of the reference signal REF is set to 0V, the threshold voltage of the oxide transistor is about-2.2V. According to the high and low level values of the scanning signal, to make the oxide transistor turn off at the low level and turn on at the high level, the reference signal REF can be set to be a negative potential signal, at this time, the threshold voltage of the oxide transistor is usually greater than-2V, the high level value of the scanning signal is greater than-2V, the low level value is less than-2V, and a certain voltage difference exists between the high and low level values and-2V, so that when the scanning signal is switched between the high and low levels, the on and off of the oxide transistor can be effectively controlled.
In some embodiments, taking the compensation transistor M4 as an example, when signal voltages with different voltage magnitudes are applied to the bottom gates of the oxide transistors:
1) when the same compensation signal S2N is applied to the top gate and the bottom gate of the oxide transistor, namely the top gate and the bottom gate are connected with the same scanning signal line, the threshold voltage Shift value DeltaVth Shift of the oxide transistor is 0.439V through testing;
2) when a compensation signal S2N is applied to the top gate of the oxide transistor and a reference signal REF with the voltage value of 0V is applied to the bottom gate of the oxide transistor, the threshold voltage Shift value delta Vth Shift of the oxide transistor is-0.066V through testing;
3) when the compensation signal S2N is applied to the top gate of the oxide transistor and the reference signal REF with the voltage value of-3V is applied to the bottom gate, the threshold voltage Shift value delta Vth Shift of the oxide transistor is tested to be-0.010V.
According to the drift degree of the threshold voltage of the transistor when different signal voltages are applied to the bottom gate, it can be determined that compared with a scanning signal in which the bottom gate of the oxide transistor is connected with the top gate, the bottom gate is electrically connected with the stable reference signal REF, so that the drift degree of the threshold voltage of the transistor can be reduced, and the stability of the threshold voltage of the transistor can be improved. In contrast to the reference signal REF with 0 potential applied to the bottom gate, when the reference signal REF with negative potential is applied to the bottom gate, the threshold voltage drift degree of the oxide transistor can be further reduced, and the stability of the oxide transistor can be greatly improved.
An embodiment of the present application further provides a display device, please refer to fig. 11, where the display device may be a PC, a television, a display, a mobile terminal, a tablet computer, a wearable device, and the like, and the display device may include the display panel provided in the embodiment of the present application.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principles and embodiments of the present application are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present application. It should be noted that there are no specific structures in the above description, and it will be apparent to those skilled in the art that various modifications, decorations, or changes can be made without departing from the principle of the present application, and the technical features can be combined in a suitable manner; such modifications, variations, or combinations, or other applications in which the concepts and the technical solutions of the present invention are applied without modification, are intended to be covered by the present invention.

Claims (13)

1. A display panel includes a pixel circuit and a light emitting element;
the pixel circuit comprises a driving transistor, a compensation transistor and a first initialization transistor;
the driving transistor is used for providing driving current for the light-emitting element;
the compensation transistor is used for providing a data signal for the driving transistor;
the first initialization transistor is used for providing an initialization signal for the driving transistor;
the compensation transistor and the first initialization transistor are oxide transistors comprising a first grid and a second grid, one of the first grid and the second grid of the compensation transistor is connected with a reference signal, and the other one of the first grid and the second grid of the compensation transistor is connected with a compensation signal; one of a first grid and a second grid of the first initialization transistor is connected with a reference signal, and the other one is connected with a first initialization signal; the signal voltage of the reference signal is lower than the effective signal voltage of the compensation signal and the effective signal voltage of the first initialization signal.
2. The display panel according to claim 1, wherein the oxide transistor further comprises a first active layer, and the first gate electrode and the second gate electrode are located on two sides of the first active layer in a first direction, wherein the first direction is a direction perpendicular to a plane of the display panel.
3. The display panel according to claim 2, wherein the display panel further comprises a substrate over which the pixel circuit and the light-emitting element are provided;
the first grid of the oxide transistor is positioned on one side of the first active layer, which is far away from the substrate along the first direction, and the second grid of the oxide transistor is positioned on one side of the first active layer, which is close to the substrate along the first direction.
4. The display panel according to claim 3, wherein a gate insulating layer thickness of the second gate of the oxide transistor is larger than a gate insulating layer thickness of the first gate of the oxide transistor;
the second grid of the compensation transistor is connected with a reference signal, and the second grid of the first initialization transistor is connected with the reference signal.
5. The display panel according to claim 3, wherein a first gate of the compensation transistor is connected to a reference signal, and a second gate of the first initialization transistor is connected to the reference signal;
or the second grid of the compensation transistor is connected with a reference signal, and the first grid of the first initialization transistor is connected with the reference signal.
6. The display panel according to claim 1, wherein the reference signal comprises a first reference signal and a second reference signal, one of the first gate and the second gate of the first initialization transistor is connected to the first reference signal, and one of the first gate and the second gate of the compensation transistor is connected to the second reference signal.
7. The display panel according to claim 6, wherein the width-to-length ratio of the conduction channel of the oxide transistor and the signal voltage of the reference signal satisfy the following equation:
(M1W/L-M2W/L)*(Vref1-Vref2)>0；
wherein, M1W/LM2 being the width-to-length ratio of the conduction channel of the first initialization transistorW/LFor the aspect ratio of the conduction channel of the compensation transistor, Vref1 is the signal voltage of the first reference signal and Vref2 is the signal voltage of the second reference signal.
8. The display panel according to claim 1, wherein the pixel circuit includes a first pixel circuit and a second pixel circuit, and the reference signal includes a first reference signal and a second reference signal;
in the first pixel circuit, one of the first gate and the second gate of the first initialization transistor is connected to a first reference signal, and one of the first gate and the second gate of the compensation transistor is connected to a second reference signal;
in the second pixel circuit, one of the first gate and the second gate of the first initialization transistor is connected to a second reference signal, and one of the first gate and the second gate of the compensation transistor is connected to a first reference signal.
9. The display panel according to claim 1, wherein a first pole of the compensation transistor is connected to a second pole of the driving transistor, and a second pole of the compensation transistor is connected to a gate of the driving transistor; the pixel circuit includes:
a light emission control transistor for selectively allowing the light emitting element to enter a light emission phase;
and the data writing transistor is connected to the first pole of the driving transistor and is used for providing a data signal for the driving transistor.
10. The display panel according to claim 9, wherein the pixel circuit further comprises:
a second initialization transistor connected to a first pole of the light emitting element for providing a second initialization signal to the light emitting element.
11. The display panel according to claim 10, characterized in that the display panel comprises:
a scanning signal line connected to a gate of the data writing transistor, the scanning signal line being configured to provide a scanning signal;
the scanning signal line is also connected to a gate of the second initialization transistor.
12. The display panel according to claim 1, wherein the reference signal is a negative potential signal.
13. A display device characterized by comprising the display panel according to any one of claims 1 to 12.
CN202210294935.XA 2022-03-24 2022-03-24 Display panel and display device Pending CN114677948A (en)

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CN111429836A (en) * 2020-04-09 2020-07-17 深圳市华星光电半导体显示技术有限公司 Pixel driving circuit and display panel
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