CN114675152A - Dynamic characteristic test system for power semiconductor device - Google Patents

Dynamic characteristic test system for power semiconductor device Download PDF

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Publication number
CN114675152A
CN114675152A CN202011552324.8A CN202011552324A CN114675152A CN 114675152 A CN114675152 A CN 114675152A CN 202011552324 A CN202011552324 A CN 202011552324A CN 114675152 A CN114675152 A CN 114675152A
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China
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switch
test
semiconductor device
power semiconductor
voltage
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Chinese (zh)
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柯俊吉
钟圣荣
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Shanghai Beiling Co Ltd
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Shanghai Beiling Co Ltd
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Priority to CN202011552324.8A priority Critical patent/CN114675152A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2637—Circuits therefor for testing other individual devices

Abstract

The invention discloses a dynamic characteristic test system of a power semiconductor device, which comprises a test host, wherein the test host integrates a high-voltage capacitor module, a low-voltage capacitor module, a second switching unit and at least one test topological circuit; the high-voltage capacitor module is used for storing preset high-voltage electric energy; the low-voltage capacitor module is used for storing preset low-voltage electric energy; the test topology circuit comprises a first switching unit and an interface for accessing the power semiconductor device to be tested, wherein the first switching unit is used for switching the test topology circuit so as to enable the power semiconductor device to be tested to be in different test states; the second switching unit is used for selecting the high-voltage capacitor module or the low-voltage capacitor module to supply power for the test topology circuit. The high-voltage and low-voltage capacitor segmentation method meets the requirement of wide voltage, the supporting components are reduced by testing the topological circuit, the size of the test system is reduced, the test efficiency is improved, and the safety and the reliability of the system are improved.

Description

Dynamic characteristic test system for power semiconductor device
Technical Field
The invention relates to the technical field of electronic component testing, in particular to a dynamic characteristic testing system of a power semiconductor device.
Background
The power semiconductor device is also called as a power electronic device and is mainly used for power electronic devices for electric energy conversion and circuit control of power equipment. The power semiconductor device electrical characteristic test comprises static characteristic test and dynamic characteristic test, is a main means for evaluating the device design and manufacturing level of each manufacturer, is also a practical tool for the device manufacturer to establish a specification, and provides an important reference for device type selection in the design of an actual application system. The static characteristic test of the device mainly comprises a transfer characteristic test, an output characteristic test, a blocking characteristic test and the like; the device dynamic characteristic test mainly comprises a device switch characteristic test, an inverse parallel diode recovery characteristic test, a device short circuit characteristic test and the like. When the power semiconductor device works, the power semiconductor device needs to bear dozens of to thousands of amperes of current or more than hundreds of volts, so the dynamic characteristic test is more rigorous to evaluate the voltage and current endurance capability of the device.
The existing dynamic test system for the power semiconductor device needs more matched components, so that the test system is large in size, generally very expensive in price and low in reliability. For example, a high-voltage relay or a high-voltage IGBT (Insulated Gate Bipolar Transistor) module is generally used as a switching element in a test system, and is easily interfered by the outside to generate a malfunction, which causes a fault in the test system. In addition, the conventional test system has poor universality for testing the dynamic characteristics of devices with different packages.
Disclosure of Invention
The invention aims to overcome the defects of more matched components, large volume, high system cost and low reliability of a dynamic test system of a power semiconductor device in the prior art, and provides the dynamic characteristic test system of the power semiconductor device.
The invention solves the technical problems through the following technical scheme:
the invention provides a dynamic characteristic test system of a power semiconductor device, which comprises a test host, wherein the test host integrates a high-voltage capacitor module, a low-voltage capacitor module, a second switching unit and at least one test topological circuit;
the high-voltage capacitor module is used for storing preset high-voltage electric energy;
the low-voltage capacitor module is used for storing preset low-voltage electric energy;
the test topology circuit comprises a first switching unit and an interface for accessing the power semiconductor device to be tested, wherein the first switching unit is used for switching the test topology circuit so as to enable the power semiconductor device to be tested to be in different test states;
the second switching unit is used for selecting the high-voltage capacitor module or the low-voltage capacitor module to supply power to the test topology circuit.
Preferably, the high-voltage capacitor module comprises a plurality of high-voltage large-capacity capacitors, and the low-voltage capacitor module comprises a plurality of low-voltage large-capacity capacitors connected in parallel;
the capacitance value of the high-voltage large-capacity capacitor is lower than that of the low-voltage large-capacity capacitor;
the high-voltage large-capacity capacitors are divided into a plurality of capacitor groups with the same number, the high-voltage large-capacity capacitors in the capacitor groups are connected in parallel, and the capacitor groups are connected in series;
each capacitor bank further comprises at least one first load resistor, and the high-voltage large-capacity capacitors in the capacitor banks are connected with the first load resistors in parallel to achieve voltage balance among the capacitor banks.
Preferably, the test host further comprises a plurality of different types of universal test sockets to adapt to different packaged power semiconductor devices to be tested.
Preferably, the universal test base is connected with the interface by a kelvin wiring method so as to separate a power loop current and a driving loop current of the power semiconductor device to be tested.
Preferably, the test topology circuit includes a load unit and two interfaces, where the two interfaces are a first interface and a second interface, respectively, and the first interface and the second interface include a first power end and a second power end, respectively;
the first switching unit comprises a fifth switch, a sixth switch, a seventh switch and an eighth switch;
one end of the fifth switch and one end of the seventh switch are both electrically connected with the first power supply end of the first interface;
the other end of the fifth switch, one end of the sixth switch and one end of the load unit are respectively electrically connected with the second power end of the first interface and the first power end of the second interface;
the other end of the load unit, the other end of the seventh switch and one end of the eighth switch are electrically connected;
the other end of the sixth switch and the other end of the eighth switch are electrically connected with a second power supply end of the second interface respectively.
Preferably, the load unit includes a plurality of load inductors and a switch, and the switch is configured to control the load inductors to be connected in series and in parallel to achieve different inductance values.
Preferably, the second switching unit includes a third switch and a fourth switch, both the third switch and the fourth switch are single-pole double-throw switches, the third switch is used for selecting a positive pole of the high-voltage capacitor module or a positive pole of the low-voltage capacitor module to be electrically connected with the test topology circuit, and the fourth switch is used for selecting a negative pole of the high-voltage capacitor module or a negative pole of the low-voltage capacitor module to be electrically connected with the test topology circuit.
Preferably, the switches included in the power semiconductor device dynamic characteristic testing system of any combination of the above items are all plug-in switches.
Preferably, the power semiconductor device dynamic characteristic test system further comprises a power supply module and a charge-discharge control module, wherein the charge-discharge control module is electrically connected with the power supply module, the high-voltage capacitor module and the low-voltage capacitor module respectively;
the charge and discharge control module comprises a first switch, a second switch and a second load resistor;
one end of the first switch is electrically connected with the positive electrode of the power supply module, and the other end of the first switch is electrically connected with one end of the second switch, the positive electrode of the high-voltage capacitor module and the positive electrode of the low-voltage capacitor module;
the other end of the second switch is electrically connected with one end of the second load resistor;
the other end of the second load resistor is electrically connected with the negative electrode of the power supply module, the negative electrode of the high-voltage capacitor module and the negative electrode of the low-voltage capacitor module.
Preferably, the power semiconductor device dynamic characteristic test system further comprises an upper computer, a signal generator and an oscilloscope, and a drive board is further integrated in the test host;
the upper computer is used for controlling the signal generator to generate a double-pulse signal and outputting the double-pulse signal to the driving board, and the driving board is used for amplifying the power of the double-pulse signal and then transmitting the power to the power semiconductor device to be tested; the oscilloscope is used for acquiring a test signal corresponding to the power semiconductor device to be tested and transmitting the test signal to the upper computer;
and the upper computer is used for analyzing and processing the test signal so as to obtain the dynamic characteristic of the power semiconductor device to be tested.
Preferably, the power semiconductor device dynamic characteristic test system further comprises a temperature adjusting module, and the temperature adjusting module is used for adjusting the temperature of the power semiconductor device to be tested.
The positive progress effects of the invention are as follows:
(1) by adopting a high-low voltage capacitor segmentation method, the high-voltage capacitor module and the low-voltage capacitor module are integrated in the test host, so that the wider voltage requirement of the power semiconductor device test is met, the capacitance value of the capacitor can be selected according to actual requirements, the size of a test system is obviously reduced, and the cost of the test system is reduced.
(2) The test topology circuit is switched through the first switching unit, so that the test of the switching characteristic, the reverse recovery characteristic and the short-circuit characteristic of the power semiconductor device to be tested is realized, compared with a method for changing the circuit topology through mechanical disassembly and assembly, the time consumed by switching the circuit topology is reduced, the test efficiency is greatly improved, and the test process and the operation complexity are reduced; compared with the method adopting a high-voltage relay or a high-voltage IGBT module to switch the circuit topology, the method greatly reduces the required matching components of the test system, reduces the volume of the test system, reduces the cost of the test system and also improves the reliability of the system.
Drawings
Fig. 1 is a block diagram showing a configuration of a power semiconductor device dynamic characteristic test system according to embodiment 1 of the present invention.
Fig. 2 is a schematic circuit diagram of a power semiconductor device dynamic characteristic test system according to embodiment 2 of the present invention.
Fig. 3 is a circuit configuration diagram of the load unit in embodiment 2 of the present invention.
FIG. 4a is a schematic diagram of a non-Kelvin connection between a conventional universal socket and a device under test.
Fig. 4b is a schematic diagram of the kelvin connection between the universal test socket and the power semiconductor device to be tested in embodiment 2 of the present invention.
FIG. 5a is a schematic circuit diagram of a non-Kelvin connection of a conventional universal socket and a device under test.
Fig. 5b is a schematic circuit diagram of the kelvin connection between the universal test socket and the power semiconductor device to be tested in embodiment 2 of the present invention.
Fig. 6 is a block diagram showing a configuration of a power semiconductor device dynamic characteristic test system according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 1, the present embodiment provides a power semiconductor device dynamic characteristic testing system, which includes a testing host 1, wherein the testing host 1 integrates a high-voltage capacitor module 2, a low-voltage capacitor module 3, a second switching unit 4 and at least one testing topology circuit 5; the high-voltage capacitor module 2 is used for storing preset high-voltage electric energy; the low-voltage capacitor module 3 is used for storing preset low-voltage electric energy; the test topology circuit 5 comprises a first switching unit 6 and an interface 7 for accessing the power semiconductor device to be tested, wherein the first switching unit 6 is used for switching the test topology circuit 5 so as to enable the power semiconductor device to be tested to be in different test states; the second switching unit 4 is configured to select the high-voltage capacitor module 2 or the low-voltage capacitor module 3 to supply power to the test topology circuit 5.
In addition, according to the test requirement, the dynamic characteristic test system of the power semiconductor device can comprise a plurality of test topological circuits, and simultaneously carry out dynamic characteristic test on a plurality of power semiconductor devices to be tested so as to improve the test efficiency.
The dynamic characteristic testing system of the power semiconductor device adopts a high-low voltage capacitor segmentation method, and integrates a high-voltage capacitor module and a low-voltage capacitor module in a testing host, so that the wider voltage requirement of the power semiconductor device testing is met, and a high-voltage capacitor with a high voltage and a high capacitance value is not required to be configured any more due to the segmented arrangement of the capacitors, so that the high-voltage capacitor can select the high-voltage capacitor with a low capacitance value according to the actual requirement, the volume of the testing system is obviously reduced, and the cost of the testing system is reduced; the test topology circuit is switched through the first switching unit, so that the test on the switching characteristic, the reverse recovery characteristic and the short-circuit characteristic of the power semiconductor device to be tested can be realized, and compared with a method for changing the circuit topology through mechanical disassembly and assembly, the time consumed by switching the circuit topology is reduced, the test efficiency is greatly improved, and the test process and the operation complexity are reduced; compared with the method adopting a high-voltage relay or a high-voltage IGBT module to switch the circuit topology, the method greatly reduces the required matching components of the test system, reduces the volume of the test system, reduces the cost of the test system and also improves the reliability of the system.
Example 2
The dynamic characteristic test system of the power semiconductor device of the embodiment is a further improvement of the embodiment 1, and specifically:
as shown in fig. 2, the high-voltage capacitor module 2 includes a plurality of high-voltage large-capacity capacitors, and the low-voltage capacitor module 3 includes a plurality of low-voltage large-capacity capacitors connected in parallel; the capacitance value of the high-voltage large-capacity capacitor is lower than that of the low-voltage large-capacity capacitor. It should be noted that the ranges of high pressure and low pressure in this embodiment are known to those skilled in the art; the capacitance of the high-voltage capacitor is thousands of muF, and the capacitance of the low-voltage capacitor is tens of thousands of muF (microfarads).
In the embodiment, the high-voltage large-capacity capacitors are divided into a plurality of capacitor groups with the same number, the high-voltage large-capacity capacitors in the capacitor groups are connected in parallel, and the capacitor groups are connected in series; each capacitor bank also includes at least one first load resistor 34, and the high-voltage bulk capacitors in the capacitor banks are connected in parallel with the first load resistor 34 to implement voltage equalization between the capacitor banks. The first load resistor 34 is a high voltage precision resistor.
The second switching unit 4 comprises a third switch 13 and a fourth switch 14, both the third switch 13 and the fourth switch 14 are single-pole double-throw switches, the third switch 13 is used for selecting the positive pole of the high-voltage capacitor module 2 or the positive pole of the low-voltage capacitor module 3 to be electrically connected with the test topology circuit 5, and the fourth switch 14 is used for selecting the negative pole of the high-voltage capacitor module 2 or the negative pole of the low-voltage capacitor module 3 to be electrically connected with the test topology circuit 5. Specifically, the fixed ends of the third switch 13 and the fourth switch 14 are electrically connected to the test topology circuit 5, and the movable ends of the third switch 13 and the fourth switch 14 are electrically connected to the high-voltage capacitor module 2 and the low-voltage capacitor module 3, respectively.
The dynamic characteristic test system of the power semiconductor device adopts a high-low voltage capacitor segmentation method, a high-voltage capacitor module 2 and a low-voltage capacitor module 3 are integrated in a test host 1, and a third switch 13 and a fourth switch 14 are utilized to select the high-voltage capacitor module 2 or the low-voltage capacitor module 3 to access a circuit, so that the wider voltage requirement of the power semiconductor device test is met, the use of a high-voltage high-capacitance capacitor is avoided, the volume of the test system can be obviously reduced, and the cost of the test system is reduced.
The test topology circuit 5 includes a load unit 8 and two interfaces for accessing the power semiconductor device to be tested, the two interfaces are a first interface 71 and a second interface 72, respectively, and the first interface 71 and the second interface 72 include a first power supply terminal and a second power supply terminal, respectively.
The first switching unit 6 includes a fifth switch 9, a sixth switch 10, a seventh switch 11, and an eighth switch 12; one end of the fifth switch 9 and one end of the seventh switch 11 are both electrically connected to the first power terminal of the first interface 71; the other end of the fifth switch 9, one end of the sixth switch 10, and one end of the load unit 8 are electrically connected to the second power terminal of the first interface 71 and the first power terminal of the second interface 72, respectively; the other end of the load unit 8, the other end of the seventh switch 11, and one end of the eighth switch 12 are electrically connected; the other end of the sixth switch 10 and the other end of the eighth switch 12 are electrically connected to the second power terminal of the second interface 72, respectively.
Specifically, when the fifth switch 9, the sixth switch 10 and the eighth switch 12 are turned off and the seventh switch 11 is turned on, the test topology circuit 5 is configured to test the switching characteristics of the power semiconductor device to be tested of the second interface 72 and the reverse recovery characteristics of the power semiconductor device to be tested of the first interface 71; when the fifth switch 9, the sixth switch 10 and the seventh switch 11 are turned off and the eighth switch 12 is turned on, the test topology circuit 5 is used for testing the switching characteristics of the power semiconductor device to be tested of the first interface 71 and the reverse recovery characteristics of the power semiconductor device to be tested of the second interface 72; when the sixth switch 10, the seventh switch 11 and the eighth switch 12 are turned off and the fifth switch 9 is turned on, the test topology circuit 5 is used for testing the short-circuit characteristic of the power semiconductor device to be tested of the second interface 72; when the fifth switch 9, the seventh switch 11 and the eighth switch 12 are turned off and the sixth switch 10 is turned on, the test topology circuit 5 is used for testing the short-circuit characteristic of the power semiconductor device to be tested of the first interface 71.
The test topology circuit 5 is switched through the fifth switch 9, the sixth switch 10, the seventh switch 11 and the eighth switch 12, so that the reverse recovery characteristic and the short-circuit characteristic of two power semiconductor devices to be tested can be tested at the same time, compared with a mode of changing the circuit topology by mechanical disassembly and assembly, the time consumed by switching the circuit topology is reduced, the complexity of the test process and operation is reduced, and the test efficiency is greatly improved.
The power semiconductor device dynamic characteristic test system further comprises a power supply module 15 and a charge-discharge control module 16, wherein the charge-discharge control module 16 is respectively and electrically connected with the power supply module 15, the high-voltage capacitor module 2 and the low-voltage capacitor module 3; the charge and discharge control module 16 includes a first switch 17, a second switch 18, and a second load resistor 19; one end of the first switch 17 is electrically connected with the anode of the power module 15, and the other end of the first switch 17 is electrically connected with one end of the second switch 18, the anode of the high-voltage capacitor module 2 and the anode of the low-voltage capacitor module 3; the other end of the second switch 18 is electrically connected to one end of a second load resistor 19; the other end of the second load resistor 19 is electrically connected to the negative electrode of the power module 15 and the stationary end of the fourth switch 14. The first switch 17 and the second switch 18 are ship-shaped switches.
Before testing, the first switch 17 is used for controlling the power supply module 15 to charge the high-voltage capacitor module 2 and the low-voltage capacitor module 3, and after testing, the second switch 18 and the second load resistor 19 are used for discharging the high-voltage capacitor module 2 and the low-voltage capacitor module 3, so that the safety and reliability of the testing system are improved.
As shown in fig. 3, the load unit 8 includes a plurality of load inductors and switches for controlling the load inductors to be connected in series and in parallel to realize different inductance values.
Specifically, in this embodiment, the load unit 8 includes three adjustable load inductance circuits connected in parallel, which are a first adjustable load inductance circuit 20, a second adjustable load inductance circuit 21, and a third adjustable load inductance circuit 22.
The first adjustable load inductor circuit 20 includes two first inductors 23, a first switch 24, a second switch 25, and a third switch 26. When the first switch 24 is closed, the second switch 25 is opened, and the third switch 26 is closed, the two first inductors 23 are connected in parallel; when the first switch 24 is open, the second switch 25 is closed, and the third switch 26 is open, the two first inductors 23 are connected in series; when the first switch 24 is turned off, the second switch 25 is turned off, and the third switch 26 is turned on, or when the first switch 24 is turned on, the second switch 25 is turned off, and the third switch 26 is turned off, only one first inductor 23 is connected to the circuit. The first adjustable load inductor circuit 20 can achieve 3 inductance values.
Similarly, the second adjustable load inductor circuit 21 and the third adjustable load inductor circuit 22 may also implement 3 inductance values. When the first, second and third adjustable load inductance circuits 20, 21, 22 use three different inductance values, the load unit 8 can realize nine different inductance values of 25 μ H (microhenry), 50 μ H, 100 μ H, 125 μ H, 250 μ H, 500 μ H, 750 μ H, 1500 μ H, 3000 μ H.
During implementation, the method that the banana head type female seat and the short connector are combined is adopted for the change-over switch of the load unit 8, a mechanical switch or a high-cost electronic switch element is replaced, the change-over switch is used for adjusting the inductance value of the load unit 8 according to test requirements before testing, the testing requirement of a wide current range is met, the testing operation is simpler, less time is consumed, the reliability of a testing system is further improved, and the cost of the testing system is reduced.
The switches included in the dynamic characteristic test system of the power semiconductor device are all plug-in switches. Specifically, the third switch 13, the fourth switch 14, the fifth switch 9, the sixth switch 10, the seventh switch 11, and the eighth switch 12 are all realized by a combination of a plug-in banana head type female socket and a short-circuit male head.
The existing commercial test system generally adopts a high-voltage relay or a high-voltage IGBT module as a switch element, so that the cost of the test system is higher, the switching of a test topological circuit is realized by adopting the combination of a plug-in banana head type female seat and a short-circuit male head, the switching of a high-voltage mode and a low-voltage mode is realized, the system cost is obviously reduced, and the system reliability is improved.
The test mainframe 1 also includes a number of different kinds of universal test sockets to accommodate different packages of power semiconductor devices to be tested. In the specific implementation, in order to facilitate interconnection between the surface-mount type power semiconductor device to be tested and the interface 7, a mode of combining the test socket and the adapter plate is adopted.
In this embodiment, the test socket is connected to the interface by using the kelvin wiring method, so that the power loop current and the driving loop current of the power semiconductor device to be tested can be separated. In specific implementation, for discrete devices packaged by the transistor, Kelvin wiring is directly realized in a wiring mode of an elastic sheet in the test socket; for the surface-mounted power semiconductor device to be tested, pins of the power semiconductor device to be tested are led out through the universal test base, Kelvin wiring is achieved on the PCB adapter plate through the universal test base, and finally the pins are led out to the test main board through the welding pins, so that dynamic characteristic test of the surface-mounted power semiconductor device to be tested is achieved.
As shown in fig. 4a, the universal test socket is connected to the power semiconductor device to be tested by clamping pins 33 of the power semiconductor device to be tested by using a plurality of pairs of spring plates 32, and when non-kelvin connections are adopted, two pins of each pair of spring plates are electrically connected. As shown in fig. 4b, the kelvin connection is achieved by disconnecting the two pins of each pair of spring plates 32.
Under the Kelvin connection mode, the power loop current and the driving loop current of the power semiconductor device to be tested are separated at the contact point of the pin of the power semiconductor device to be tested and the elastic sheet of the test socket. The device insertion depth is assumed to be the same in both Kelvin and non-Kelvin connection modes. As shown in FIG. 5a, in the non-Kelvin connection mode, the common-source or emitter parasitic inductance is the pin parasitic inductance and the spring parasitic inductance L of the power semiconductor device to be testedsocketAnd a PCB (Printed Circuit Board) current path parasitic inductance LtraceAnd (4) summing. As shown in FIG. 5b, the parasitic inductance of the common source or the emitter is only the parasitic inductance L of the pin of the power semiconductor device to be tested in the Kelvin connection modelead. Therefore, the influence of the parasitic inductance of the external circuit lead on the switching characteristic of the power semiconductor device to be tested can be eliminated by adopting the Kelvin connection mode.
As shown in fig. 6, the dynamic characteristic testing system for the power semiconductor device further includes an upper computer 27, a signal generator 28 and an oscilloscope 29, and a driving board 30 is further integrated in the testing host 1.
The upper computer 27 is used for controlling the signal generator 28 to generate a double-pulse signal and outputting the double-pulse signal to the driving board 30, and the driving board 30 is used for amplifying the power of the double-pulse signal and transmitting the power to the power semiconductor device to be tested; the oscilloscope 29 is used for collecting the test signal corresponding to the power semiconductor device to be tested and transmitting the test signal to the upper computer.
The upper computer 27 is used for analyzing and processing the test signal to obtain the dynamic characteristics of the power semiconductor device to be tested.
The power semiconductor device dynamic characteristic test system further comprises a temperature adjusting module 31, and the temperature adjusting module 31 is used for adjusting the temperature of the power semiconductor device to be tested.
The dynamic characteristic testing system of the power semiconductor device adopts a high-low voltage capacitor segmentation method, integrates a plurality of high-voltage capacitors with lower capacitance values and low-voltage capacitors with higher capacitance values in a testing host, and selects a high-voltage capacitor module or a low-voltage capacitor module to supply power through a plug-in switch, so that the wider voltage requirement of the power semiconductor device testing is met, the size of the testing system is obviously reduced, the cost of the testing system is reduced, and the safety and reliability of the system are improved; the testing of the switching characteristic, the reverse recovery characteristic and the short-circuit characteristic of the power semiconductor device to be tested is realized by switching the testing topological circuit through the plug-in switch and adjusting the inductance value of the load unit, and the reverse recovery characteristic and the short-circuit characteristic of the two power semiconductor devices to be tested can be tested simultaneously, so that the supporting components required by the testing system are greatly reduced, the size of the testing system is reduced, the time consumed by circuit topology switching is reduced, the testing efficiency is greatly improved, the complexity of the testing process and operation is reduced, and the safety and reliability of the system are improved; the dynamic characteristic test system of the power semiconductor device is provided with a plurality of different types of universal test seats, and the universal test seats are connected with the interface by using a Kelvin wiring method, so that the dynamic characteristic test system of the power semiconductor device can be compatible with different power semiconductor devices to be tested, and the influence of the parasitic inductance of a lead of an external circuit on the switching characteristic of the power semiconductor device to be tested is greatly reduced; the temperature of the power semiconductor device to be tested is adjusted through the temperature adjusting module, so that the test environment and the result are closer to the working environment of the power semiconductor device to be tested.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (10)

1. The power semiconductor device dynamic characteristic test system is characterized by comprising a test host, wherein the test host integrates a high-voltage capacitor module, a low-voltage capacitor module, a second switching unit and at least one test topology circuit;
the high-voltage capacitor module is used for storing preset high-voltage electric energy;
the low-voltage capacitor module is used for storing preset low-voltage electric energy;
the test topology circuit comprises a first switching unit and an interface for accessing the power semiconductor device to be tested, wherein the first switching unit is used for switching the test topology circuit so as to enable the power semiconductor device to be tested to be in different test states;
the second switching unit is used for selecting the high-voltage capacitor module or the low-voltage capacitor module to supply power to the test topology circuit.
2. The power semiconductor device dynamic characteristic test system of claim 1, wherein the high voltage capacitance module comprises a plurality of high voltage large capacity capacitors, and the low voltage capacitance module comprises a plurality of low voltage large capacity capacitors connected in parallel;
the capacitance value of the high-voltage large-capacity capacitor is lower than that of the low-voltage large-capacity capacitor;
the high-voltage large-capacity capacitors are divided into a plurality of capacitor groups with the same number, the high-voltage large-capacity capacitors in the capacitor groups are connected in parallel, and the capacitor groups are connected in series;
each capacitor bank further comprises at least one first load resistor, and the high-voltage large-capacity capacitors in the capacitor banks are connected with the first load resistors in parallel to achieve voltage balance among the capacitor banks.
3. The power semiconductor device dynamic characteristics testing system of claim 1, wherein the test mainframe further comprises a plurality of different types of universal test sockets to adapt to different packaged power semiconductor devices to be tested.
4. The power semiconductor device dynamic characteristic testing system of claim 3, wherein the universal test base is connected to the interface using Kelvin wiring to separate a power loop current and a drive loop current of the power semiconductor device under test.
5. The power semiconductor device dynamic characteristic testing system according to claim 1, wherein the test topology circuit includes a load unit and two of the interfaces, the two interfaces being a first interface and a second interface, respectively, the first interface and the second interface including a first power supply terminal and a second power supply terminal, respectively;
the first switching unit comprises a fifth switch, a sixth switch, a seventh switch and an eighth switch;
one end of the fifth switch and one end of the seventh switch are both electrically connected with the first power end of the first interface;
the other end of the fifth switch, one end of the sixth switch and one end of the load unit are respectively electrically connected with the second power end of the first interface and the first power end of the second interface;
the other end of the load unit, the other end of the seventh switch and one end of the eighth switch are electrically connected;
the other end of the sixth switch and the other end of the eighth switch are electrically connected with a second power supply end of the second interface respectively.
6. The power semiconductor device dynamic characteristic test system of claim 5, wherein the load unit comprises a plurality of load inductors and a change-over switch, the change-over switch is used for controlling the load inductors to be connected in series and in parallel so as to realize different inductance values.
7. The power semiconductor device dynamic characteristic testing system according to claim 1, wherein the second switching unit includes a third switch and a fourth switch, the third switch and the fourth switch are both single-pole double-throw switches, the third switch is used for selecting a positive pole of the high-voltage capacitor module or a positive pole of the low-voltage capacitor module to be electrically connected with the test topology circuit, and the fourth switch is used for selecting a negative pole of the high-voltage capacitor module or a negative pole of the low-voltage capacitor module to be electrically connected with the test topology circuit.
8. The power semiconductor device dynamic characteristic test system according to any one of claims 1 to 7, wherein the switches included in the power semiconductor device dynamic characteristic test system are all plug-in switches.
9. The power semiconductor device dynamic characteristic test system according to claim 1, further comprising a power supply module and a charge-discharge control module, wherein the charge-discharge control module is electrically connected to the power supply module, the high-voltage capacitor module and the low-voltage capacitor module, respectively;
the charge and discharge control module comprises a first switch, a second switch and a second load resistor;
one end of the first switch is electrically connected with the positive electrode of the power supply module, and the other end of the first switch is electrically connected with one end of the second switch, the positive electrode of the high-voltage capacitor module and the positive electrode of the low-voltage capacitor module;
the other end of the second switch is electrically connected with one end of the second load resistor;
the other end of the second load resistor is electrically connected with the negative electrode of the power supply module, the negative electrode of the high-voltage capacitor module and the negative electrode of the low-voltage capacitor module.
10. The power semiconductor device dynamic characteristic test system according to claim 1, wherein the power semiconductor device dynamic characteristic test system further comprises an upper computer, a signal generator and an oscilloscope, and a driving board is further integrated in the test host computer;
the upper computer is used for controlling the signal generator to generate a double-pulse signal and outputting the double-pulse signal to the driving board, and the driving board is used for amplifying the power of the double-pulse signal and then transmitting the power to the power semiconductor device to be tested; the oscilloscope is used for acquiring a test signal corresponding to the power semiconductor device to be tested and transmitting the test signal to the upper computer;
the upper computer is used for analyzing and processing the test signal to obtain the dynamic characteristic of the power semiconductor device to be tested; and/or the presence of a gas in the gas,
the power semiconductor device dynamic characteristic test system further comprises a temperature adjusting module, and the temperature adjusting module is used for adjusting the temperature of the power semiconductor device to be tested.
CN202011552324.8A 2020-12-24 2020-12-24 Dynamic characteristic test system for power semiconductor device Pending CN114675152A (en)

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Application Number Priority Date Filing Date Title
CN202011552324.8A CN114675152A (en) 2020-12-24 2020-12-24 Dynamic characteristic test system for power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011552324.8A CN114675152A (en) 2020-12-24 2020-12-24 Dynamic characteristic test system for power semiconductor device

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Publication Number Publication Date
CN114675152A true CN114675152A (en) 2022-06-28

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