CN114666998A

CN114666998A - Method for manufacturing on-board capacitor and printed circuit board

Info

Publication number: CN114666998A
Application number: CN202011535937.0A
Authority: CN
Inventors: 葛路烨; 何海力; 叶颖; 王羽
Original assignee: Hangzhou Hikvision Digital Technology Co Ltd
Current assignee: Hangzhou Hikvision Digital Technology Co Ltd
Priority date: 2020-12-23
Filing date: 2020-12-23
Publication date: 2022-06-24

Abstract

The invention provides a method for manufacturing an on-board capacitor and a printed circuit board. According to the present invention, a stacked body having a preset capacitance value may be formed in a capacitor encapsulation area of a printed circuit board by alternately printing dielectric insulation layers and electrode layers of opposite polarities stacked by being staggered with the dielectric insulation layers interposed therebetween, and the stacked body may be protected by a protective layer, whereby a capacitor may be directly grown on a finished board on the printed circuit board. On one hand, the on-board capacitor is grown on the printed circuit board without a welding process, so that welding defects such as cold joint or short circuit can be avoided; on the other hand, the capacitor is arranged on the printed circuit board growth plate, the selection and purchase of finished components of the capacitor can be omitted, and the factory cycle of the finished components of the printed circuit board can be shortened. In addition, the capacitance on the plate grown on the printed circuit board can not be limited by the capacitance value standard, and the custom manufacture of the capacitance value of the capacitor on the plate can be supported.

Description

Method for manufacturing on-board capacitor and printed circuit board

Technical Field

The present invention relates to capacitor technology, and more particularly, to a method for manufacturing an on-Board capacitor and a Printed Circuit Board (PCB).

Background

The capacitor is a component commonly used in a printed circuit board, and can be arranged in a capacitor packaging area of the printed circuit board by welding.

However, when the capacitor is soldered to the printed circuit board, soldering defects such as cold solder or short circuit of solder are likely to occur, and the reliability of connection of the capacitor to the printed circuit board is not high.

Furthermore, before the capacitor is soldered, a preparation period such as device selection and purchase of the capacitor is involved, and such a preparation period may delay a delivery period of a finished product of a Printed Circuit Board Assembly (PCBA).

Therefore, how to improve the connection reliability of the capacitor on the printed circuit board and shorten the delivery period of the finished upper circuit board becomes a technical problem to be solved in the prior art.

Disclosure of Invention

The embodiment of the invention provides a method for manufacturing an on-board capacitor and a printed circuit board with the capacitor, which are beneficial to improving the connection reliability of the capacitor on the printed circuit board and shortening the delivery cycle of a finished upper circuit board of the printed circuit board.

In one embodiment, there is provided a method of manufacturing a capacitor on board, including:

providing a bare board of a printed circuit board, wherein the bare board has a capacitive packaging area;

forming a stacked body in the capacitor encapsulation region by alternately printing electrode layers which are stacked in a staggered manner and have opposite polarities and dielectric insulating layers which are separated between adjacent electrode layers having opposite polarities, wherein the sum of capacitance values between every two adjacent electrode layers having opposite polarities in the stacked body via the dielectric insulating layers reaches a preset capacitance value;

forming a protective layer covering the stack entirely.

Alternatively, alternately printing electrode layers of opposite polarity stacked in staggered positions and dielectric insulating layers separating adjacent electrode layers of opposite polarity to form a stack in the capacitor encapsulation area, comprising: printing a first electrode layer and a second electrode layer alternately staggered with the dielectric insulating layer in the capacitor packaging area, wherein: first and second pads arranged at intervals in a first direction of the capacitor encapsulation area, at least partially outside boundaries of opposite sides of the dielectric insulating layer in the first direction, the first electrode layer having a first misalignment offset projecting out to partially overlap the first pad outside the boundaries of the dielectric insulating layer in the first direction, and the first electrode layer being electrically isolated from the second electrode layer and the second pad by the dielectric insulating layer; the second electrode layer has a second misalignment offset which protrudes out to the outside of the boundary of the dielectric insulating layer in the first direction to partially overlap the second pad, and the second electrode layer is electrically isolated from the first electrode layer and the first pad by the dielectric insulating layer; the capacitance value between each two of the electrode layers of opposite polarities adjacent to each other across the dielectric insulating layer is associated with the area of the overlapping portion of the first electrode layer and the second electrode layer across the dielectric insulating layer, the thickness of the dielectric insulating layer, and the dielectric constant of the dielectric insulating layer.

Optionally, printing a first electrode layer and a second electrode layer alternately staggered with the dielectric insulating layer in the capacitor packaging region, including: when the dielectric insulating layer is to be printed, positioning an insulating layer screen printing plate with insulating layer screen patterns, brushing fluid insulating material on the positioned insulating layer screen printing plate so that the fluid insulating material forms insulating material film layer patterns through the insulating layer screen patterns, and forming the dielectric insulating layer after curing; when the first electrode layer or the second electrode layer is to be printed, an electrode layer screen printing plate with an electrode layer screen pattern is positioned, and a fluid conductive material is coated on the positioned electrode layer screen printing plate, so that the fluid conductive material forms a conductive material film layer pattern through the electrode layer screen pattern, and the first electrode layer or the second electrode layer is formed after curing.

Optionally, forming a stacked body in the capacitor encapsulation area by alternately printing electrode layers of opposite polarities stacked in staggered relation and dielectric insulating layers separating between adjacent electrode layers of opposite polarities, further comprises: printing a base insulating layer on the capacitor-encapsulating region prior to alternately printing electrode layers of opposite polarity stacked in staggered relation and a dielectric insulating layer separating between adjacent electrode layers of opposite polarity; wherein the first pad and the second pad are at least partially outside of opposite side boundaries of the base insulating layer in the first direction; the first electrode layer and the second electrode layer partially overlap the first pad and the second pad with the insulating base layer interposed therebetween.

Optionally, printing a base insulating layer in the capacitor encapsulation area, including: and positioning an insulating layer screen printing plate with insulating layer screen mesh patterns, brushing fluid insulating materials on the positioned insulating layer screen printing plate so that the fluid insulating materials form insulating material film layer patterns through the insulating layer screen mesh patterns, and forming the base insulating layer after curing.

Optionally, printing a first electrode layer and a second electrode layer alternately staggered with the dielectric insulating layer in the capacitor packaging region, including: when the dielectric insulating layer is to be printed, positioning the dielectric insulating layer screen to the same positioning position as that of the base insulating layer, and brushing a fluid insulating material by using the positioned dielectric insulating layer screen, so that the fluid insulating material forms an insulating material film layer pattern through the dielectric insulating layer silk screen pattern, and forming the dielectric insulating layer which is aligned and overlapped with the base insulating layer after curing; when the first electrode layer or the second electrode layer is to be printed, an electrode layer screen printing plate with electrode layer screen patterns is positioned, and fluid conductive materials are coated on the positioned electrode layer screen printing plate, so that the fluid conductive materials form conductive material film layer patterns through the electrode layer screen patterns, and then the first electrode layer or the second electrode layer is formed after curing.

Optionally, forming a blanket covering the stack entirely, comprising: coating a protective paint having electrical insulation and corrosion prevention properties at least on the capacitor packaging region where the stacked body is formed to form the protective layer for blocking gas and liquid.

Alternatively, alternately printing electrode layers of opposite polarity stacked in staggered positions and dielectric insulating layers separating adjacent electrode layers of opposite polarity to form a stack in the capacitor encapsulation area, comprising: synchronously performing the alternate printing in a first capacitor packaging area and a second capacitor packaging area until a first stacked body with a preset first capacitance value is completed in the first capacitor packaging area; selectively continuing the alternate printing in the second capacitor packaging area until a second stacked body with a capacitance value increased to a preset second capacitance value is formed in the second capacitor packaging area.

In another embodiment, there is provided a printed circuit board including:

a bare board having a capacitive encapsulation area;

a stacked body formed in the capacitor encapsulation region by alternately printing electrode layers stacked with a dislocation and having opposite polarities and dielectric insulating layers separating between adjacent electrode layers having opposite polarities, wherein a sum of capacitance values between each two adjacent electrode layers having opposite polarities via the dielectric insulating layers in the stacked body reaches a preset capacitance value;

a protective layer fully covering the stack.

Optionally, the preset capacitance value is p × 10q farads, where p is an integer or a non-integer greater than 0, and q is an integer.

Based on the above-described embodiment, a stacked body having a preset capacitance value may be formed in a capacitor encapsulation area of a bare board of a printed circuit board by alternately printing dielectric insulation layers and electrode layers of opposite polarities stacked by dislocation via the dielectric insulation layers, and the stacked body may be protected by a protective layer, whereby a capacitor may be directly grown on a finished board of the printed circuit board.

On one hand, the capacitor on the board is directly grown on the printed circuit board without a welding process, so that the welding defects such as insufficient soldering or short circuit of soldering tin can be avoided, and the connection reliability of the capacitor on the printed circuit board is improved; on the other hand, the capacitors are arranged on the finished product board of the printed circuit board, so that the selection and purchase of the finished components of the capacitors can be avoided, and the factory cycle of the finished products of the upper circuit board (PCBA) can be shortened; in addition, the on-board capacitor grown on the printed circuit board can not be limited by the capacitance standard like a finished product of a capacitor element, so that the customization of the capacitance value can be supported (for example, the customization of the capacitance value of the on-board capacitor generated by manufacturing is supported), and the problems that the circuit area is increased and the capacitance value is not accurate enough due to the fact that an equivalent circuit is built by combining a plurality of standard value capacitors when a non-standard capacitance value is needed can be avoided.

Drawings

The following drawings are only schematic illustrations and explanations of the present invention, and do not limit the scope of the present invention:

FIG. 1 is an exemplary flow diagram of a method of fabricating an on-board capacitor in one embodiment;

FIGS. 2a and 2b are schematic diagrams of the minimum capacitance unit of the capacitance on a board grown on a printed circuit board using the manufacturing method shown in FIG. 1;

FIG. 3 is a schematic diagram of an example of a capacitor on a land growth plate based capacitor package area of a printed circuit board using the manufacturing method shown in FIG. 1;

FIGS. 4a to 4g are schematic top views of the capacitor on board in the example of FIG. 3;

FIG. 5 is a schematic flow chart of the manufacturing method shown in FIG. 1 suitable for the example shown in FIG. 3;

FIGS. 6a and 6b are schematic diagrams of a suitable processing sequence for the flow scheme shown in FIG. 5;

FIG. 7 is a schematic diagram of an example of an expansion of a capacitor on a plate based on a pad growth using the manufacturing method shown in FIG. 1;

FIG. 8 is a schematic top plan view of the base insulating layer further included in the on-board capacitor of the example shown in FIG. 7;

FIGS. 9a to 9g are schematic top views of the capacitor on board in the example of FIG. 7;

FIG. 10 is a schematic flow chart of an example of a manufacturing method as shown in FIG. 1, suitable for use in the method of FIG. 7;

FIGS. 11a and 11b are schematic diagrams of a suitable process for the flow of FIG. 10;

FIG. 12 is a schematic flow chart of the method of FIG. 1 for growing a plurality of on-board capacitors on the same printed circuit board;

fig. 13a and 13b are schematic diagrams of a process supporting the growth of multiple on-plate capacitors as shown in fig. 12.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and examples.

FIG. 1 is an exemplary flow diagram of a method of fabricating an on-board capacitor in one embodiment. Referring to fig. 1, in this embodiment, a method for manufacturing an on-board capacitor may include:

s100: providing a bare board of a printed circuit board, wherein the bare board is provided with a capacitor packaging area;

s110: forming a stacked body in the capacitor encapsulation region by alternately printing electrode layers which are stacked in a staggered manner and have opposite polarities and dielectric insulating layers which separate between adjacent electrode layers having opposite polarities, wherein the sum of capacitance values between every two adjacent electrode layers having opposite polarities via the dielectric insulating layers in the stacked body reaches a preset capacitance value;

s120: a blanket covering the stack is formed.

In this step, a protective paint having electrical insulation and corrosion prevention properties, such as a waterproof, dustproof, and corrosion-prevention paint, may be applied to at least the capacitor packaging region where the stacked body is formed, so as to form a gas-liquid barrier layer for preventing moisture, dust particles, corrosive substances, and the like in the environment from contacting the stacked body. For example, the protective paint covering the stacked body may be partially sprayed on the capacitor encapsulation area after the stacked body is formed by the bare board and before the bare board is mounted with other components, or the protective paint may be sprayed or dip-coated on the entire board of the printed circuit board after the stacked body is formed by the bare board and after the mounting of other components on the bare board is completed.

Of course, the manner of forming the protective layer in this step is not limited to spraying or dip coating of the protective paint, and the protective layer may be formed by laying a protective film that partially covers the stacked body or covers the entire board of the printed circuit board.

This concludes the one-time growth process for the on-board capacitors of the printed circuit board.

Based on the above-described procedure, a stacked body having a preset capacitance value may be formed in a capacitor encapsulation area of a bare board of a printed circuit board by alternately printing dielectric insulation layers and electrode layers of opposite polarities stacked in a staggered manner via the dielectric insulation layers, that is, both the dielectric insulation layers and the electrode layers may be formed through a uniform printing process, and the stacked body may be protected by a protective layer, whereby a capacitor may be directly grown on a finished board of the printed circuit board.

On one hand, the capacitor on the board is directly grown on the printed circuit board without a welding process, so that the occurrence of welding defects such as insufficient soldering or short circuit of soldering tin can be avoided, and the connection reliability of the capacitor on the printed circuit board is improved;

on the other hand, the capacitor on the finished board of the printed circuit board can avoid the model selection and purchase of the finished product of the components of the capacitor, so that the capacitor can be arranged at any time after the bare board of the printed circuit board is processed, thereby being beneficial to shortening the factory-leaving period of the finished product of the upper circuit board, for example, the layout design of the printed circuit board is not required to be modified because the design of the capacitance value is changed (the series-parallel capacitance equivalent circuit is required to be modified because of the limitation of the standard capacitance value of the finished product of the selectable capacitor components); the problem that the finished product of the capacitor component is in stock shortage or unsmooth logistics can prolong the processing period of the finished product of the upper circuit board can be avoided;

furthermore, by covering the outermost layer of the stack with a protective layer, a hermetic protective layer for the stack can be formed to avoid adverse effects in the working environment that may cause damage to the stack or a significant change in the volume, including but not limited to: the method can avoid various damages of the internal electrical structure of the stacked body caused by the corrosive air (such as salt fog and the like) entering the stacked body formed by the printing process, prevent the moisture in the environment from entering the stacked body or dust from attaching to the stacked body to cause the capacitance value of the stacked body to change obviously, and further avoid the faults or performance reduction of related circuits caused by the changes.

In addition, because the capacitance value of the stacked body obtained by the printing process is related to the number of layers of the printed electrode layer and the dielectric insulating layer, the area of the overlapped part of the first electrode layer and the second electrode layer through the dielectric insulating layer, the thickness of the dielectric insulating layer and the dielectric constant of the dielectric insulating layer, and the number of the printed layers is not limited by the process basically, the area of the overlapped part of the first electrode layer and the second electrode layer through the dielectric insulating layer, the thickness of the dielectric insulating layer and the dielectric constant of the dielectric insulating layer are all controllable, the capacitance on the board grown on the printed circuit board can not be limited by the capacitance value standard as a finished product of the capacitor component, thereby the customization of the capacitance value (for example, the customization of the capacitance value of the on-board capacitor generated by manufacturing) can be supported, and further, the increase of the circuit area caused by the combination of a plurality of standard value capacitors to build an equivalent circuit when the nonstandard capacitance value is needed to be used can be avoided, The capacitance value is not accurate enough.

Fig. 2a and 2b are schematic diagrams of a minimum capacitance unit of a capacitance on a board grown on a printed circuit board using the manufacturing method shown in fig. 1. The minimum capacitance unit is also understood to be the smallest stack, which can be the smallest capacitance unit in the stack.

Referring to fig. 2a, each two

electrode layers

210 and 220 of opposite polarities adjacent to each other with the dielectric insulating layer 200 interposed therebetween may be regarded as a minimum capacitance unit of on-board capacitance, and an equivalent capacitance value Δ C of each minimum capacitance unit may be expressed as the following expression (1):

wherein, the equivalent capacitance of the minimum capacitance unitΔ C is in units of Farad (F); s is an effective area of a minimum capacity cell, which may be an overlapping area of a pair of electrode layers of opposite polarities alternately stacked with a dielectric insulating layer interposed therebetween (the dielectric insulating layer is preferably set to expand a boundary outward from one or more directions on the basis of an overlapping portion of the pair of electrode layers of opposite polarities alternately stacked with the dielectric insulating layer interposed therebetween, and an area of the dielectric insulating layer is larger than an overlapping area of the pair of electrode layers), and may be in units of square meters (m [ (] S [ ])²) (ii) a d is a distance between a pair of electrode layers of opposite polarity alternately stacked with a dielectric insulating layer interposed therebetween, i.e., a thickness of the dielectric insulating layer sandwiched between the pair of electrode layers of opposite polarity, which may have a unit of meter (m); epsilon is the relative dielectric constant of the dielectric insulating layer in a solid state, and the unit is F/m; epsilon₀The dielectric constant in vacuum can be 8.86 × 10^-12The unit is F/m.

Assuming that the sum of the numbers of layers of electrode layers of opposite polarities is K (K is a natural number), if the numbers of layers of electrode layers of different polarities are the same (when K is an even number) or the difference in the numbers of layers between electrode layers of different polarities is 1 (when K is an odd number), and the number of layers of dielectric insulating layers is K-1, then K-1 may be formed for the electrode layers of opposite polarities alternately stacked with the dielectric insulating layers interposed therebetween, at which time the equivalent capacitance C of the stacked body may be the series value of the equivalent capacitance Δ C of K-1 minimum capacitance units, and may be expressed as expression (2) as follows:

referring to fig. 2b, in actual processing, the effective areas S _ i and S _ j of different minimum capacitance units and/or the thicknesses d _ i and d _ j of different dielectric insulating layers may be slightly different due to positioning errors, and at this time, the equivalent capacitance C of the stacked body may be more accurately expressed as the following expression (3):

alternatively, the equivalent capacitance C of the stack can also be approximately expressed as expression (4) below:

wherein S _ avg represents an average value of an overlapping area S _ K of K-1 to electrode layers of opposite polarities alternately stacked with a dielectric insulating layer interposed therebetween, and d _ avg represents an average value of d _ K of thicknesses of the K-1 dielectric insulating layers.

In whatever way the equivalent capacitance C of the stack is expressed, it can be regarded as the equivalent capacitance value Δ C being the cumulative value of the particle sizes. Therefore, the capacitance value of the on-board capacitor can be customized with the equivalent capacitance value Δ C as the granularity.

The customization described herein is relative to the IEC (international electrotechnical commission) standard value of the currently most used chip multilayer Ceramic capacitor MLCC (Multi-layer Ceramic Capacitors) in the electronics industry.

Specifically, the IEC standard capacitance value of the MLCC is expressed by the product of a fixed value C _ std of two significant digits and the power n of 10, e.g., C _ std × 10ⁿWherein C _ std is a selected value in the following set of values:

{1.0，1.1，1.2，1.3，1.5，1.6，1.8，2.0，2.2，2.4，2.7，3.0，3.3，3.6，3.9，4.3、4.7，5.1，5.6，6.2，6.8，7.5，8.2，9.1}

if there is a non-satisfaction of C _ std × 10ⁿThe non-standard capacitance value of (2), then:

a capacitor equivalent circuit needs to be built in a series, parallel or series-parallel mode of a plurality of standard value capacitors, so that the circuit design is complex, and the board layout space of a printed circuit board is occupied;

alternatively, the embedded capacitor needs to be processed on the printed circuit board, but the manufacturing process of the printed circuit board with the embedded capacitor is complicated, the cost is greatly increased, and the failure rate of the printed circuit board during use (for example, the via hole of the embedded capacitor is broken due to thermal expansion and contraction) is easily increased.

To adopt the aboveEmbodiments may not meet the C _ std × 10 requirement for off-board capacitance limitations, as the on-board capacitance may not be as limited by the capacitance criteria as the finished componentⁿThe requirement of the non-standard capacitance value of (2) can be realized without building an equivalent circuit by using an MLCC capacitor with a standard capacitance value or manufacturing an embedded capacitor when a printed circuit board is processed.

That is, the preset capacity value of the stacked body is represented as p × 10^qFarad (F), wherein p is any integer or non-integer greater than 0 and q is an integer (positive or negative).

In order to better understand the technical solutions of the above embodiments, the following detailed descriptions are made with reference to specific examples.

Fig. 3 is a schematic diagram of an example of a capacitor on a land growth plate based capacitor package area of a printed circuit board using the manufacturing method shown in fig. 1. Fig. 4a to 4g are schematic top views of the on-board capacitors in the example shown in fig. 3.

Referring to fig. 3 in conjunction with fig. 4a to 4g, in this example, a first pad 310 and a second pad 320 of opposite polarities are disposed at an interval in a first direction of the capacitor encapsulation area 300, wherein an electrode layer electrically connected to the first pad 310 and electrically isolated from the second pad 320 may be referred to as a first electrode layer 410, and an electrode layer electrically connected to the second pad 320 and electrically isolated from the first pad 310 may be referred to as a second electrode layer 420.

In this example, overlapping regions of the first electrode layers 410 and the second electrode layers 420 of opposite polarities alternately stacked with the dielectric insulating layer 400 interposed therebetween are denoted as S30, and the overlapping regions S30 may be located in the space between the first pad 310 and the second pad 320 in the first direction, i.e., opposite side boundaries of the dielectric insulating layer 400 in the first direction are respectively protruded at least a distance from opposite side boundaries of the overlapping regions S30 in the first direction. Also, at least one of the opposite side boundaries of the dielectric insulating layer 400 in the second direction intersecting (e.g., perpendicular to) the first direction is protruded from the corresponding one of the opposite side boundaries of the overlap region S30 in the second direction by a certain distance.

One end of the first electrode layer 410, which is close to the first pad 310, protrudes out of the boundary of the dielectric insulating layer 400 in the first direction to partially overlap the first pad 310, so as to realize electrical connection with the first pad 310; and, the other end of the first electrode layer 410 near the second pad 320 is indented within the boundary of the dielectric insulating layer 400 at the interval between the first pad 310 and the second pad 320 to be electrically isolated from the second electrode layer 420 and the second pad 320 by the dielectric insulating layer 400;

one end of the second electrode layer 420 close to the second pad 320 protrudes out of the boundary of the dielectric insulating layer 400 in the first direction to partially overlap the second pad 320, so as to realize electrical connection with the second pad 320; also, the other end of the second electrode layer 420 near the first pad 310 is indented within the boundary of the dielectric insulating layer 400 at the interval between the first pad 310 and the second pad 320 to be electrically isolated from the first electrode layer 410 and the first pad 310 by the dielectric insulating layer 400.

Fig. 4a to 4g illustrate a preferable manner in which the boundaries of the dielectric insulating layer 400 in the first and second directions may be located outside the boundaries of the overlap region S30 in the first and second directions, respectively, whereby the boundary of the dielectric insulating layer 400 may completely surround the overlap region S30.

In fig. 4a to 4g, the size of the overlapping area S30 in the first direction is smaller than the spacing distance between the first pad 310 and the second pad 320, in which case:

a dimension L40 of the dielectric insulation layer 400 in the first direction may be equal to a spacing distance between the first pad 310 and the second pad 320 (as indicated by a solid-line dimension line of L40 in fig. 4a to 4 g) such that the first pad 310 and the second pad 320 are all located outside a boundary of the dielectric insulation layer 400 in the first direction;

alternatively, the dimension L40 of the dielectric insulation layer 400 in the first direction may also be larger than (as indicated by the dashed arrows on both sides of the dimension line of L40 in fig. 4a to 4 g) the spacing distance between the first pad 310 and the second pad 320, and only the first pad 310 and the second pad 320 are partially covered in the first direction, so that the portions of the first pad 310 and the second pad 320 that do not overlap with the dielectric insulation layer 400 are each located outside the two boundaries of the dielectric insulation layer 400 in the first direction.

Thus, the first pads 310 and the second pads 320, which are spaced apart in the first direction of the capacitor encapsulation area 300, may be at least partially outside the boundaries of the opposite sides of the dielectric insulation layer 400 in the first direction, respectively.

In fig. 4a to 4 g:

the boundary of the overlap region S30 in the second direction may be located within the boundary of the first and

second pads

310 and 320 in the second direction as shown in fig. 4a to 4c (fig. 4b and 4c are used to indicate that the first and second electrode layers 410 and 420 may be different in size in the first and/or second direction), in which case the boundary of the dielectric insulating layer 400 in the second direction is located outside the boundary of the overlap region S30 in the second direction, and may be located inside the boundary of the first and

second pads

310 and 320 in the second direction, may extend outside the boundary of the first and

second pads

310 and 320 in the second direction as shown by the dotted arrow, and may even extend outside the boundary of the capacitive packaging region 300 in the second direction;

alternatively, the boundary of the overlapping region S30 in the second direction may be aligned with the boundary of the first pad 310 and the second pad 320 in the second direction as shown in fig. 4d and 4e (fig. 4e is used to indicate that the first electrode layer 410 and the second electrode layer 420 may have different dimensions in the first direction), in which case the boundary of the dielectric insulating layer 400 in the second direction may be outside the boundary of the first pad 310 and the second pad 320 in the second direction, or may extend outside the boundary of the capacitor packing region 300 in the second direction as shown by the dotted arrow;

alternatively, the boundary of the overlapping region S30 in the second direction may also be located between the boundary of the first pad 310 and the second pad 320 in the second direction and the boundary of the capacitor encapsulation region 300 in the second direction, as shown in fig. 4f and 4g (fig. 4g is used to indicate that the first electrode layer 410 and the second electrode layer 420 may have different dimensions in the first direction and/or the second direction), in which case the boundary of the dielectric insulation layer 400 in the second direction may be flush with the boundary of the capacitor encapsulation region 300 in the second direction, or may extend beyond the boundary of the capacitor encapsulation region 300 in the second direction, as shown by the dashed arrow.

In fig. 4a to 4g, although only the opposite ends of the first electrode layer 410 and the second electrode layer 420 are shown to be located within the boundaries of the first pad 310 and the second pad 320, respectively, in the first direction, it is understood that the opposite ends of the first electrode layer 410 and the second electrode layer 420 may also extend up to the boundaries of the capacitor encapsulation area 300 in the first direction as indicated by the dotted arrows.

In addition, in fig. 4a to 4g, the capacitor sealing area 300 is illustrated as a rectangle, in this case, the first direction of the capacitor sealing area 300 may be a length direction of the rectangle, and the second direction may be a width direction of the capacitor sealing area 300. In fig. 4a to 4e, the first and

second pads

310 and 320, the first and second electrode layers 410 and 420, and the dielectric insulating layer 400 are all rectangular, but it is understood that such a view expression is only for the convenience of intuitively defining the boundaries of different structures, and the shapes of the capacitor package region 300, the first and

second pads

310 and 320, the first and second electrode layers 410 and 420, and the dielectric insulating layer 400 should not be unnecessarily limited.

Fig. 5 is a schematic flow chart of the manufacturing method shown in fig. 1 applied to the example shown in fig. 3. Referring to fig. 5, the manufacturing method in the present embodiment may specifically include:

s500: providing a bare board of a printed circuit board, wherein the bare board is provided with a capacitor packaging area;

s510: printing, in a capacitor package area, a first electrode layer and a second electrode layer which are stacked in a staggered manner and have opposite polarities and a dielectric insulating layer which is separated between the adjacent first electrode layer and the second electrode layer having opposite polarities, wherein:

(1) the first bonding pads and the second bonding pads are arranged in the first direction of the capacitor packaging area at intervals and are respectively at least partially positioned outside the boundaries of two opposite sides of the dielectric insulating layer in the first direction;

(2) the first electrode layer has a first dislocation offset which extends out of the boundary of the dielectric insulating layer in the first direction and is partially overlapped with the first pad, and the first electrode layer is electrically isolated from the second electrode layer and the second pad by the dielectric insulating layer;

(3) the second electrode layer has a second dislocation offset which extends out of the boundary of the dielectric insulating layer in the first direction and is partially overlapped with the second pad, and the second electrode layer is electrically isolated from the first electrode layer and the first pad through the dielectric insulating layer;

(4) the capacitance value between each two electrode layers of opposite polarity adjacent to each other with the dielectric insulating layer interposed therebetween is related to the area of the overlapping portion of the first electrode layer and the second electrode layer with the dielectric insulating layer interposed therebetween, the thickness of the dielectric insulating layer, and the dielectric constant of the dielectric insulating layer.

S520: a blanket covering the stack is formed.

Fig. 6a and 6b are schematic diagrams of a suitable process for the flow shown in fig. 5.

Referring to fig. 6a, in step S510 of the process shown in fig. 5, a screen with a screen pattern may be used, that is:

s510 a: when the first electrode layer 410 is to be printed, positioning the first electrode layer screen 61 having the first electrode layer screen pattern 610, and brushing a fluid conductive material on the positioned first electrode layer screen 61, so that the fluid conductive material forms a conductive material film layer pattern (first conductive material film layer pattern) through the first electrode layer screen pattern 610, and forming the first electrode layer 410 after curing;

s510 b: when the dielectric insulating layer 400 is to be printed, positioning the insulating layer screen 60 having the insulating layer screen pattern 600, and brushing a fluid insulating material on the positioned insulating layer screen 60, so that the fluid insulating material forms an insulating material film layer pattern through the insulating layer screen pattern 600, and forming the dielectric insulating layer 400 after curing;

s510 c: when the second electrode layer 420 is to be printed, positioning the second electrode layer screen 62 having the second electrode layer screen pattern 620, and brushing the fluid conductive material on the positioned second electrode layer screen 62, so that the fluid conductive material forms a conductive material film layer pattern (second conductive material film layer pattern) through the second electrode layer screen pattern 620, and the second electrode layer 420 is formed after curing;

s510 d: when the dielectric insulating layer 400 is to be printed again, the insulating layer screen 60 having the insulating layer screen pattern 600 is positioned, and the fluid insulating material is brushed on the positioned insulating layer screen 60, so that the fluid insulating material forms an insulating material film layer pattern through the insulating layer screen pattern 600, and the dielectric insulating layer 400 is formed after the fluid insulating material is cured.

S510 e: when the first electrode layer 410 is to be printed again, the first electrode layer screen 61 having the first electrode layer screen pattern 610 is positioned, and the fluid conductive material is coated on the positioned first electrode layer screen 61, so that the fluid conductive material forms a conductive material film layer pattern (first conductive material film layer pattern) through the first electrode layer screen pattern 610, and the first electrode layer 410 is formed after curing.

After performing S510a once:

the complete cycle of S510b to S510e may be performed several more times and then S520 may be performed to form the overcoat layer 430 covering the stack completely;

alternatively, after several complete cycles of S510b to S510e, a half cycle of S510b to S510c may be performed, and then the overcoat layer 430 fully covering the stack may be formed by performing S520.

Referring to fig. 6b, if the first electrode layer 410 and the second electrode layer 420 have the same shape and size, the first electrode layer 410 and the second electrode layer 420 may be printed using the same screen, that is, S510 in the flow shown in fig. 5 may include:

s510 a': when the first electrode layer 410 is to be printed, the electrode layer screen 63 with the reusable electrode layer screen pattern 630 is positioned, and a fluid conductive material is coated on the reusable electrode layer screen 63 which is positioned, so that the fluid conductive material forms a conductive material film layer pattern (first conductive material film layer pattern) through the reusable electrode layer screen pattern 630, and the first electrode layer 410 is formed after curing;

s510 c': when the second electrode layer 420 is to be printed, the reusable electrode layer screen 63 with the reusable electrode layer screen pattern 630 is positioned at a position different from the position where the first electrode layer 410 is printed, and the positioned reusable electrode layer screen 63 is coated with a fluid conductive material, so that the fluid conductive material forms a conductive material film layer pattern (second conductive material film layer pattern) through the reusable electrode layer screen pattern 630, and the second electrode layer 420 is formed after curing;

s510 d: when the dielectric insulating layer 400 is to be printed again, the insulating layer screen 60 having the insulating layer screen pattern 600 is positioned, and the fluid insulating material is brushed on the positioned insulating layer screen 60, so that the fluid insulating material passes through the insulating layer screen pattern 600 to form an insulating material film layer pattern, and the dielectric insulating layer 400 is formed after curing.

S510 e': when the first electrode layer 410 is to be printed again, the reusable electrode layer screen 63 having the reusable electrode layer screen pattern 630 is positioned at the same printing positioning position as in step S510 a', and the fluid conductive material is coated on the positioned reusable electrode layer screen 63, so that the fluid conductive material forms a conductive material film layer pattern (first conductive material film layer pattern) through the reusable electrode layer screen pattern 630, and the first electrode layer 410 is formed after curing.

After performing S510 a' once:

s520 forming the overcoat layer 430 to cover the stack entirely may be performed after performing several complete cycles of S510b 'to S510 e';

alternatively, after several complete cycles of S510b 'to S510 e', a half cycle of S510b 'to S510 c' may be performed, and then S520 may be performed to form the overcoat layer 430 that covers the stack completely.

In the process flow shown in fig. 6a or fig. 6b, the fluid insulating material may be an insulating ink, and the fluid conductive material may be a conductive ink.

If the thickness of the dielectric insulating layer 400 formed by curing the insulating ink is too small, holes are easily formed in the dielectric insulating layer 400, and short-circuit contact or insufficient voltage resistance occurs between the two adjacent first electrode layer 410 and second electrode layer 420 above and below the dielectric insulating layer 400; if the thickness of the dielectric insulating layer 400 formed by curing the insulating ink is too large, the distance d between the two adjacent first electrode layer 410 and second electrode layer 420 above and below the dielectric insulating layer is easily made too large, resulting in a decrease in the capacitance value of the minimum capacitance unit, thereby resulting in a stacked body having too many stacked numbers of minimum capacitance units when a preset capacitance value is satisfied, too high overall height, or having a true capacitance value that is slightly smaller than the preset capacitance value when a desired stacked height is satisfied. Similarly, the thickness of the first electrode layer 410 and the second electrode layer 420 formed by curing the conductive ink should not be too large or too small.

The ink thickness can be controlled to achieve the desired thickness of the dielectric insulating layer 400, the first electrode layer 410, and the second electrode layer 420 by controlling the following parameters: the content of the thinner of the printing ink, the hole density (mesh number) of the silk screen, the running speed of the printing scraper, the distance between the insulating layer screen and the electrode layer screen relative to the surface to be brushed, and the like.

After the brush coating, the curing of the formed insulating material film layer pattern and the formed conductive material film layer pattern can be realized through a baking process or an ultraviolet irradiation process.

The baking process for curing the insulating material film layer patterns and the conducting material film layer patterns can last for a preset baking time (for example, 10-30 minutes) and a preset baking temperature (for example, 150 +/-10 ℃); and the ultraviolet irradiation process is used for curing the film layer patterns of each layer of the insulating material and the film layer patterns of the conducting material, and the continuous preset irradiation time can be set according to the irradiation intensity.

In addition, in the case that the fluid conductive material is silver paste ink, it is preferable to use a baking process to achieve curing due to poor light transmittance of the metallic silver powder.

Fig. 7 is a schematic diagram of an example of an expansion of the capacitance on the plate based on the pad growth using the manufacturing method shown in fig. 1. Fig. 8 is a schematic top view of the base insulating layer further included in the on-board capacitor in the example shown in fig. 7. Fig. 9a to 9g are schematic top views of the on-board capacitors in the example shown in fig. 7. Referring to fig. 7 in conjunction with fig. 8 and fig. 9a to 9g, in this extended example, in the first direction of the capacitor encapsulation area 300, the first pad 310 and the second pad 320 having opposite polarities are still arranged at an interval like the example shown in fig. 3, and the electrode layer electrically connected to the first pad 310 and electrically isolated from the second pad 320 may be referred to as a first electrode layer 710, and the electrode layer electrically connected to the second pad 320 and electrically isolated from the first pad 310 may be referred to as a second electrode layer 720.

However, unlike the example shown in fig. 3, in the expanded example shown in fig. 7, the overlapping region S70 of the first electrode layer 710 and the second electrode layer 720 of opposite polarities alternately stacked via the dielectric insulating layer 400 crosses the interval between the first pad 310 and the second pad 320 in the first direction and forms a partial overlap with each of the first pad 310 and the second pad 320.

With particular attention to fig. 8, in order to avoid the conductive contact between the first electrode layer 710 of the lowest layer of the stacked body and the second pad 320 of opposite polarity, in the expanded example shown in fig. 7, the base insulating layer 800 needs to be additionally printed on the capacitor packaging region 300 before the capacitor packaging region 300 is printed with the first electrode layer 710 and the second electrode layer 720 alternately offset with the dielectric insulating layer 700 interposed therebetween. The first electrode layer 710 and the second electrode layer 720 of the subsequent printing partially overlap the first pad 310 and the second pad 320 via the insulating base layer 800 via the overlapping portion S70 of the insulating dielectric layer 700.

The base insulating layer 800 may form partial coverage of the first and

second pads

310 and 320 in the first direction, and the base insulating layer 800 may form partial coverage or full coverage of the first and

second pads

310 and 320 in the second direction. Scalability of coverage of the base insulating layer 800 is indicated by dashed arrows in fig. 8.

In actual design, the shape and size of the base insulating layer 800 may be the same as the shape and size of the dielectric insulating layer 700, or may be different from the shape and size of the dielectric insulating layer 700. For convenience of description and illustration, in this extended example, it is exemplified that the shape and size of the base insulating layer 800 may be the same as those of the dielectric insulating layer 700.

In this case, the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction is at least flush with the boundary of the overlap region S70 in the first direction, or preferably, the opposite side boundaries of the base insulating layer 800 in the first direction may be expanded to extend at least beyond the corresponding side boundaries of the overlap region S70 in the first direction. Also, the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the second direction intersecting (e.g., perpendicular to) the first direction may be at least flush with the boundary of the overlap region S70 in the second direction, or preferably, at least one side boundary of the opposite side boundaries of the base insulating layer 800 in the second direction may be expanded to extend beyond the corresponding side boundary of the overlap region S70 in the second direction.

One end of the first electrode layer 710 close to the first pad 310 protrudes out of the boundary of the insulating base layer 800 and the insulating dielectric layer 700 in the first direction to partially overlap the first pad 310, so as to achieve electrical connection with the first pad 310; and, the other end of the first electrode layer 710 near the second pad 320 is retracted within the boundary of the base insulating layer 800 and the dielectric insulating layer 700 above the second pad 320 to be electrically isolated from the second electrode layer 720 and the second pad 320 by at least one of the base insulating layer 800 and the dielectric insulating layer 700;

one end of the second electrode layer 720 close to the second pad 320 protrudes out to the outside of the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction to partially overlap the second pad 320, so as to realize electrical connection with the second pad 320; also, the other end of the second electrode layer 720 near the first pad 310 is retracted above the first pad 310 within the boundary of the base insulating layer 800 and the dielectric insulating layer 700 to be electrically isolated from the first electrode layer 710 and the first pad 310 by at least one of the base insulating layer 800 and the dielectric insulating layer 700.

The planarization process of the capacitor encapsulation area 300 of the bare board of the printed circuit board can be realized by further printing the base insulating layer 800, for example, there may be a recessed gap (similar to a "trench") with a width of about 0.1mm between the boundary of the solder resist layer (commonly called "green oil") of the capacitor encapsulation area 300 and the boundary of the copper foil layer on the surface of the first pad 310 and the second pad 320, and the printed base insulating layer 800 can make the surface unevenness caused by the recessed gap tend to be planarized, which is helpful for the planarization of the stacked body.

Fig. 9a to 9g illustrate a preferable manner in which the boundaries of the base insulating layer 800 and the dielectric insulating layer 700 in the first and second directions may be located outside the boundaries of the overlap region S70 in the first and second directions, respectively, whereby the boundaries of the base insulating layer 800 and the dielectric insulating layer 700 may completely surround the overlap region S70.

In fig. 9a to 9g, a dimension of the overlapping region S70 in the first direction is greater than (may also be equal to) a spacing distance between the first pad 310 and the second pad 320, in which case a dimension L70 of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction may be greater than (as indicated by a solid dimension line of L70 in fig. 9a to 9 g) the spacing distance between the first pad 310 and the second pad 320, so that the first pad 310 and the second pad 320 are located only partially outside a boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction.

The dimension L70 of the base insulating layer 800 and the dielectric insulating layer 700 in the first direction may be adjusted according to actual needs, that is, as indicated by the dashed arrows on both sides of the dimension line of L70 in fig. 9a to 9g, as long as it is satisfied that the base insulating layer 800 and the dielectric insulating layer 700 form only partial coverage of the first pad 310 and the second pad 320 in the first direction.

In fig. 9a to 9 g:

the boundary of the overlap region S70 in the second direction may be located inside the boundary of the first and

second pads

310 and 320 in the second direction as shown in fig. 9a to 9c (fig. 9b and 9c are used to indicate that the sizes of the first and second electrode layers 710 and 720 in the first and/or second directions may be different), in which case the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the second direction is located outside the boundary of the overlap region S70 in the second direction, and may be located inside the boundary of the first and

second pads

310 and 320 in the second direction as shown by the dotted arrow, and may even extend outside the boundary of the capacitor package region 300 in the second direction;

alternatively, the boundary of the overlapping region S70 in the second direction may be aligned with the boundaries of the first and

second pads

310 and 320 in the second direction as shown in fig. 9d and 9e (fig. 9e is used to indicate that the first and second electrode layers 710 and 720 may have different dimensions in the first direction), in which case the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the second direction may be outside the boundary of the first and

second pads

310 and 320 in the second direction, or may extend outside the boundary of the capacitor packing region 300 in the second direction as shown by the dotted arrow;

alternatively, the boundary of the overlapping region S70 in the second direction may also be located between the boundary of the first and

second pads

310 and 320 in the second direction and the boundary of the capacitor packaging region 300 in the second direction as shown in fig. 9f and 9g (fig. 9g is used to indicate that the first and second electrode layers 710 and 720 may have different dimensions in the first and/or second directions), in which case the boundary of the base insulating layer 800 and the dielectric insulating layer 700 in the second direction may be flush with the boundary of the capacitor packaging region 300 in the second direction or may extend beyond the boundary of the capacitor packaging region 300 in the second direction as shown by the dotted arrow.

In fig. 9a to 9g, although only the opposite ends of the first and second electrode layers 710 and 720 are shown to be located within the boundaries of the first and

second pads

310 and 320, respectively, in the first direction, it is understood that the opposite ends of the first and second electrode layers 710 and 720 may also extend up to the boundaries of the capacitor encapsulation area 300 in the first direction as indicated by the dotted arrows.

In addition, the rectangular representations used in fig. 9a to 9g, like fig. 4a to 4g, should not unnecessarily limit the shapes of the capacitor packaging area 300, the first and

second pads

310 and 320, the first and second electrode layers 710 and 720, and the base insulating layer 800 and the dielectric insulating layer 700.

It is understood that the example shown in fig. 3 does not exclude the layout of the insulating base layer 800, and if the insulating base layer is applied to the example shown in fig. 3, the first pads 310 and the second pads 320 spaced apart in the first direction of the capacitor encapsulation area 300 may be at least partially located outside the boundary between the insulating base layer 800 and the dielectric insulating layer 400 in the first direction.

Fig. 10 is a schematic flow diagram of the manufacturing method shown in fig. 1, applied to the example shown in fig. 7. Referring to fig. 10, the manufacturing method in the present embodiment may specifically include:

s1000: providing a bare board of a printed circuit board, wherein the bare board is provided with a capacitance packaging area;

s1011: printing a base insulating layer in the capacitor packaging area, wherein the first bonding pad and the second bonding pad are respectively at least partially positioned outside the boundaries of two opposite sides of the base insulating layer in the first direction;

s1012: printing a first electrode layer and a second electrode layer which are stacked in a staggered manner and have opposite polarities and a dielectric insulating layer which separates adjacent first electrode layers and second electrode layers having opposite polarities in a capacitor packaging region where a base insulating layer is formed,

wherein:

(2) the first electrode layer has a first dislocation offset which protrudes out of the boundary of the base insulating layer and the dielectric insulating layer on the first direction and partially overlaps the first pad, and the first electrode layer is electrically isolated from the second electrode layer and the second pad by the base insulating layer and the dielectric insulating layer;

(3) the second electrode layer has a second dislocation offset which is partially overlapped with the second pad outside the boundary of the base insulating layer and the dielectric insulating layer on the first direction, and is electrically isolated from the first electrode layer and the first pad by the base insulating layer and the dielectric insulating layer;

(4) the first electrode layer and the second electrode layer are partially overlapped with the first pad and the second pad through the base insulating layer and the overlapping part of the dielectric insulating layer;

(5) the capacitance value between each two electrode layers of opposite polarity adjacent to each other with the dielectric insulating layer interposed therebetween is related to the area of the overlapping portion of the first electrode layer and the second electrode layer with the dielectric insulating layer interposed therebetween, the thickness of the dielectric insulating layer, and the dielectric constant of the dielectric insulating layer.

S1020: a blanket covering the stack is formed.

To this end, one growth process for the on-board capacitors of the printed circuit board is completed.

Fig. 11a and 11b are schematic diagrams of a suitable process for the flow shown in fig. 10.

Referring to fig. 11a, in the process shown in fig. 10, S1011 and S1012 can both use a screen with a screen pattern, that is:

s1011: positioning the insulating layer screen 110 having the insulating layer screen pattern 1100, and brushing a fluid insulating material on the positioned insulating layer screen 110, so that the fluid insulating material passes through the insulating layer screen pattern 1100 to form an insulating material film layer pattern, and curing to form the base insulating layer 800;

then after performing one S1012a and several complete cycles of S1012b to S1012e, or one S1012a, several complete cycles of S1012b to S1012e, and one half cycle of S1012b to S1012c, S1120 may be performed to form the overcoat 730 which covers the stack completely.

S1012 a-S1012 e in fig. 11a may be substantially the same as S510a and S510e as shown in fig. 6a, specifically as follows:

s1012 a: when the first electrode layer 710 is to be printed, positioning the first electrode layer screen 111 having the first electrode layer screen pattern 1110, and brushing a fluid conductive material on the positioned first electrode layer screen 111, so that the fluid conductive material forms a conductive material film layer pattern (first conductive material film layer pattern) through the first electrode layer screen pattern 1110, and forms the first electrode layer 710 partially overlapping with the base insulating layer 800 after being cured;

s1012 b: when the dielectric insulating layer 700 is to be printed, the insulating layer screen 110 for printing the base insulating layer 800 may be reused to position the insulating layer screen 110 to the same position as for printing the base insulating layer 800, and the fluid insulating material is applied to the positioned insulating layer screen 110, such that the fluid insulating material forms an insulating material film pattern through the insulating layer screen pattern 1100, and after curing, the dielectric insulating layer 700 is formed that substantially completely overlaps the base insulating layer 800;

s1012 c: when the second electrode layer 720 is to be printed, positioning the second electrode layer screen 112 having the second electrode layer screen pattern 1120, and brushing a fluid conductive material on the positioned second electrode layer screen 112, so that the fluid conductive material forms a conductive material film pattern (second conductive material film pattern) through the second electrode layer screen pattern 1120, and forming the second electrode layer 720 after curing;

s1012 d: when the dielectric insulating layer 700 is to be printed again, the insulating layer screen 110 is also positioned to the same positioning position as the base insulating layer 800, and a fluid insulating material is applied to the positioned insulating layer screen 110 such that the fluid insulating material forms an insulating material film pattern through the insulating layer screen pattern 1100, and upon curing, forms the dielectric insulating layer 700 that substantially completely overlaps the base insulating layer 800.

S1012 e: when the first electrode layer 710 is to be printed again, the electrode layer screen 111 having the first electrode layer screen pattern 1110 is positioned at the same printing positioning position as that in step S1012a, and the fluid conductive material is applied to the positioned electrode layer screen 111, so that the fluid conductive material forms a conductive material film layer pattern (first conductive material film layer pattern) through the first electrode layer screen pattern 1110, and the first electrode layer 710 is formed after curing.

Referring to fig. 11b, similarly to fig. 6b, if the first electrode layer 710 and the second electrode layer 720 have the same shape and size, the reusable electrode layer screen 113 having the reusable electrode layer screen pattern 1130 may be used for printing the first electrode layer 710 and the second electrode layer 720. Also, after performing one complete cycle of S1012a 'and several times of S1012 b' to S1012e ', or performing one complete cycle of S1012 a', several complete cycles of S1012b 'to S1012 e', and one half cycle of S1012b 'to S1012 c', S1120 may be performed to form the overcoat layer 730 fully covering the stack.

In the process flow shown in fig. 11a or fig. 11b, the fluid insulating material may be an insulating ink, and the fluid conductive material may be a conductive ink. Furthermore, by adjusting the diluent content of the ink, the hole density (mesh number) of the screen, the running speed of the printing squeegee, the distance between the insulating layer screen or the electrode layer screen and the surface to be brushed, and other parameters, the thickness of the ink layer printed on the printed circuit board can be controlled, so that the base insulating layer 800, the dielectric insulating layer 700, the first electrode layer 710 and the second electrode layer 720 reach the desired thickness. After the coating is brushed, the formed insulating material film layer patterns and the formed conducting material film layer patterns are cured through a baking process or an ultraviolet irradiation process.

The above is a description of growing capacitors on a single board of a printed circuit board, and in practical application, when the manufacturing method in the embodiment is implemented to grow capacitors on a printed circuit board, capacitors on multiple boards may also be grown on one printed circuit board simultaneously through a printing process.

If the number of stacked capacitors on a plurality of boards to be grown simultaneously on the same bare board of the printed circuit board is equal, silk screen patterns for the capacitors on each board can be manufactured at different positions of the same insulating layer screen and the same electrode layer screen, and then the silk screen patterns are synchronously printed and grown by utilizing the process.

If the number of stacked layers of capacitors on a plurality of boards to be grown simultaneously on a bare board of the same printed circuit board is not all the same, then a plurality of sets of insulating layer screens and electrode layer screens can be prepared according to the number of stacked layers, wherein:

for the first set of the insulating layer screen and the electrode layer screen, different positions of the same insulating layer screen and the same electrode layer screen can be provided with screen patterns aiming at the capacitor on each plate;

for the second set of the insulating layer screen and the electrode layer screen, different positions of the same insulating layer screen and the same electrode layer screen may have screen patterns of the capacitors on the remaining plates except the capacitor on the plate having the smallest number of stacked layers;

for the third set of the insulating layer screen and the electrode layer screen, different positions of the same insulating layer screen and the same electrode layer screen may have screen patterns of the capacitors on the remaining plates other than the capacitors on the two plates having the smallest and next smallest number of stacked layers;

by analogy, in the direction that piles up the increase in the number of piles, every insulating layer half tone and electrode layer half tone compare in preceding set of insulating layer half tone and electrode layer half tone, reduce the silk screen pattern that has the board electric capacity that the one-level was piled up the number of piles on, until last set of insulating layer half tone and electrode layer half tone, same insulating layer half tone and same electrode layer half tone can only have the silk screen pattern of the board electric capacity that piles up the number of piles the most.

Fig. 12 is a schematic flow chart of the method of fig. 1 for growing a plurality of on-board capacitors on the same printed circuit board. Referring to fig. 12, when the manufacturing method shown in fig. 1 is used for growing a plurality of on-board capacitors, for every two adjacent on-board capacitors, the manufacturing method may include the following steps (assuming that the capacitance value generated in the first package region is required to be the first capacitance value and to have the first number of stacked layers, and the capacitance value generated in the second package region is required to be the second capacitance value and to have the second number of stacked layers, and the second number of stacked layers is greater than the first number of stacked layers):

s1200: selectively printing a base insulating layer on the first capacitor packaging area and the second capacitor packaging area;

s1210: and synchronously alternately printing electrode layers with opposite polarities and dielectric insulating layers separating the adjacent electrode layers with the opposite polarities, which are adjacent to each other through the dielectric insulating layers and stacked in a staggered mode, on the first capacitor packaging area and the second capacitor packaging area until the number of stacked layers of the first capacitor packaging area and the second capacitor packaging area reaches the first stacked layer number, and forming a first stacked body with a preset first capacitance value in the first capacitor packaging area.

S1220: and selectively alternately printing dielectric insulating layers separated between the adjacent electrode layers with opposite polarities and the electrode layers with opposite polarities which are adjacent and staggered and stacked through the dielectric insulating layers in the second capacitor packaging area until the number of stacked layers of the second capacitor packaging area is increased from the first stacked layer number to the second stacked layer number, and forming a second stacked body with a preset second capacitance value in the second capacitor packaging area.

If the overlapping area of the pair of electrode layers of opposite polarity alternately stacked with the dielectric insulating layer interposed therebetween in the first stack is the same as the overlapping area of the pair of electrode layers of opposite polarity alternately stacked with the dielectric insulating layer interposed therebetween in the second stack, after S1210, the capacitance values of the first stack and the second stack having the first number of stacked layers may each be a first capacitance value; after S1220, the capacitance value of the second stack may increase from the first capacitance value to the second capacitance value after passing S1220, i.e., the second capacitance value may be greater than the first capacitance value.

If the overlapping area of the pair of electrode layers of opposite polarity alternately stacked with the dielectric insulating layer interposed therebetween in the first stack is different from the overlapping area of the pair of electrode layers of opposite polarity alternately stacked with the dielectric insulating layer interposed therebetween in the second stack, after S1210, the capacitance value of the first stack having the first number of stacked layers may be a first capacitance value, and the capacitance value of the second stack may be different from the first capacitance value and may not reach a second capacitance value; after S1220, the capacitance value of the second stack may increase to a second capacitance value after passing S1220, and the second capacitance value may be less than or equal to or greater than the first capacitance value.

S1200 in the above flow is an optional step.

Fig. 13a and 13b are schematic diagrams of a process supporting the growth of multiple on-plate capacitors as shown in fig. 12. In fig. 13a and 13b, it is assumed that the printed circuit board needs to grow an on-board capacitance in a first capacitance package region having a pair of

pads

1311 and 1312 and a second capacitance package region having another pair of

pads

1321 and 1322, wherein the preset capacitance value of the on-board capacitance in the first capacitance package region is C1 (the stacked body of the on-board capacitance in the first capacitance package region has a first stacked layer number), and the preset capacitance value of the on-board capacitance in the second capacitance package region is C2 (the stacked body of the on-board capacitance in the second capacitance package region has a second stacked layer number greater than the first stacked layer number).

A set of insulating layer screen 1910 and

electrode layer screens

1911 and 1912, denoted as an α screen set, are provided, wherein the insulating layer screen 1910 has an insulating layer screen pattern 1910a for forming the base insulating layer 1500 and the dielectric insulating layer 1400 in the first capacitor packaging region and an insulating layer screen pattern 1910b for forming the base insulating layer 1800 and the dielectric insulating layer 1700 in the second capacitor packaging region, the electrode layer screen 1911 has an electrode layer screen pattern 1911a for forming the first electrode layer 1410 in the first capacitor packaging region and an electrode layer screen pattern 1911b for forming the first electrode layer 1710 in the second capacitor packaging region, and the electrode layer screen 1912 has an electrode layer screen pattern 1912a for forming the second electrode layer 1420 in the second capacitor packaging region and a screen electrode layer pattern 1912b for forming the second electrode layer 1720 in the second capacitor packaging region.

Further, another set of insulating layer screen 1920 and

electrode layer screens

1921 and 1922, which are referred to as a β screen set, is provided, in which the insulating layer screen 1920 has only the insulating layer screen pattern 1920b for forming the dielectric insulating layer 1700 in the second capacitor sealing region, the electrode layer screen 1921 has only the electrode layer screen pattern 1921b for forming the first electrode layer 1710 in the second capacitor sealing region, and the electrode layer screen 1912 has only the electrode layer screen pattern 1922b for forming the second electrode layer 1720 in the second capacitor sealing region.

Thus, according to the flow shown in fig. 12:

firstly, synchronously printing

base insulating layers

1500 and 1800 in a first capacitor packaging area and a second capacitor packaging area by using an insulating layer screen 1910 in an alpha screen group;

then, using the insulating layer screen 1910 and the

electrode layer screens

1911 and 1912 in the α screen set, alternately printing the dielectric insulating layer 1400 and the first electrode layer 1410 and the second electrode layer 1420 stacked alternately with the dielectric insulating layer 1400 interposed therebetween, and alternately printing the dielectric insulating layer 1700 and the first electrode layer 1710 and the second electrode layer 1720 stacked alternately with the dielectric insulating layer 1700 interposed therebetween in the second capacitance encapsulation region, simultaneously until the number of stacked layers in the first capacitance encapsulation region reaches a first stacked layer number, and the number of stacked layers in the second capacitance encapsulation region also reaches the first stacked layer number, at which time, the sum of capacitance values between each two first electrode layers 1410 and second electrode layers 1420 of opposite polarities adjacent with the dielectric insulating layer 1400 interposed therebetween in the first capacitance encapsulation region reaches a preset first capacitance value C1, but electrical capacitance values between each two first electrode layers 1710 and second electrode layers 1720 of opposite polarities adjacent with the dielectric insulating layer 1700 interposed therebetween in the second capacitance encapsulation region are alternately printed alternately The sum of the capacitance values does not reach a preset second capacitance value C2;

thereafter, the dielectric insulating layers 1700 and each two of the first electrode layers 1710 and the second electrode layers 1720 adjacent to each other with the dielectric insulating layers 1700 interposed therebetween are alternately printed in the second capacitor packaging region by using the insulating layer screens 1920 and the

electrode layer screens

1921 and 1922 in the β screen group until the number of stacked layers of the dielectric insulating layers 1700 and the first electrode layers 1710 and the second electrode layers 1720 stacked in the second capacitor packaging region increases from the first number of stacked layers to the second number of stacked layers, at which time, the sum of capacitance values between each two of the first electrode layers 1710 and the second electrode layers 1720 of opposite polarities adjacent to each other with the dielectric insulating layers 1700 interposed therebetween increases to a preset second capacitance value C2.

In fig. 13a, the insulating base layer 1500 is not necessarily formed in the first capacitor sealing region including the

pads

1311 and 1312, but the insulating base layer 1500 is formed in the first capacitor sealing region so as to improve insulation reliability without increasing the number of screen plates for insulating layers.

Referring to fig. 13b, if the base insulating layer 1500 is not formed in the first capacitor encapsulation area, the insulating layer 1920 in the β halftone set may be used to selectively print the base insulating layer 1800 in the second capacitor encapsulation area, and then as shown in S1210 and S1220 in the flow shown in fig. 12, the α set and the β set are used to complete the subsequent printing.

The first capacitor encapsulation area and the second capacitor encapsulation area shown in fig. 13a and 13b may be multiple in different positions of the bare board of the same printed circuit board, that is, as long as the stacked body of the capacitors on the board of the printed circuit board has only two stacked layer number designs, only two screen plate sets may be provided regardless of the number of the capacitor encapsulation areas. If the stacked body of the on-board capacitors of the printed circuit board has more than two stacked layers, the number of the screen sets may be increased in the manner described above.

In another embodiment, there is also provided a printed circuit board including:

a bare board with capacitive encapsulation area(s);

a stack(s) (as shown in fig. 3 and 4a to 4e, or fig. 7 and 9a to 9 e) formed in the capacitor encapsulation region by alternately printing electrode layers which are alternately stacked and have opposite polarities and dielectric insulating layers which separate between adjacent electrode layers having opposite polarities, wherein a sum of capacitance values between each two electrode layers having opposite polarities adjacent to each other through the dielectric insulating layers in the stack reaches a preset capacitance value, and when there is more than one stack, the number of stacked layers may not be completely the same for each stack, or the preset capacitance values reached by the sum of capacitance values between each two electrode layers having opposite polarities adjacent to each other through the dielectric insulating layers may not be completely the same;

a protective layer (e.g. a protective lacquer or film as described above) covering the stack in its entirety.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A method of fabricating a capacitor on a board, comprising:

providing a bare board of a printed circuit board, wherein the bare board has a capacitance packaging area;

forming a protective layer covering the stack entirely.

2. The method of manufacturing of claim 1, wherein alternately printing electrode layers of opposite polarity stacked in staggered positions and dielectric insulating layers separating adjacent electrode layers of opposite polarity forms a stack in the capacitor encapsulation area, comprising:

printing a first electrode layer and a second electrode layer alternately staggered with the dielectric insulating layer in the capacitor packaging area, wherein:

first pads and second pads arranged at intervals in a first direction of the capacitor packaging area are at least partially positioned outside boundaries of two opposite sides of the dielectric insulating layer in the first direction,

the first electrode layer has a first misalignment offset protruding to partially overlap the first pad outside a boundary of the dielectric insulating layer in the first direction, and the first electrode layer is electrically isolated from the second electrode layer and the second pad by the dielectric insulating layer;

the second electrode layer has a second misalignment offset protruding to a position outside a boundary of the dielectric insulating layer in the first direction to partially overlap the second pad, and the second electrode layer is electrically isolated from the first electrode layer and the first pad by the dielectric insulating layer;

a capacitance value between each two of the electrode layers of opposite polarities adjacent via the dielectric insulating layer is associated with an area of an overlapping portion of the first electrode layer and the second electrode layer via the dielectric insulating layer, and a thickness of the dielectric insulating layer and a dielectric constant of the dielectric insulating layer.

3. The manufacturing method according to claim 2, wherein printing a first electrode layer and a second electrode layer alternately offset with the dielectric insulating layer in between in the capacitor packaging region comprises:

when the dielectric insulating layer is to be printed, positioning an insulating layer screen printing plate with insulating layer screen patterns, brushing fluid insulating material on the positioned insulating layer screen printing plate so that the fluid insulating material forms insulating material film layer patterns through the insulating layer screen patterns, and forming the dielectric insulating layer after curing;

when the first electrode layer or the second electrode layer is to be printed, an electrode layer screen printing plate with an electrode layer screen pattern is positioned, and a fluid conductive material is coated on the positioned electrode layer screen printing plate, so that the fluid conductive material forms a conductive material film layer pattern through the electrode layer screen pattern, and the first electrode layer or the second electrode layer is formed after curing.

4. A method of manufacturing according to claim 2, wherein a stack is formed in the capacitor encapsulation area by alternately printing electrode layers of staggered stacks and opposite polarity and dielectric insulating layers separating between adjacent electrode layers of opposite polarity, further comprising:

printing a base insulating layer on the capacitor package region prior to alternately printing electrode layers of opposite polarity stacked in staggered relation and a dielectric insulating layer separating adjacent electrode layers of opposite polarity;

wherein the first pad and the second pad are at least partially outside of opposite side boundaries of the base insulating layer in the first direction;

the first electrode layer and the second electrode layer partially overlap the first pad and the second pad with the insulating base layer interposed therebetween.

5. The manufacturing method according to claim 4, wherein printing a base insulating layer in the capacitor encapsulation area comprises:

and positioning an insulating layer screen printing plate with insulating layer screen mesh patterns, brushing fluid insulating materials on the positioned insulating layer screen printing plate so that the fluid insulating materials form insulating material film layer patterns through the insulating layer screen mesh patterns, and forming the base insulating layer after curing.

6. The manufacturing method according to claim 5, wherein printing a first electrode layer and a second electrode layer alternately offset with the dielectric insulating layer in between in the capacitor packaging region comprises:

when the dielectric insulating layer is to be printed, positioning the dielectric insulating layer screen to the same positioning position as that of the base insulating layer, and brushing a fluid insulating material by using the positioned dielectric insulating layer screen, so that the fluid insulating material forms an insulating material film layer pattern through the dielectric insulating layer silk screen pattern, and forming the dielectric insulating layer which is aligned and overlapped with the base insulating layer after curing;

when the first electrode layer or the second electrode layer is to be printed, an electrode layer screen printing plate with an electrode layer screen pattern is positioned, and a fluid conductive material is coated on the positioned electrode layer screen printing plate, so that the fluid conductive material passes through the electrode layer screen pattern to form a conductive material film layer pattern, and then the first electrode layer or the second electrode layer is formed after curing.

7. The manufacturing method according to claim 1, wherein forming the overcoat layer to entirely cover the stack includes:

coating a protective paint having electrical insulation and corrosion prevention properties at least on the capacitor packaging region where the stacked body is formed to form the protective layer for blocking gas and liquid.

8. A method of manufacturing according to any of claims 1 to 7, wherein alternately printing electrode layers of opposite polarity stacked in staggered positions and dielectric insulating layers separating adjacent electrode layers of opposite polarity, forming a stack in the capacitor encapsulation area, comprises:

synchronously performing the alternate printing in a first capacitor packaging area and a second capacitor packaging area until a first stacked body with a preset first capacitance value is completed in the first capacitor packaging area;

selectively continuing the alternate printing in the second capacitor packaging area until a second stacked body with a capacitance value increased to a preset second capacitance value is formed in the second capacitor packaging area.

9. A printed circuit board, comprising:

a bare board having a capacitive encapsulation area;

a stacked body formed in the capacitor encapsulation region by alternately printing electrode layers of opposite polarities which are alternately stacked with a shift and a dielectric insulating layer separating between adjacent electrode layers of opposite polarities, wherein a sum of capacitance values between each two of the electrode layers of opposite polarities adjacent to each other with the dielectric insulating layer interposed therebetween reaches a preset capacitance value;

a protective layer fully covering the stack.

10. The printed circuit board of claim 9, wherein the predetermined capacitance value is p x 10^qFarad, wherein p is an integer or non-integer greater than 0 and q is an integer.