CN114665879A

CN114665879A - Current-frequency conversion circuit and working method thereof

Info

Publication number: CN114665879A
Application number: CN202210388863.5A
Authority: CN
Inventors: 贺林; 陈昕; 郭宇锋; 蔡志匡
Original assignee: Nanjing University of Posts and Telecommunications
Current assignee: Nanjing University of Posts and Telecommunications
Priority date: 2022-04-14
Filing date: 2022-04-14
Publication date: 2022-06-24

Abstract

The invention discloses a current-frequency conversion circuit and a working method thereof, wherein the current-frequency conversion circuit comprises: the circuit comprises an integrator, a main comparator, an auxiliary comparator, a ring oscillator, an RS latch, a D trigger, an AND gate, a NOT gate and a reset switch. The invention uses the main comparator to turn over in advance and controls the auxiliary high-frequency dynamic comparator to work in part of time in the period, thereby not only effectively reducing the power consumption of the system, but also improving the precision and the linearity of current-frequency conversion.

Description

Current-frequency conversion circuit and working method thereof

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a current-frequency conversion circuit and a working method thereof.

Background

In current sensing applications, current-to-frequency conversion circuits are used. The current-frequency conversion circuit converts the current signal into a frequency signal, and measures the magnitude of the current signal indirectly by measuring the frequency of the output signal. The current-frequency conversion circuit has the advantages of simple structure, easy realization, low cost and high conversion resolution.

Liu Xiaoming, etc. volume 30 of the university of Lanzhou university of transportation in 2011In the "design of an I-F conversion circuit in weak current measurement" written by people, a schematic structural diagram of a conventional current-frequency conversion circuit shown in fig. 1 is used. The circuit is mainly composed of an integrator 100, a comparator 200, a monostable trigger circuit 300 and a reset switch 400. The integrator 100 is composed of an operational amplifier 105 and a charge/discharge capacitor 110. In the circuit operation process, when the output voltage 130 of the integrator 100 is greater than the reference voltage 205 of the comparator 200, the output voltage 210 of the comparator 200 is inverted from a low level to a high level, and then the monostable circuit 300 is triggered to generate a pulse signal with a certain width and amplitude to control the closing of the reset switch 400, so as to realize the discharging operation of the feedback capacitor 110, the output voltage 130 of the integrator is gradually reduced, when the output voltage 210 of the comparator is decreased to the reference voltage 205 of the comparator, the output voltage 210 of the comparator is inverted from the high level to the low level, and the monostable output 400 is inverted from the high level to the low level, so that the reset switch 400 is opened, and therefore, the charging state is started again. By repeating the above process, an oscillation frequency of the output signal proportional to the magnitude of the input current can be generated. In the structure of the current-frequency conversion circuit, a continuous time comparator is used, and the static power consumption consumed by the continuous time comparator is relatively large. Since the current-frequency conversion circuit always compares the output voltage 130 of the integrator 100 with the reference voltage 205 of the comparator during operation, the current of the comparator 100 is not reasonably utilized due to the continuous operation state of the comparator, thereby increasing the power consumption of the current-frequency conversion circuit. In addition, the continuous time comparator is slow and generates a delay T with the process, power supply voltage, and temperature variations (PVT)_dAs shown in fig. 3. Therefore, the delay generated by the comparator can cause the zero crossing point to be detected inaccurately, and as a result, the output frequency of the current-frequency conversion circuit has errors, which affects the linearity and precision of the current-frequency conversion circuit.

Therefore, it is necessary to provide a current-frequency conversion circuit to solve the above problems.

Disclosure of Invention

Technical problem to be solved

The invention aims to solve the technical problems of high power consumption, low linearity and low precision of the traditional current-frequency conversion circuit, and controls the auxiliary high-frequency dynamic comparator which accurately detects the zero crossing point to be started at partial time in a period by using the main comparator to overturn in advance.

(II) technical scheme

The whole current-frequency conversion circuit comprises an integrator, a main comparator, a ring oscillator, an auxiliary comparator, an RS latch, a first D trigger, a second D trigger, a NOT gate, an AND gate and a reset switch.

The integrator comprises an operational amplifier and a feedback capacitor;

the ring oscillator comprises PMOS transistors and a plurality of odd number of inverters connected end to end.

The whole working process of the current-frequency conversion circuit can be divided into two stages: a charging phase and a discharging phase.

In the first stage, the current source to be tested inputs current to the integrator. The integrator output voltages are connected to the positive inputs of the main comparator and the auxiliary comparator, respectively. The reference voltage of the main comparator is slightly lower than that of the auxiliary comparator. When the output voltage of the integrator continuously rises, the main comparator can overturn before the auxiliary comparator, the output voltage of the main comparator is overturned from low level to high level, the output voltage of the main comparator is connected to the clock input end of the first D trigger, and the data input end of the first D trigger is connected with the high level. Therefore, the inversion of the output voltage of the main comparator causes the inverted output signal of the first D flip-flop to be inverted from high level to low level. And a signal output by the negative end of the first D trigger is connected to the grid electrode of a PMOS (P-channel metal oxide semiconductor) enabling tube of the ring oscillator, so that the PMOS enabling tube is conducted, and the ring oscillator starts to oscillate after a short oscillation starting time. The output signal of the ring oscillator is used as the input clock signal of the auxiliary comparator to control the auxiliary comparator to start working. Since the integrator output voltage is lower than the reference voltage of the auxiliary comparator at this time, the negative side output signal of the auxiliary comparator is a series of short pulse signals, and the positive side output signal of the auxiliary comparator is kept at a low level. When the output voltage of the integrator rises to the reference voltage of the auxiliary comparator, the output signal of the negative end of the auxiliary comparator is at a low level, the output signal of the positive end of the auxiliary comparator is at a high level, the output signal of the positive end of the auxiliary comparator is connected with the set end of the RS latch, the output signal of the positive end of the RS latch is turned from the low level to the high level, the output signal of the positive end of the RS latch is connected to the clock input end of the second D trigger, the data input end of the second D trigger is connected with the high level, and the output signal of the positive end of the second D trigger is turned from the low level to the high level. Since the output signal of the main comparator is already at a high level, the output signals of the second D flip-flop and the main comparator are output at a high level after passing through the and gate.

In the second stage, in the discharging stage, after the output signal of the and gate is at a high level, on one hand, the switch for resetting is controlled to be closed, so that the feedback capacitor starts to discharge, and on the other hand, the output signal of the and gate is input to the resetting end of the first D trigger, so that the signal output by the negative end of the first D trigger is inverted from a low level to a high level. Since the signal output by the negative end of the first D trigger is connected with the grid electrode of the PMOS enabling tube, the PMOS enabling tube is disconnected, the ring oscillator stops oscillating, and the output clock signal of the ring oscillator is kept at a low level. When the output voltage of the integrator drops to the reference voltage of the auxiliary comparator, the auxiliary comparator stops working because the ring oscillator stops oscillating at the moment, and the auxiliary comparator is in a reset state, so that two output signals of the auxiliary comparator are both low level. When the input set end and the reset end of the RS latch are both in low level, the output end signal is kept unchanged, so that the output signal of the positive end of the RS latch keeps in high level. The output voltage of the integrator continues to drop, and when the output voltage of the integrator drops to the reference voltage of the main comparator, the output signal of the main comparator is inverted from high level to low level. Because the output signal of the main comparator is connected to the input end of the AND gate, the output signal of the AND gate is turned from high level to low level, the reset switch is switched off, the discharging process is finished, and the whole signal period is finished. Meanwhile, the output signal of the main comparator is input to the reset terminal of the second D flip-flop after passing through the not gate, so that the output signal of the positive terminal of the second D flip-flop is inverted from high level to low level.

Preferably, the main comparator is designed as a continuous time comparator, the input stage adopts a basic transconductance amplifier structure, and the output stage adopts push-pull output.

It is further preferred that the auxiliary comparator is designed as a clocked dynamic comparator. Two phase inverters are connected end to form a positive feedback latch structure, so that the performance of the comparator is improved. When the clock signal is at low level, the auxiliary comparator is in reset state, and the output signals are all at low level; when the clock signal is at a high level, the auxiliary comparator starts to operate to perform comparison.

Preferably, the bandgap reference circuit generates a zero temperature coefficient current, and then the current is divided by the resistor to generate a reference voltage of the main comparator and a reference voltage of the auxiliary comparator, and the reference voltage of the main comparator is controlled to be slightly lower than the reference voltage of the auxiliary comparator, so that the main comparator is inverted before the auxiliary comparator.

(III) advantageous effects

According to the technical scheme, the invention has the following beneficial effects:

1. the main comparator is used for reversing in advance to generate an enable signal to control the auxiliary comparator to work. Because the power consumption of the main comparator is very low, the auxiliary comparator is started only in part of the time in the period, and the purpose of reducing the power consumption of the system is achieved.

2. The auxiliary comparator is a dynamic comparator and does not consume static power consumption.

3. The auxiliary comparator adopts a high-frequency dynamic comparator, so that zero crossing point detection can be more accurately realized, and the linearity and the precision of the system are improved.

4. The auxiliary dynamic comparator turns off the input clock signal through the feedback signal immediately after detecting that the input signal reaches the reference voltage of the auxiliary dynamic comparator, so that the auxiliary comparator stops working in time, and the power consumption of the system is further reduced.

Drawings

FIG. 1 is a conventional current-to-frequency conversion circuit;

fig. 2 OTA-based continuous-time comparator;

fig. 3 delay T of OTA-based continuous-time comparator_d；

FIG. 4 is a circuit diagram of the dual comparator based current-to-frequency conversion of the present invention;

FIG. 5 is a waveform diagram of a current-to-frequency conversion circuit;

fig. 6 shows a circuit diagram of an auxiliary comparator.

Detailed Description

The technical scheme of the invention is further explained with reference to the accompanying drawings 2-6.

The whole current-frequency conversion circuit comprises an integrator 100, a main comparator 200, a ring oscillator 300, an auxiliary comparator 400, an RS latch 430, a D flip-flop 220, a D flip-flop 505, a NOT gate 520, an AND gate 530 and a reset switch 600.

Wherein the integrator 100 includes an operational amplifier 105 and a feedback capacitor 110;

the ring oscillator 300 includes a PMOS transistor 305 and an odd number of inverters 330-1-330-n connected end-to-end.

The working structure of the whole current-frequency conversion circuit is shown in fig. 4, and the circuit working process can be divided into two stages: a charging phase and a discharging phase.

In the first stage charge phase, the current source 120 under test inputs current into the integrator 100. The integrator output voltage 130 is connected to the positive inputs of the main comparator 200 and the auxiliary comparator 400, respectively. The inverting input of the main comparator is connected to a reference potential 205 and the inverting input of the auxiliary comparator is connected to a reference potential 405. Reference voltage 205 is slightly smaller in magnitude than reference voltage 405. When the output voltage 130 of the integrator 100 continuously rises, the main comparator will flip before the auxiliary comparator, and the output voltage 210 of the main comparator 200 will flip from low level to high level, and 210 is connected to the clock input terminal of the D flip-flop 220 triggered by the rising edge, and the data input terminal of the flip-flop 220 is connected to high level. The toggling of the output voltage 210 of the main comparator 200 causes the negative side output signal 225 of the flip-flop 220 to toggle from a high level to a low level. Signal 225 is coupled to the gate of PMOS enable 305 of ring oscillator 300 so that PMOS enable 305 is turned on, ring oscillator 300 begins oscillating after a short attack time. The output signal 320 of the ring oscillator 300 is used as a clock input signal for the auxiliary comparator 400 to control the auxiliary comparator 400 to start operating. Since the integrator 100 output voltage 130 is now lower than the reference voltage 405 of the auxiliary comparator 400, the negative side output signal 415 of the auxiliary comparator 400 is a series of short pulse signals and the positive side output signal 410 of the auxiliary comparator 400 remains low. When the output voltage 130 of the integrator 100 rises to the reference voltage 405 of the auxiliary comparator 400, as shown at time t2 in fig. 5, the output signal 415 of the negative terminal of the auxiliary comparator 400 is at a low level, the output signal 410 of the positive terminal is at a high level, and since the signal 410 is connected to the set terminal of the RS latch, the output signal 435 of the positive terminal of the RS latch is inverted from the low level to the high level, the signal 435 is connected to the clock input terminal of the D flip-flop 505 triggered by the rising edge, and the data input terminal of the D flip-flop 505 is connected to the high level, so the forward output signal 525 of the DFF2 is inverted from the low level to the high level. Since 130 is already high, the post output signal 600 of 525 and 210 through the AND gate is high.

In the second stage, in the discharging stage, after the signal 600 is at a high level, on one hand, the switch for controlling the reset is closed, so that the feedback capacitor 110 starts to discharge, and on the other hand, the signal 600 is input to the reset terminal of the flip-flop 220, so that the signal 225 output by the negative terminal of the flip-flop 220 is inverted from a low level to a high level. When the signal 225 goes high and the gate of the PMOS enable transistor 305 is connected, the PMOS enable transistor 305 is disconnected, the ring oscillator 300 stops oscillating and the output clock signal 320 remains low. Due to the closing of the reset switch, the output voltage 130 of the integrator drops sharply, and when the voltage 130 drops to the reference voltage 405 of the auxiliary comparator 400, i.e. at time t3 in fig. 2, since the ring oscillator 300 has stopped oscillating at this time, the auxiliary comparator 400 stops working and is in a reset state, so that both

output signals

410 and 415 of the auxiliary comparator 400 are at a low level. The value of 435 remains high because the output signal 435 remains unchanged when both the set and reset terminals of the RS latch 430 are low. The output voltage 130 of the integrator 100 continues to drop and the main comparator 200 output signal 210 flips from high to low when 130 drops to the reference voltage 205 of the main comparator 200, i.e., at time t4 in fig. 5. Since 210 is connected to the input terminal of and gate 530, it causes the output signal 600 of and gate 530 to turn from high level to low level, which causes the reset switch to turn off, the discharging process ends, and the whole signal cycle is completed. Meanwhile, 130 is inputted to the reset terminal of the D flip-flop 505 after passing through the inverter 520, which causes the output signal 525 of the D flip-flop 505 to be inverted from high level to low level. The reset operation of the D flip-flop 505 is necessary, otherwise, the output signal 525 is always high, and during the next charging process, due to the effect of the and gate 530, as long as the output signal 210 of the main comparator 200 is high, the output signal 600 of the and gate 530 will be inverted from low to high, which is not in accordance with the original design.

The main comparator 200 is designed as a continuous-time comparator, and as shown in fig. 2, the input stage adopts a basic transconductance amplifier structure, and the output stage adopts push-pull output.

The auxiliary comparator 400 is designed as a clocked dynamic comparator as shown in fig. 6. Wherein, M3 and M5, M4 and M6 respectively form inverters, and then two inverters are connected end to form a positive feedback latch structure, so as to improve the performance of the comparator. M7, M8,

Is a MOS tube controlled by a clock. When the clock signal CLK is at low level, the auxiliary comparator is in reset state, and output signals Voutp and Voutn are both at low level; the auxiliary comparator starts to operate when the clock signal CLK is high, and performs comparison.

A zero temperature coefficient current is generated by a bandgap reference circuit, and then the current is divided by a resistor to generate an input signal 205 of the main comparator 200 and an input signal 405 of the auxiliary comparator, and the control 205 is slightly smaller than 405, so that the main comparator is inverted before the auxiliary comparator.

In terms of power consumption, the continuous time comparator of the conventional current-frequency conversion circuit has a high requirement on speed, so that the bias current of the comparator is high, and the power consumption is also high. The current-frequency conversion circuit based on the dual comparator can optimize the power consumption in the following four aspects:

(1) because the main comparator in the invention is mainly used for triggering the auxiliary comparator to work by overturning in advance in each period, the requirement on the speed of the main comparator is not high, and the power consumption of the comparator is reduced by sacrificing the speed. The bias current of the main comparator can be set as small as possible, so that the comparator which continuously works consumes the power consumption as small as possible.

(2) The auxiliary comparator is a dynamic comparator controlled by a clock, and does not consume static power consumption.

(3) The auxiliary comparator is only turned on during a portion of the cycle and only when active will dynamic power be generated.

(4) The auxiliary dynamic comparator immediately turns off the input clock signal through the feedback signal after detecting that the input signal reaches the reference voltage of the auxiliary dynamic comparator, so that the auxiliary comparator stops working in time, the working time of the auxiliary comparator is shortened as much as possible, and the power consumption of the system is further reduced.

Meanwhile, in the aspect of linearity, because a continuous time comparator is used in a conventional current-frequency conversion circuit and the speed of the continuous time comparator is limited, the zero crossing point detection of the conventional current-frequency conversion circuit is not accurate enough, and the linearity of current-frequency conversion is affected. The high-frequency dynamic comparator is adopted, so that the speed is higher, the zero crossing point is more accurately detected, and the linearity of current-frequency conversion is higher.

The above embodiments are intended to further illustrate the technical solution of the present invention, and the specific scope of protection is subject to the description of the claims.

Claims

1. A current-frequency conversion circuit comprises an integrator, a main comparator and a reset switch, and is characterized by further comprising an auxiliary comparator, a ring oscillator, an RS latch, two D triggers, an AND gate and a NOT gate;

the integrator comprises an operational amplifier and a feedback capacitor;

the main comparator comprises a first input end, a second input end and an output end;

the auxiliary comparator comprises a first signal input end, a second signal input end, a clock input end, a first output end and a second output end;

the current source to be detected flows into the integrator, and the output end of the integrator is respectively connected to the first input end of the main comparator and the first input end of the auxiliary comparator;

signals of second input ends of the main comparator and the auxiliary comparator are respectively compared with signals of an output end of the integrator;

the two D triggers are divided into a first D trigger and a second D trigger;

the first D flip-flop and the second D flip-flop respectively comprise a data input end, a clock input end, a reset end, a first output end and a second output end;

the AND gate comprises a first input end, a second input end and an output end;

the output end of the main comparator is connected to the clock input end of the first D trigger, the data input end of the first D trigger is connected with a high level, and the output end of the AND gate is connected with the reset end of the first D trigger;

the ring oscillator comprises an MOS enabling tube and a plurality of odd number of phase inverters which are connected end to end;

the second output end of the first D trigger is connected with the grid electrode of the MOS enabling tube;

the output end of the ring oscillator is connected to the clock input end of the auxiliary comparator;

the RS latch comprises a first input end, a second input end and an output end;

a first output end of the auxiliary comparator is connected with a first input end of the RS latch, and a second output end of the auxiliary comparator is connected with a second input end of the RS latch;

the output end of the RS latch is connected to the clock input end of a second D trigger, and the data input end of the second D trigger is connected with a high level;

the output end of the main comparator is connected with the input end of the NOT gate, and the output end of the NOT gate is connected with the reset end of the second D trigger;

the first output end of the second trigger is connected with the first input end of the AND gate, the output end of the main comparator is connected with the second input end of the AND gate, and the output end of the AND gate is connected with the reset switch.

2. The current-to-frequency conversion circuit of claim 1, wherein the main comparator is a continuous-time comparator.

3. The current-to-frequency conversion circuit of claim 1, wherein the auxiliary comparator is a clocked dynamic comparator.

4. The current-to-frequency conversion circuit of claim 1, wherein the signal at the second input of the main comparator is lower than the signal at the second input of the auxiliary comparator.

5. An operating method of a current-frequency conversion circuit, which is applied to the current-frequency conversion circuit according to any one of claims 1 to 4, comprising:

the current source to be measured flows into the integrator, and the voltage of the output end of the integrator is gradually increased;

when the voltage of the output end of the integrator is gradually increased, the main comparator is turned over before the auxiliary comparator, the ring oscillator is controlled to generate a clock signal through the first D trigger, and the ring oscillator triggers the auxiliary comparator to start working;

when a first input end signal of the auxiliary comparator is higher than a second input end signal, the output of the auxiliary comparator is overturned, so that the output of the RS latch is triggered to be overturned;

the switching of the output of the RS latch triggers the conduction of the reset switch by controlling the second D trigger and the AND gate, so that the feedback capacitor is rapidly discharged, and the output voltage of the integrator is rapidly reduced; meanwhile, an AND gate output signal controls the ring oscillator to stop oscillating through the first D trigger, and the auxiliary comparator stops working;

when the output voltage of the integrator is reduced to the potential of the second input end of the main comparator, the output of the main comparator is turned over, and the reset switch is disconnected through the AND gate; a new round of charging and discharging process starts.