CN114665735B - ANPC three-level inverter topology circuit, control method and control device - Google Patents

ANPC three-level inverter topology circuit, control method and control device Download PDF

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CN114665735B
CN114665735B CN202210578273.9A CN202210578273A CN114665735B CN 114665735 B CN114665735 B CN 114665735B CN 202210578273 A CN202210578273 A CN 202210578273A CN 114665735 B CN114665735 B CN 114665735B
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diode
turning
tube
moment
mos
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CN114665735A (en
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陈建明
叶智
肖培谦
吴龙生
卢钢
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ZHEJIANG HRV ELECTRIC CO Ltd
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ZHEJIANG HRV ELECTRIC CO Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention discloses an ANPC three-level inversion topological circuit, a control method and a control device, which are applicable to the technical field of circuits. Each switch tube adopts an MOS tube and adds an MOS tube of a common source in each MOS tube, and a first MOS tube is turned on and then turned off compared with a second MOS tube in each switch control, so that one MOS tube is a hard switch and other MOS tubes are soft switches in different modes, and the switching loss of the switch tubes is reduced. Meanwhile, the conduction of the MOS tube is used as synchronous rectification, the conduction resistance is small, and the conduction loss is effectively reduced. In addition, only the first diode, the fourth diode, the fifth diode and the sixth diode corresponding to the anti-parallel diodes are SIC diodes, the high-frequency switch tubes adopt MOS tubes, and the corresponding MOS tubes have follow currents, so that the capacity is small, the adopted cost is low, and the problem of cost increase caused by the fact that the SIC diodes are used by the anti-parallel diodes and the four high-frequency switch tubes in the existing matching mode is solved.

Description

ANPC three-level inversion topology circuit, control method and control device
Technical Field
The invention relates to the technical field of circuits, in particular to an ANPC three-level inverter topology circuit, a control method and a control device.
Background
The inverter is a converter which converts current electric energy (batteries, storage batteries and the like) into constant-frequency constant-voltage or frequency-modulation voltage-regulation alternating current. Active Neutral-clamped (ANPC) type three-level inverter topologies are commonly used in photovoltaic inverters for high voltage high power applications.
Fig. 1 is a structural diagram of a conventional ANPC three-level inverter topology circuit, which is composed of 6 switching tubes T1-T6 and respective anti-parallel diodes D1-D6, and the general control modes are T1, T4, T5 and T6 switching tubes high-frequency driving and T2 and T3 power-frequency driving. There are two general matching ways, one is to use Insulated Gate Bipolar Transistors (IGBTs) for all 6 switching tubes, and the other is to use IGBTs for T2 and T3 switching tubes, and silicon carbide (SIC) diodes are used for the T1, T4, T5, T6 switching tubes and anti-parallel diodes. The 6 switch tubes of the first collocation mode all adopt IGBT, because IGBT tailing problem, its switching frequency is lower can't improve, need adopt the inductance of great volume, contradicts with the miniaturized trend of equipment product, and simultaneously, IGBT has switching loss, and its efficiency is lower. The second matching mode adopts a SIC/IGBT combined mode, for the high-power occasion, the price of the SIC device is linearly increased along with the current, and the price and the cost of the SIC under the same power are higher when four high-frequency switching tubes and respective anti-parallel diodes are used.
Therefore, a need for solving the problem of how to improve the efficiency and reduce the cost of the ANPC three-level inverter topology circuit is urgently needed by those skilled in the art.
Disclosure of Invention
The invention aims to provide an ANPC three-level inverter topology circuit, a control method and a control device, which can improve the efficiency of the ANPC three-level inverter topology circuit and reduce the cost.
In order to solve the above technical problem, the present invention provides an ANPC three-level inverter topology circuit, which includes a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a switch unit, a first switch tube and a second switch tube;
the cathode of the second diode is connected with the collector of the first switching tube, the anode of the second diode is connected with the emitter of the first switching tube, the cathode of the third diode is connected with the collector of the second switching tube, and the anode of the third diode is connected with the emitter of the second switching tube;
the first diode, the fourth diode, the fifth diode and the sixth diode are SIC diodes and are respectively connected with a switch unit in parallel, wherein the switch unit comprises a first MOS tube and a second MOS tube, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is used for being switched on and off in the first diode, the fourth diode, the fifth diode and the sixth diode in comparison with the second MOS tube.
Preferably, the first switch tube and the second switch tube are both IGBT switch tubes.
Preferably, the capacitor further comprises a first capacitor, a second capacitor and a first inductor;
the first end of the first capacitor is connected with the cathode of the first diode, the second end of the first capacitor, the anode of the fifth diode and the cathode of the sixth diode are connected with the first end of the second capacitor, the second end of the second capacitor is connected with the anode of the fourth diode, and the first end of the first inductor and the anode of the second diode are connected with the cathode of the third diode.
In order to solve the above technical problem, the present invention further provides a method for controlling an ANPC three-level inverter topology circuit, which is applied to the ANPC three-level inverter topology circuit, and includes:
acquiring a current operation mode of the ANPC three-level inverter topology circuit;
when the current operation mode is an active power mode, turning off a second MOS tube of the switching tube which does not provide the corresponding follow current loop at a first moment, turning off a first MOS tube of the switching tube which does not provide the corresponding follow current loop at a second moment, turning on the first MOS tube of the switching tube which provides the corresponding follow current loop at a third moment, and turning on the second MOS tube of the switching tube which provides the corresponding follow current loop at a fourth moment;
when the current operation mode is a reactive power mode, the second MOS tube of the switch tube corresponding to the follow current loop is turned off at the first moment, the first MOS tube of the switch tube corresponding to the follow current loop is turned off at the second moment, the first MOS tube of the switch tube corresponding to the follow current loop is turned on at the third moment, and the second MOS tube of the switch tube corresponding to the follow current loop is turned on at the fourth moment.
Preferably, when the current operation mode is an active power mode, the method further includes turning off a second MOS transistor of the switching transistor not providing a freewheeling circuit at a first time, turning off a first MOS transistor of the switching transistor not providing a freewheeling circuit at a second time, turning on a first MOS transistor of the switching transistor providing a freewheeling circuit at a third time, and turning on a second MOS transistor of the switching transistor providing a freewheeling circuit at a fourth time, including:
when the current operation mode is the positive half cycle of the active power mode, turning off a second MOS tube corresponding to the first switch tube at the first moment, turning off a first MOS tube corresponding to the first switch tube at the second moment, turning on a first MOS tube corresponding to the fifth switch tube at the third moment, and turning on a second MOS tube corresponding to the fifth switch tube at the fourth moment;
when the current operation mode is the negative half cycle of the active power mode, the second MOS tube corresponding to the fourth switching tube is turned off at the first moment, the first MOS tube corresponding to the fourth switching tube is turned off at the second moment, the first MOS tube corresponding to the sixth switching tube is turned on at the third moment, and the second MOS tube corresponding to the sixth switching tube is turned on at the fourth moment.
Preferably, when the current operation mode is a reactive power mode, the method includes turning off the second MOS transistor of the switching transistor corresponding to the freewheeling circuit at a first time, turning off the first MOS transistor of the switching transistor corresponding to the freewheeling circuit at a second time, turning on the first MOS transistor of the switching transistor corresponding to the freewheeling circuit at a third time, and turning on the second MOS transistor of the switching transistor corresponding to the freewheeling circuit at a fourth time, and includes:
when the current operation mode is the positive half cycle of the reactive power mode, turning off a second MOS tube corresponding to the first switch tube at the first moment, turning off a first MOS tube corresponding to the first switch tube at the second moment, turning on a first MOS tube corresponding to the fifth switch tube at the third moment, and turning on a second MOS tube corresponding to the fifth switch tube at the fourth moment;
when the current operation mode is the negative half cycle of the reactive power mode, the second MOS tube corresponding to the fourth switching tube is turned off at the first moment, the first MOS tube corresponding to the fourth switching tube is turned off at the second moment, the first MOS tube corresponding to the sixth switching tube is turned on at the third moment, and the second MOS tube corresponding to the sixth switching tube is turned on at the fourth moment.
In order to solve the above technical problem, the present invention further provides a control device for an ANPC three-level inverter topology circuit, which is applied to the ANPC three-level inverter topology circuit, and includes:
the acquisition module is used for acquiring the current operation mode of the ANPC three-level inverter topology circuit;
the first operation module is used for turning off a second MOS (metal oxide semiconductor) tube of the switch tube which does not provide the corresponding follow current loop at a first moment, turning off a first MOS tube of the switch tube which does not provide the corresponding follow current loop at a second moment, turning on the first MOS tube of the switch tube which provides the corresponding follow current loop at a third moment and turning on the second MOS tube of the switch tube which provides the corresponding follow current loop at a fourth moment when the current operation mode is the active power mode;
and the second operation module is used for turning off a second MOS tube of the switch tube corresponding to the follow current loop at a first moment, turning off a first MOS tube of the switch tube corresponding to the follow current loop at a second moment, turning on a first MOS tube of the switch tube corresponding to the follow current loop at a third moment, and turning on a second MOS tube of the switch tube corresponding to the follow current loop at a fourth moment.
The invention provides an ANPC three-level inverter topology circuit which comprises a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a switch unit, a first switch tube and a second switch tube, wherein the first diode, the second diode, the third diode, the fourth diode, the fifth diode, the sixth diode, the switch unit and the first switch tube are connected in series; the cathode of the second diode is connected with the collector of the first switching tube, the anode of the second diode is connected with the emitter of the first switching tube, the cathode of the third diode is connected with the collector of the second switching tube, and the anode of the third diode is connected with the emitter of the second switching tube; the first diode, the fourth diode, the fifth diode and the sixth diode are SIC diodes and are respectively connected with a switch unit in parallel, wherein the switch unit comprises a first MOS tube and a second MOS tube, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is used for being switched on and off in the first diode, the fourth diode, the fifth diode and the sixth diode in comparison with the second MOS tube. On the basis of the existing topological circuit, on the one hand, each switch tube adopts an MOS tube and adds an MOS tube with a common source in each MOS tube, the first MOS tube is turned on and then turned off earlier than the second MOS tube in each switch control, so that one MOS tube in different modes is a hard switch, and the rest MOS tubes are soft switches, thereby reducing the switching loss of the switch tube, and avoiding the problems of tailing and switching loss caused by the fact that all the IGBT switch tubes are used by the first MOS tube and the second MOS tube corresponding to each switch tube in the existing topological structure. Meanwhile, the conduction of the MOS tube is used as synchronous rectification, the conduction resistance is small, the conduction loss is effectively reduced, and the product efficiency is improved. On the other hand, in the circuit, only the first diode, the fourth diode, the fifth diode and the sixth diode corresponding to the anti-parallel diodes are SIC diodes, and the first MOS tubes corresponding to the first diode, the fourth diode, the fifth diode and the sixth diode are high-frequency switching tubes and adopt MOS tubes; compared with the traditional SIC diode, the corresponding MOS tube has follow current, so that the capacity is smaller, the adopted cost is lower, and the problem of cost increase caused by the use of the SIC diode by the anti-parallel diode and the four high-frequency switching tubes in the conventional matching mode is solved. In conclusion, the circuit improves the product efficiency and reduces the cost.
In addition, the invention also provides a control method and a control device of the ANPC three-level inverter topology circuit, which have the same beneficial effects as the ANPC three-level inverter topology circuit.
Drawings
In order to illustrate the embodiments of the present invention more clearly, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a structural diagram of a conventional ANPC three-level inverter topology circuit;
fig. 2 is a structural diagram of an ANPC three-level inverter topology circuit according to an embodiment of the present invention;
fig. 3 is a flowchart of a control method of an ANPC three-level inverter topology circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of positive half cycle active mode commutation according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a positive half cycle mode driving according to an embodiment of the present invention;
fig. 6 is a schematic diagram of negative half cycle active mode commutation according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a negative half cycle mode driving according to an embodiment of the present invention;
fig. 8 is a schematic diagram of commutation in the positive half cycle reactive mode according to an embodiment of the present invention;
fig. 9 is a schematic diagram of commutation in the negative half cycle reactive mode according to an embodiment of the present invention;
fig. 10 is a structural diagram of a control device of an ANPC three-level inverter topology circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
The core of the invention is to provide an ANPC three-level inverter topology circuit, a control method and a control device, which can improve the efficiency of the ANPC three-level inverter topology circuit and reduce the cost.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
It should be noted that, the ANPC three-level inverter topology circuit provided by the present invention is suitable for a photovoltaic inverter in a high-voltage and high-power situation, and is matched with a suitable control mode, and compared with the matching mode of the existing ANPC three-level inverter topology circuit, for the first matching mode, all of 6 switching tubes adopt IGBT switching tubes, the switching frequency of the IGBT switching tubes cannot be increased, the inductance volume is relatively large, and the IGBT has switching loss, and the efficiency is low; for the second matching mode, for the high-power occasion, the price of the SIC device is increased linearly along with the current, the price and the cost of the SIC device are higher when four high-frequency tubes and respective anti-parallel diodes use the same power, and the product is gradually pursued to be miniaturized. The invention ensures that the loss of the switch tube is reduced under the active and reactive conditions, improves the efficiency and simultaneously reduces the cost of the switch tube.
Fig. 2 is a structural diagram of an ANPC three-level inverter topology circuit according to an embodiment of the present invention, where the circuit includes: the first diode, the second diode, the third diode, the fourth diode, the fifth diode, the sixth diode, the switch unit, the first switch tube and the second switch tube;
the cathode of the second diode is connected with the collector of the first switching tube, the anode of the second diode is connected with the emitter of the first switching tube, the cathode of the third diode is connected with the collector of the second switching tube, and the anode of the third diode is connected with the emitter of the second switching tube;
the first diode, the fourth diode, the fifth diode and the sixth diode are SIC diodes and are respectively connected with a switch unit in parallel, wherein the switch unit comprises a first MOS tube and a second MOS tube, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is used for being switched on and off in the first diode, the fourth diode, the fifth diode and the sixth diode in comparison with the second MOS tube.
As shown in fig. 2, each of the first diode D1, the fourth diode D4, the fifth diode D5 and the sixth diode D6 is connected in parallel to a switching unit, wherein the switching unit includes a first MOS transistor and a second MOS transistor, and a source of the first MOS transistor is connected to a source of the second MOS transistor.
The first diode D1, the fourth diode D4, the fifth diode D5, and the sixth diode D6 are SIC diodes.
It can be appreciated that the use of SIC diodes greatly improves the efficiency and stability of inverters, motor drives, uninterruptible power supplies and electric vehicle circuitry. For high-power occasions, the price of SIC devices increases linearly, the matching mode of the conventional ANPC three-level inverter topology circuit is shown in figure 1, and SIC diodes are adopted for T1, T4-T6 switching tubes and D1-D6, so that the cost of the inverter is greatly increased. The first diode D1, the fourth diode D4, the fifth diode D5 and the sixth diode D6 which correspond to the anti-parallel diodes are SIC diodes, and because the corresponding MOS tubes follow current, the capacity is small, the adopted cost is low, and the problem of cost increase caused by the fact that the anti-parallel diodes and the four high-frequency tubes use the SIC diodes in the existing collocation mode is solved.
In this embodiment, only the first diode D1, the fourth diode D4, the fifth diode D5, and the sixth diode D6 are SIC diodes, and a small current, generally around 1/3 with the same power, is used.
First and second MOS transistors Q1 and Q1A corresponding to the switching unit of first diode D1, first and second MOS transistors Q4 and Q4A corresponding to the switching unit of fourth diode D4, first and second MOS transistors Q5 and Q5A corresponding to the switching unit of fifth diode D5, first and second MOS transistors Q6 and Q6A corresponding to the switching unit of sixth diode D6, the cathode of first diode D1 and the anode of fifth diode D5 are connected to the cathode of sixth diode D6, the anode of first diode D1 and the cathode of fifth diode D5 are connected to the cathode of second diode D2, the anode of second diode D2 is connected to the cathode of third diode D3, the anode of third diode D3 and the anode of sixth diode D6 are connected to the cathode of fourth diode D6, and the anode of fourth diode D6 and the cathode of fifth diode D6 are connected to the anode of fifth diode D6.
A cathode of the second diode D2 is connected to a collector of the first switching transistor Q2, an anode of the second diode D2 is connected to an emitter of the first switching transistor Q2, a cathode of the third diode D3 is connected to a collector of the second switching transistor Q3, and an anode of the third diode D3 is connected to an emitter of the second switching transistor Q3.
In the control process, for the positive half cycle of the ANPC three-level inverter topology circuit, the first MOS tube Q1 corresponding to the switch unit of the first diode D1 and the first MOS tube Q5 corresponding to the switch unit of the fifth diode D5 are driven in a high-frequency complementary mode, and the first switch tube Q2 is normally open; for the negative half cycle of the ANPC three-level inverter topology circuit, the first MOS transistor Q4 corresponding to the switching unit of the fourth diode D4 and the first MOS transistor Q6 corresponding to the switching unit of the sixth diode D6 are driven in a high-frequency complementary manner, and the second switching transistor Q3 is normally open.
Specifically, Q is turned on and off before Q is turned off, and Q1 and Q1A are connected in anti-parallel with first diode D1, Q4 and Q4A and fourth diode D4, Q5 and Q5A are connected in anti-parallel with fifth diode D5, Q6 and Q6A and sixth diode D6.
The invention provides an ANPC three-level inverter topology circuit which comprises a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a switch unit, a first switch tube and a second switch tube, wherein the first diode, the second diode, the third diode, the fourth diode, the fifth diode, the sixth diode, the switch unit and the first switch tube are connected in series; the cathode of the second diode is connected with the collector of the first switching tube, the anode of the second diode is connected with the emitter of the first switching tube, the cathode of the third diode is connected with the collector of the second switching tube, and the anode of the third diode is connected with the emitter of the second switching tube; the first diode, the fourth diode, the fifth diode and the sixth diode are SIC diodes and are respectively connected with a switch unit in parallel, wherein the switch unit comprises a first MOS tube and a second MOS tube, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is used for being switched on and off in the first diode, the fourth diode, the fifth diode and the sixth diode in comparison with the second MOS tube. On the basis of the existing topological circuit, on the one hand, each switch tube adopts an MOS tube and adds an MOS tube with a common source in each MOS tube, the first MOS tube is turned on and then turned off earlier than the second MOS tube in each switch control, so that one MOS tube in different modes is a hard switch, and the rest MOS tubes are soft switches, thereby reducing the switching loss of the switch tube, and avoiding the problems of tailing and switching loss caused by the fact that all the IGBT switch tubes are used by the first MOS tube and the second MOS tube corresponding to each switch tube in the existing topological structure. Meanwhile, the conduction of the MOS tube is used as synchronous rectification, the conduction resistance is small, the conduction loss is effectively reduced, and the product efficiency is improved. On the other hand, in the circuit, only the first diode, the fourth diode, the fifth diode and the sixth diode corresponding to the anti-parallel diodes are SIC diodes, and the first MOS tubes corresponding to the first diode, the fourth diode, the fifth diode and the sixth diode are high-frequency switching tubes and adopt MOS tubes; compared with the traditional SIC diode, the corresponding MOS tube has follow current, so that the capacity is smaller, the adopted cost is lower, and the problem of cost increase caused by the use of the SIC diode by the anti-parallel diode and the four high-frequency switching tubes in the conventional matching mode is solved. In conclusion, the circuit improves the product efficiency and reduces the cost.
On the basis of the above embodiments, the first switching tube Q2 and the second switching tube Q3 are both IGBT switching tubes.
It can be understood that the first switching tube Q2 and the second switching tube Q3 use slow IGBT switching tubes with low saturation voltage drop. The IGBT switching tube is a composite fully-controlled voltage-driven power Semiconductor device consisting of a bipolar triode and an MOS tube, and has the advantages of high input impedance of a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) and low conduction voltage drop of GTR, the GTR saturation voltage is reduced, the current-carrying density is high, and the driving current is larger; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current-carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage.
Because the IGBT switching tube has the problems of trailing and switching loss, the collocation mode of the conventional ANPC three-level inverter topology circuit is shown in figure 1, the collocation mode T1-T6 switching tubes completely use IGBTs, the switching frequency is reduced, and the efficiency is difficult to optimize.
In this embodiment, the first switch tube and the second switch tube are both IGBT switch tubes. Only the first switch tube and the second switch tube adopt IGBT tubes, the other switch tubes adopt MOS tubes, the conduction of the MOS tubes is used as synchronous rectification, the conduction resistance is small, and the conduction loss is effectively reduced; compared with the existing topological structure, the problems of tailing and switching loss caused by the fact that IGBT switching tubes are used completely are avoided, and the product efficiency is further improved.
On the basis of the above embodiment, the method further includes: the first capacitor, the second capacitor and the first inductor;
the first end of the first capacitor is connected with the cathode of the first diode, the second end of the first capacitor, the anode of the fifth diode and the cathode of the sixth diode are connected with the first end of the second capacitor, the second end of the second capacitor is connected with the anode of the fourth diode, and the first end of the first inductor and the anode of the second diode are connected with the cathode of the third diode.
Specifically, a first terminal of the first capacitor C1 is connected to a cathode of the first diode D1, a second terminal of the first capacitor C1, an anode of the fifth diode D5, and a cathode of the sixth diode D6 are connected to a first terminal of the second capacitor C2, a second terminal of the second capacitor C2 is connected to an anode of the fourth diode D4, and a first terminal of the first inductor L1 and an anode of the second diode D2 are connected to a cathode of the third diode D3.
The first capacitor, the second capacitor and the first inductor provided by the embodiment enable the structure of the ANPC three-level inverter topology circuit to be complete.
The above detailed description of the embodiment of the ANPC three-level inverter topology circuit provided by the present invention also provides a control method of the ANPC three-level inverter topology circuit corresponding to the apparatus, and since the embodiment of the method portion corresponds to the embodiment of the apparatus portion, the embodiment of the method portion refers to the description of the embodiment of the apparatus portion, and is not repeated here.
Fig. 3 is a flowchart of a control method of an ANPC three-level inverter topology circuit according to an embodiment of the present invention, and as shown in fig. 3, the method includes:
s11: acquiring a current operation mode of the ANPC three-level inverter topology circuit;
it can be understood that the current operation mode of the ANPC three-level inverter topology circuit is obtained, the operation mode at this time includes an active power mode and a reactive power mode, and the determination of the two modes depends on the current direction and the voltage direction. When the current direction is the same as the voltage direction, the power converter is in an active power mode; when the current direction is opposite to the voltage direction, the reactive power mode is in this case.
S12: when the current operation mode is an active power mode, turning off a second MOS tube of the switching tube which does not provide the corresponding follow current loop at a first moment, turning off a first MOS tube of the switching tube which does not provide the corresponding follow current loop at a second moment, turning on the first MOS tube of the switching tube which provides the corresponding follow current loop at a third moment, and turning on the second MOS tube of the switching tube which provides the corresponding follow current loop at a fourth moment;
specifically, the freewheeling circuit acts to form a closed loop according to the self-induced voltage or the electromotive force to suppress the increase of the self-induced voltage, for example, a reverse diode is connected in parallel to two ends of a coil of the direct current relay to enable the self-induced voltage or the electromotive force generated at the moment of power failure to have a closed loop, and the current flowing through the closed loop suppresses the rate of change of the magnetic flux and suppresses the increase of the self-induced voltage.
When the current operation mode is an active power mode, the second MOS tube which does not provide the switch tube corresponding to the follow current loop is turned off at the first moment, the first MOS tube which does not provide the switch tube corresponding to the follow current loop is turned off at the second moment, and the first MOS tube which does not provide the switch tube corresponding to the follow current loop is turned off at the second moment, so that the first MOS tube which does not provide the switch tube corresponding to the follow current loop is turned off hard, and the second MOS tube is turned off softly. And the first MOS tube for providing the switching tube corresponding to the follow current loop is switched on at the third moment, the second MOS tube for providing the switching tube corresponding to the follow current loop is switched on at the fourth moment, and the corresponding first MOS tube and the corresponding second MOS tube are in soft switching-on due to the follow current.
S13: when the current operation mode is a reactive power mode, the second MOS tube of the switch tube corresponding to the follow current loop is turned off at the first moment, the first MOS tube of the switch tube corresponding to the follow current loop is turned off at the second moment, the first MOS tube of the switch tube corresponding to the follow current loop is turned on at the third moment, and the second MOS tube of the switch tube corresponding to the follow current loop is turned on at the fourth moment.
When the current operation mode is the reactive power mode, the second MOS tube of the switch tube corresponding to the follow current loop is cut off at the first moment, the first MOS tube of the switch tube corresponding to the follow current loop is cut off at the second moment, because of the follow current loop, the first MOS tube and the second MOS tube of the switch tube corresponding to the follow current loop are soft cut off, the first MOS tube of the switch tube corresponding to the follow current loop is not provided at the third moment, the second MOS tube of the switch tube corresponding to the follow current loop is provided at the fourth moment, the first MOS tube of the switch tube corresponding to the follow current loop is not provided at the moment, and the second MOS tube is soft.
The embodiment of the invention provides a control method of an ANPC three-level inverter topological circuit, which comprises the steps of obtaining the current operation mode of the ANPC three-level inverter topological circuit, and when the current operation mode is an active power mode, not providing that a first MOS tube corresponding to a switch tube corresponding to a follow current loop is turned off after a second MOS tube is turned off, and providing that the first MOS tube corresponding to the switch tube corresponding to the follow current loop is turned on before the second MOS tube is turned on. When the current operation mode is a reactive power mode, the first MOS tube corresponding to the switch tube providing the follow current loop is turned off after being compared with the second MOS tube, and the first MOS tube corresponding to the switch tube not providing the follow current loop is turned on before being compared with the second MOS tube. On the one hand, each switch tube adopts an MOS tube and adds an MOS tube with a common source in each MOS tube, and a first MOS tube is turned on and then turned off in each switch control compared with a second MOS tube, so that one MOS tube is a hard switch and other MOS tubes are soft switches in different modes, the switching loss of the switch tubes is reduced, and the problems of tailing and switching loss caused by the fact that the first MOS tube and the second MOS tube corresponding to each switch tube in the existing topological structure control method are avoided. Meanwhile, the conduction of the MOS tube is used as synchronous rectification, the conduction resistance is small, the conduction loss is effectively reduced, and the product efficiency is improved. On the other hand, only the first diode, the fourth diode, the fifth diode and the sixth diode corresponding to the anti-parallel diode are SIC diodes, and the first MOS tubes corresponding to the first diode, the fourth diode, the fifth diode and the sixth diode are high-frequency switch tubes and adopt MOS tubes; compared with the traditional SIC diode, the corresponding MOS tube has follow current, so that the capacity is smaller, the adopted cost is lower, and the problem of cost increase caused by the use of the SIC diode by the anti-parallel diode and the four high-frequency switching tubes in the conventional matching mode is solved. In conclusion, the method improves the product efficiency and reduces the cost.
In a specific embodiment, when the current operation mode in step S12 is the active power mode, the method includes turning off the second MOS transistor that does not provide the switching transistor corresponding to the freewheel loop at a first time, turning off the first MOS transistor that does not provide the switching transistor corresponding to the freewheel loop at a second time, turning on the first MOS transistor that provides the switching transistor corresponding to the freewheel loop at a third time, and turning on the second MOS transistor that provides the switching transistor corresponding to the freewheel loop at a fourth time, and includes:
when the current operation mode is the positive half cycle of the active power mode, turning off a second MOS tube corresponding to the first switching tube at a first moment, turning off a first MOS tube corresponding to the first switching tube at a second moment, turning on a first MOS tube corresponding to the fifth switching tube at a third moment, and turning on a second MOS tube corresponding to the fifth switching tube at a fourth moment;
when the current operation mode is the negative half cycle of the active power mode, the second MOS tube corresponding to the fourth switching tube is turned off at the first moment, the first MOS tube corresponding to the fourth switching tube is turned off at the second moment, the first MOS tube corresponding to the sixth switching tube is turned on at the third moment, and the second MOS tube corresponding to the sixth switching tube is turned on at the fourth moment.
It can be understood that the active power mode has a positive half cycle and a negative half cycle, and when the active power mode is in the positive half cycle, fig. 4 is a schematic diagram of positive half cycle active mode commutation provided in the embodiment of the present invention, as shown in fig. 4, a circuit is switched from an operating state 1 to an operating state 2, a second MOS transistor Q1A corresponding to a first switching transistor D1 is turned off at a first time, a first MOS transistor Q1 corresponding to a first switching transistor D1 is turned off at a second time, a first MOS transistor Q5 corresponding to a fifth switching transistor D5 is turned on at a third time, and a second MOS transistor Q5A corresponding to a fifth switching transistor D5 is turned on at a fourth time; the D5 tube is freewheeling, so Q5 and Q5A are soft on, and after Q5 and Q5A are on, a commutation loop is provided, namely the D5 tube can be matched with a smaller SIC diode.
The working state 2 is switched to the working state 1, namely the Q5A tube is switched off at the fifth moment, the Q5 tube is switched off at the sixth moment, the Q5 and the Q5A are in soft switch-off due to the fact that the D5 tube continues current, the Q1 tube is switched on at the seventh moment, the Q1A tube is switched on at the eighth moment, and therefore the Q1 is hard switched on and the Q1A is soft switched on. Fig. 5 is a schematic diagram of driving in the positive half cycle mode according to an embodiment of the present invention, which corresponds to a commutation schematic diagram in the positive half cycle active power mode.
When the active power mode is in a negative half cycle, fig. 6 is a schematic diagram of the negative half cycle active mode commutation provided in the embodiment of the present invention, a circuit is switched from a working state 3 to a working state 4, a second MOS transistor Q4A corresponding to a fourth switching transistor D4 is turned off at a first time, a first MOS transistor Q4 corresponding to a fourth switching transistor D4 is turned off at a second time, it can be known that Q4 is turned off hard, and Q4A is turned off soft; the first MOS transistor Q6 corresponding to the sixth switching transistor D6 is turned on at the third time, and the second MOS transistor Q6A corresponding to the sixth switching transistor D6 is turned on at the fourth time. The D6 tube is freewheeling, so Q6 and Q6A are soft-switched on, and after Q6 and Q6A are switched on, a commutation loop is provided, namely the D6 tube can be matched with a smaller SIC diode.
The working state 4 is switched to the working state 3, namely the Q6A tube is switched off at the fifth moment, the Q6 tube is switched off at the sixth moment, the Q6 and the Q6A are in soft switch-off due to the fact that the D6 tube continues current, the Q4 tube is switched on at the seventh moment, the Q4A tube is switched on at the eighth moment, and therefore the Q4 is hard switched on and the Q4A is soft switched on. Fig. 7 is a schematic diagram of driving in the negative half cycle mode according to an embodiment of the present invention, which corresponds to a commutation schematic diagram in the negative half cycle active power mode.
According to the switching control method and the switching control device, the switching control is carried out when the circuits of the positive half cycle and the negative half cycle are switched to work states in the active power mode, so that one MOS transistor in different modes is a hard switch, and the other MOS transistors are soft switches, the switching loss of the switching transistor is reduced, and the product efficiency is improved.
In a specific embodiment, when the current operation mode in step S13 is a reactive power mode, the method includes turning off the second MOS transistor of the switching transistor corresponding to the freewheeling circuit at a first time, turning off the first MOS transistor of the switching transistor corresponding to the freewheeling circuit at a second time, turning on the first MOS transistor of the switching transistor corresponding to the freewheeling circuit at a third time, and turning on the second MOS transistor of the switching transistor corresponding to the freewheeling circuit at a fourth time, including:
when the current operation mode is the positive half cycle of the reactive power mode, turning off a second MOS tube corresponding to the first switch tube at the first moment, turning off a first MOS tube corresponding to the first switch tube at the second moment, turning on a first MOS tube corresponding to the fifth switch tube at the third moment, and turning on a second MOS tube corresponding to the fifth switch tube at the fourth moment;
when the current operation mode is the negative half cycle of the reactive power mode, the second MOS tube corresponding to the fourth switching tube is turned off at the first moment, the first MOS tube corresponding to the fourth switching tube is turned off at the second moment, the first MOS tube corresponding to the sixth switching tube is turned on at the third moment, and the second MOS tube corresponding to the sixth switching tube is turned on at the fourth moment.
When the circuit is in the positive half cycle in the reactive power mode, as shown in fig. 8, the circuit is switched from the working state 5 to the working state 6, the second MOS transistor Q1A corresponding to the first switching transistor D1 is turned off at the first time, the first MOS transistor Q1 corresponding to the first switching transistor D1 is turned off at the second time, and as the D1 transistor continues current, Q1 and Q1A are turned off softly; the first MOS transistor Q5 corresponding to the fifth switching transistor D5 is turned on at the third time, and the second MOS transistor Q5A corresponding to the fifth switching transistor D5 is turned on at the fourth time, so that Q5 is turned on hard, and Q5A is turned on soft.
The circuit is switched from the working state 6 to the working state 5, namely the Q5A tube is turned off at the fifth moment, the Q5 tube is turned off at the sixth moment, so that the Q5 tube is turned off hard, the Q5A tube is turned off soft, the Q1 tube is turned on at the seventh moment, the Q1A tube is turned on at the eighth moment, and the Q1 tube and the Q1A tube are turned on soft due to the freewheeling of the D1 diode. After Q1 and Q1A are turned on, a commutation loop is provided, i.e., the D1 transistor can be matched with a smaller SIC diode, and the positive half cycle driving can be referred to fig. 4.
When the negative half cycle is in the reactive power mode, fig. 9 is a schematic diagram of commutation in the negative half cycle reactive power mode according to the embodiment of the present invention, as shown in fig. 9, a circuit is switched from a working state 7 to a working fill 8, and a second MOS transistor Q4A corresponding to a fourth switching transistor D4 is turned off at a first time, and since a D4 transistor continues current, Q4 and Q4A are turned off softly; the first MOS transistor Q4 corresponding to the fourth switching tube D4 is turned off at the second time, the first MOS transistor Q6 corresponding to the sixth switching tube D6 is turned on at the third time, and the second MOS transistor Q6A corresponding to the sixth switching tube D6 is turned on at the fourth time, so that it is known that Q6 is turned on hard, and Q5A is turned on soft.
When the circuit is switched from the working state 8 to the working state 7, namely the Q6A tube is turned off at the fifth moment, the Q6 tube is turned off at the sixth moment, so that the Q6 tube is turned off hard, the Q6A tube is turned off soft, the Q4 tube is turned on at the seventh moment, the Q4A tube is turned on at the eighth moment, and the Q4 and the Q4A tube are turned on soft due to the freewheeling of the D4 diode. After Q4 and Q4A are turned on, a commutation loop is provided, i.e., the D4 transistor can be matched with a smaller SIC diode, and the negative half cycle driving can be referred to fig. 6.
According to the switching control method and the switching control device, switching control is performed when the circuit of the positive half cycle and the circuit of the negative half cycle are switched to work states in a reactive power mode, so that one MOS (metal oxide semiconductor) transistor is a hard switch and the other MOS transistors are soft switches in different modes, the switching loss of the switching transistor is reduced, and the product efficiency is improved.
On the basis of the above detailed description of each embodiment corresponding to the control method of the ANPC three-level inverter topology circuit, the present invention further discloses the ANPC three-level inverter topology circuit corresponding to the above method, and fig. 10 is a structural diagram of a control device of the ANPC three-level inverter topology circuit provided in the embodiment of the present invention. As shown in fig. 10, the apparatus includes:
the acquisition module 11 is used for acquiring a current operation mode of the ANPC three-level inverter topology circuit;
the first operation module 12 is configured to, when the current operation mode is an active power mode, turn off a second MOS transistor that does not provide a switching tube corresponding to the freewheeling circuit at a first time, turn off a first MOS transistor that does not provide a switching tube corresponding to the freewheeling circuit at a second time, turn on a first MOS transistor that provides a switching tube corresponding to the freewheeling circuit at a third time, and turn on a second MOS transistor that provides a switching tube corresponding to the freewheeling circuit at a fourth time;
the second operation module 13 is configured to, when the current operation mode is the reactive power mode, turn off the second MOS transistor of the switching transistor corresponding to the freewheeling circuit at the first time, turn off the first MOS transistor of the switching transistor corresponding to the freewheeling circuit at the second time, turn on the first MOS transistor of the switching transistor corresponding to the switching transistor not providing the freewheeling circuit at the third time, and turn on the second MOS transistor of the switching transistor not providing the freewheeling circuit at the fourth time.
Since the embodiment of the apparatus portion corresponds to the above-mentioned embodiment, the embodiment of the apparatus portion is described with reference to the embodiment of the method portion, and is not described again here.
The control device of the ANPC three-level inverter topology circuit provided by the embodiment has the same beneficial effects as the control method of the ANPC three-level inverter topology circuit.
The details of the ANPC three-level inverter topology circuit, the control method and the control device provided by the present invention are described above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Claims (7)

1. An ANPC three-level inverter topology circuit is characterized by comprising a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a switch unit, a first switch tube and a second switch tube;
the cathode of the first diode is connected with the anode of the bus, the anode of the first diode is connected with the cathode of the second diode, the anode of the second diode is connected with the cathode of the third diode, and the anode of the third diode is connected with the cathode of the fourth diode and the anode of the sixth diode; the anode of the fourth diode is connected with the cathode of the bus, and the anode of the fifth diode and the cathode of the sixth diode are both connected with the midpoint of the bus; the cathode of the fifth diode is connected with the cathode of the second diode and the anode of the first diode;
the cathode of the second diode is connected with the collector of the first switching tube, the anode of the second diode is connected with the emitter of the first switching tube, the cathode of the third diode is connected with the collector of the second switching tube, and the anode of the third diode is connected with the emitter of the second switching tube; the emitter of the first switching tube is connected with the collector of the second switching tube;
the first diode, the fourth diode, the fifth diode and the sixth diode are SIC diodes and are respectively connected with one switching unit in parallel, wherein the switching unit comprises a first MOS tube and a second MOS tube, the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is used for switching control of the first diode, the fourth diode, the fifth diode and the sixth diode, and the first MOS tube is firstly switched on and then switched off compared with the second MOS tube.
2. The ANPC three-level inverter topology circuit of claim 1, wherein the first switching tube and the second switching tube are both IGBT switching tubes.
3. The ANPC three-level inverter topology circuit of claim 2, further comprising a first capacitor, a second capacitor, and a first inductor;
the first end of the first capacitor is connected with the cathode of the first diode, the second end of the first capacitor, the anode of the fifth diode and the cathode of the sixth diode are connected with the first end of the second capacitor, the second end of the second capacitor is connected with the anode of the fourth diode, and the first end of the first inductor and the anode of the second diode are connected with the cathode of the third diode.
4. A control method of an ANPC three-level inverter topology circuit, which is applied to the ANPC three-level inverter topology circuit of claim 1, comprises the following steps:
acquiring a current operation mode of the ANPC three-level inverter topology circuit;
when the current operation mode is an active power mode, turning off a second MOS tube which does not provide a diode corresponding to a freewheeling circuit at a first moment, turning off a first MOS tube which does not provide the diode corresponding to the freewheeling circuit at a second moment, turning on the first MOS tube which provides the diode corresponding to the freewheeling circuit at a third moment, and turning on the second MOS tube which provides the diode corresponding to the freewheeling circuit at a fourth moment;
and when the current operation mode is a reactive power mode, turning off a second MOS tube providing a diode corresponding to the freewheeling circuit at a first moment, turning off a first MOS tube providing the diode corresponding to the freewheeling circuit at a second moment, turning on the first MOS tube not providing the diode corresponding to the freewheeling circuit at a third moment, and turning on the second MOS tube not providing the diode corresponding to the freewheeling circuit at a fourth moment.
5. The ANPC control method of the three-level inverter topology circuit of claim 4, wherein when the current operating mode is an active power mode, the method further comprises turning off a second MOS transistor not providing a diode corresponding to the freewheel loop at a first time, turning off a first MOS transistor not providing the diode corresponding to the freewheel loop at a second time, turning on the first MOS transistor providing the diode corresponding to the freewheel loop at a third time, and turning on the second MOS transistor providing the diode corresponding to the freewheel loop at a fourth time, and comprises:
when the current operation mode is the positive half cycle of the active power mode, turning off a second MOS tube corresponding to a first diode at the first moment, turning off a first MOS tube corresponding to the first diode at the second moment, turning on a first MOS tube corresponding to a fifth diode at the third moment, and turning on a second MOS tube corresponding to the fifth diode at the fourth moment;
when the current operation mode is the negative half cycle of the active power mode, turning off a second MOS transistor corresponding to a fourth diode at the first moment, turning off a first MOS transistor corresponding to the fourth diode at the second moment, turning on a first MOS transistor corresponding to a sixth diode at the third moment, and turning on a second MOS transistor corresponding to the sixth diode at the fourth moment.
6. The ANPC control method of the three-level inverter topology circuit of claim 4, wherein when the current operating mode is a reactive power mode, the method further comprises turning off a second MOS transistor providing the diode corresponding to the freewheel loop at a first time, turning off a first MOS transistor providing the diode corresponding to the freewheel loop at a second time, turning on a first MOS transistor not providing the diode corresponding to the freewheel loop at a third time, and turning on a second MOS transistor not providing the diode corresponding to the freewheel loop at a fourth time, and comprises:
when the current operation mode is the positive half cycle of the reactive power mode, turning off a second MOS tube corresponding to a first diode at the first moment, turning off a first MOS tube corresponding to the first diode at the second moment, turning on a first MOS tube corresponding to a fifth diode at the third moment, and turning on a second MOS tube corresponding to the fifth diode at the fourth moment;
when the current operation mode is the negative half cycle of the reactive power mode, turning off a second MOS tube corresponding to a fourth diode at the first moment, turning off a first MOS tube corresponding to the fourth diode at the second moment, turning on a first MOS tube corresponding to a sixth diode at the third moment, and turning on a second MOS tube corresponding to the sixth diode at the fourth moment.
7. A control device for an ANPC three-level inverter topology circuit, applied to the ANPC three-level inverter topology circuit of any one of claims 1 to 3, comprising:
the acquisition module is used for acquiring the current operation mode of the ANPC three-level inversion topological circuit;
the first operation module is used for turning off a second MOS (metal oxide semiconductor) transistor which does not provide a diode corresponding to the freewheeling circuit at a first moment, turning off a first MOS transistor which does not provide the diode corresponding to the freewheeling circuit at a second moment, turning on the first MOS transistor which provides the diode corresponding to the freewheeling circuit at a third moment, and turning on the second MOS transistor which provides the diode corresponding to the freewheeling circuit at a fourth moment when the current operation mode is the active power mode;
and the second operation module is used for turning off a second MOS tube providing the diode corresponding to the freewheeling circuit at a first moment, turning off a first MOS tube providing the diode corresponding to the freewheeling circuit at a second moment, turning on a first MOS tube not providing the diode corresponding to the freewheeling circuit at a third moment, and turning on a second MOS tube not providing the diode corresponding to the freewheeling circuit at a fourth moment when the current operation mode is a reactive power mode.
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